Abstract: A circuit module comprises a first circuit chip (102a) and a second circuit chip (102b). Each circuit chip comprises a signal input (104a, 104b) and a reference input (106a, 106b). A first termination resistance (112) connects the signal inputs (104a, 104b) and a second resistance (114) connects the reference inputs (106a, 106b). A first termination resistance (116) connects the second signal input (104b) to the termination voltage (120) and a second termination resistance (118) connects the second reference input (106b) to the termination voltage (120). A first ratio between the first resistance (112) and the first termination resistance (116) corresponds to a second ratio between the second resistance (114) and the second termination resistance (118).

Abstract: An apparatus for connecting an integrated circuit to a support has a circuit board having a first surface for attaching the integrated circuit and a second surface opposite to the first surface. Recesses are provided in the second surface for receiving at least portions of solder balls for electrically and mechanically connecting the circuit board to the support. Solder pads are formed within the recesses. An IC BGA package making use of such an integrated circuit can be implemented with a reduced height and improved electrical characteristics when compared to existing designs.

Abstract: An apparatus for connecting an integrated circuit to a support has a circuit board having a first surface for attaching the integrated circuit and a second surface opposite to the first surface. Recesses are provided in the second surface for receiving at least portions of solder balls for electrically and mechanically connecting the circuit board to the support. Solder pads are formed within the recesses. An IC BGA package making use of such an integrated circuit can be implemented with a reduced height and improved electrical characteristics when compared to existing designs.

Abstract: Contact elements of a plug-in mount are connected in an electrically conducting manner to conductive contact zones on a surface of a substrate after the plug-in mount has been loaded with a switching assembly and are electrically isolated from the signal lines in the unloaded state. Therefore, higher clock rates for the signals transmitted on the signal lines are made possible in not completely expanded systems having empty mounting locations.

Abstract: A circuit comprises a first supply line and a second supply line. A capacitor is arranged between the first supply line and the second supply line. The first supply line and the second supply line are inductively coupled, such that a switching current on the second supply line induces a compensating current into the first supply line. The compensating current compensates the switching current by flowing from the second supply line over the capacitor into the first supply line.

Abstract: A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal from the buffer amplifier architecture at the input and at the output of the buffer amplifier architecture, and takes the phase difference between the two signals to produce a control signal for setting the variable delay time of the delay circuits.

Abstract: The invention relates to an FBGA arrangement, comprising a substrate on which at least one chip is chip-bonded face-down, which has a central row of bonding pads connected to contact islands (landing pads) on the substrate by a bonding channel in the substrate via wire bridges, which substrate, for its part, is provided with soldering balls—arranged in an array—for contact connection to a printed circuit board, and the contact islands and the soldering balls being connected to one another via a rewiring of the substrate. The preferred embodiment of the invention is intended to provide an FBGA arrangement which supports the center pad row technology and at the same time has low electrical parasitics.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips and at least one buffer chip, which drives clock signals and command and address signals to the memory chips and also drives data signals to, and receives them from, the memory chips via a module-internal clock, address, command and data signal bus. The buffer chip forms an interface to an external memory main bus and the memory chips are arranged in at least one row.

Abstract: A microstrip line has a conductive trace and a ground conductor. The microstrip line has first regions and at least one second region between the conductive trace and the ground conductor. The first regions have a first dielectric constant and the at least one second region has a second dielectric constant which is less than the first dielectric constant of the first regions.

Abstract: A connector has a connector body, at least one contact and at least one bimetal stripe. One end of the contact is fixed to the connector body and another end of each contact extends from a surface of the connector body forming a springy contact. One end of the bimetal stripe is fixed in the connector body and another end of the bimetal stripe extends from the surface of the connector body. The bimetal stripe is arranged for moving the contact in a first or second position depending on the temperature of the bimetal stripe.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged in at least one row and at least one buffer chip which drives and receives clock signals and command and address signals to the memory chips and data signals to and from the memory chips via a clock, address, command and data bus inside the module and which forms an interface to an external primary memory bus. The semiconductor memory module has an even number of buffer chips arranged on it and all of the memory chips are connected to two respective buffer chips at least by one signal line type from a signal group and just to one of the two buffer chips by the remaining signal lines from the group.

Abstract: The present invention relates to a memory arrangement having a controller and having at least one memory device. Data signals, control signals and address signals can be transferred between the controller and the memory device. The memory arrangement is designed in such a way that the data signals can be transferred via data signal lines between the controller and the memory device. The memory arrangement is furthermore designed in such a way that the control signals and the address signals can likewise be transferred via the data signal lines between the controller and the memory device.

Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract: A memory system has a memory controller, a plurality of memory modules and a memory bus connected to the memory controller and branching into a plurality of sub-busses, each of which is connected to a memory module. A sub-bus has a diode associated therewith for isolating a memory module connected to that sub-bus from the memory bus.

Abstract: The invention relates to a semiconductor memory module having at least one memory chip and a buffer chip, which drives clock, address and command signals to the memory chip and drives data signals to, and receives them from, the memory chip via a module-internal clock, address, command and data bus. The buffer chip forms an interface to an external memory main bus. The data bus lines and/or the clock, command and address bus lines are respectively connected to the buffer chip at their two ends and are capable of being driven by the buffer chip from these two ends. Control means are being provided and set up in such a manner that they respectively match the directions of propagation of the data signals and of the clock, command and address signals on the corresponding bus lines during writing and reading.

Abstract: A circuit module has a module board and a plurality of circuit chips that are arranged on the module board. A module main bus having a plurality of lines of the circuit module branches into a plurality of sub-buses having a plurality of lines. Each of the sub-buses is connected to one of the circuit chips. Each circuit chip has an indication signal generating unit for providing an indication signal based on a combination of the signals received on the plurality of lines of the sub-bus connected to the respective circuit chip, and an indication signal output for outputting the indication signal.

Abstract: A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching assemblies, which have compatible interfaces. The connector has a plurality of receptacle devices with contact elements and internal contact connections between corresponding contact elements, as a result of which, the length of the connections between the switching assemblies is reduced, signal propagation times are shortened and a higher clock rate for operating the switching assemblies is made possible.

Abstract: An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.

Abstract: A memory module has a module board having a main surface. A plurality of memory chips is arranged on the main surface of the module board. Each memory chip has two main surfaces extending between a first end face and a second end face of the memory chip, first mounting sites mounted to the main surface of the module board, and second mounting sites spaced apart from the first mounting sites and mounted to support sites spaced apart from the module board, so that a distance between the first end face and the module board is greater than a distance between the second end face and the module board. A circuit chip suited for such a memory module has terminals for connecting a circuitry of the circuit chip to terminals on the motherboard. Moreover, conductive structures are provided on a surface of the circuit chip for connecting terminals of another circuit chip to terminals on the motherboard.

Abstract: A connector arrangement comprises first conductor teeth on a first support and second conductor teeth on a second support. A slider is provided for electrically and mechanically connecting and disconnecting respective first conductor teeth on the first support to respective second conductor teeth on the second support in the manner of a zipper.