Abstract: A phase-locked loop (PLL) circuit is configured to adjust a value of a bias voltage based on a comparison between a reference clock signal and a feedback clock signal, and an oscillator circuit is configured to provide the feedback clock signal and phase-shifted clock signals based on a value of the bias voltage. A frequency detector of the frequency detector is configured to cause an adjustment to the value of the bias voltage in response to detection of a frequency deviation between the reference clock signal and the feedback clock signal. To avoid a metastable state, the frequency detector is configured to apply an asynchronous delay to one of the reference clock signal or the feedback clock signal prior to detection of the frequency deviation.

Abstract: Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.

Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example self-trimming circuit includes a control circuit configured to, during a self-trimming operation, decode a test command signal to set a target voltage and set a voltage trim code to an initial value, and to adjust a value of the voltage trim code based on a stop signal. The example self-trimming circuit further includes a reference voltage regulator configured to receive the voltage trim code and to convert a band-gap reference voltage to an output voltage based on the voltage trim code, and a comparator configured to compare the target voltage with the output voltage and to provide the stop signal having a value based on the comparison.

Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example self-trimming circuit includes a control circuit configured to, during a self-trimming operation, decode a test command signal to set a target voltage and set a voltage trim code to an initial value, and to adjust a value of the voltage trim code based on a stop signal. The example self-trimming circuit further includes a reference voltage regulator configured to receive the voltage trim code and to convert a band-gap reference voltage to an output voltage based on the voltage trim code, and a comparator configured to compare the target voltage with the output voltage and to provide the stop signal having a value based on the comparison.

Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example apparatus includes a semiconductor device including a self-trimming circuit configured to receive a reference voltage and a test command signal. The self-trimming circuit is configured to convert the reference voltage to a target voltage based on the test command signal and further configured to adjust a voltage trim code until an internal voltage matches the target voltage to determine a trim level associated with the internal voltage.

Abstract: Methods and apparatuses are provided for self-trimming of a semiconductor device. An example apparatus includes a semiconductor device including a self-trimming circuit configured to receive a reference voltage and a test command signal. The self-trimming circuit is configured to convert the reference voltage to a target voltage based on the test command signal and further configured to adjust a voltage trim code until an internal voltage matches the target voltage to determine a trim level associated with the internal voltage.

Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. The effective resistance on the power supply wires may be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. The non-active bus wires may reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving performance of the chip.

Abstract: Devices and circuits for wiring configurations of a bus system and power supply wires in a memory chip with improved power efficiencies. For example, the effective resistance on the power supply wires can be reduced by utilizing non-active bus wires as additional power wires connected in parallel with the other supply wires. Further, these non-active bus wires can reduce or prevent parasitic couplings and cross-talk effects between neighboring sensitive wires, thereby improving the performance of the chip.

Abstract: A differential stage circuit is disclosed, which includes a differential circuit, a current source coupled to supply, when activated, an operating current to the differential circuit, and a control circuit coupled to control activation and deactivation of the current source. The differential stage circuit further includes a compensation circuit configured to supply a compensation pulse to the current source when the current source is activated.

Abstract: An integrated circuit includes a storage component, a voltage stabilizer circuit with an input configured to receive an input voltage and an output configured to provide an output voltage, and a load. The load is coupled to the output of the voltage stabilizer circuit. The integrated circuit is operable in a first and second operating state. In the first operating state, the storage component receives an input voltage and in the second operating state the input voltage is provided to the input of the voltage stabilizer circuit.

Abstract: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.

Abstract: A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.

Abstract: An integrated circuit includes a circuit for adjusting a voltage drop. The circuit includes a reference voltage node, an output node and a driver circuit coupled between the reference voltage node and the output node. The driver circuit includes an impedance causing a current flow through the driver circuit when a reference voltage is applied to the reference voltage node. A current source is coupled to the driver circuit to impress an adjustment current based on a control current such that the current flow through the driver circuit is adjusted to yield a desired voltage drop across the driver circuit.

Abstract: An integrated circuit includes a storage component, a voltage stabilizer circuit with an input configured to receive an input voltage and an output configured to provide an output voltage, and a load. The load is coupled to the output of the voltage stabilizer circuit. The integrated circuit is operable in a first and second operating state. In the first operating state, the storage component receives an input voltage and in the second operating state the input voltage is provided to the input of the voltage stabilizer circuit.

Abstract: An input receiver circuit is provided for receiving a noisy high-speed input signal and for generating a plurality of output signals that can be processed at a low acquisition speed compared to the speed of the high-speed input signal. The input receiver circuit includes an input for receiving the high-speed input signal (data), a plurality of integration elements and a switch for connecting the input to one of the plurality of integration elements for integrating the high-speed input signal. The input receiver circuit further includes a plurality of means for receiving one of the integrated high-speed input signals at a time and for outputting one of the plurality of output signals at a time, and a controller for controlling the switch.

Abstract: A circuit for transmitting a signal has a first signal line and a second signal line, wherein the second signal line is arranged adjacent to the first signal line, such that an interaction between signals being transmitted on the signal lines takes place. The circuit further comprises a first driver for driving a first signal on the first signal line, wherein the first signal comprises a delay. A second driver is configured for driving a second signal on the second signal line depending on the delay of the first signal, such that the delay of the first signal is adjusted due to the interaction of the second signal on the first signal. A method and computer program are also disclosed.

Abstract: A circuit arrangement for converting logic signal levels has a level converter and a mixing arrangement for influencing a pulse width. The level converter includes a first signal path and a second signal path each having a series circuit comprising two transistors of different conductivity types and two outputs which are each connected to a tap between the transistors which are coupled in series. In this case, the transistors of one conductivity type can be controlled by means of a push-pull signal and the transistors of the other conductivity type in a respective one of the two signal paths can be controlled by means of a signal at the output of the respective other signal path. The mixing arrangement includes two inputs and two outputs, the first input being coupled to the first output and the second input being coupled to the second output.

Abstract: A circuit for coupling a logic signal from a circuit input to a circuit output includes a parallel connection of a first circuit branch and a second circuit branch, wherein an inverter in the first branch powered as last inverter in this branch via first supply terminals, via which a first supply potential and a second supply potential are supplied, and an inverter in the second branch powered as first inverter in this branch via second supply voltage terminals, via which a second supply potential and a second reference potential are supplied, are adapted to receive the same logic value of the logic signal, wherein outputs of the two circuit branches are connected to each other and coupled to the circuit output. In such a circuit, propagation time differences of rising and falling edges, which may develop by fluctuation of various supply potentials, may be minimized.