Patents by Inventor Mutsumi Masumoto
Mutsumi Masumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923320Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.Type: GrantFiled: December 31, 2020Date of Patent: March 5, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tomoko Noguchi, Mutsumi Masumoto, Kengo Aoya, Masamitsu Matsuura
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Publication number: 20240023441Abstract: Provided is a method for manufacturing a thermoelectric conversion module that eliminates the need for supports and solder materials, allows collective and efficient production of a plurality of thin thermoelectric conversion modules, and includes the following steps (A) to (D): (A) disposing a chip of a P-type thermoelectric conversion material and a chip of an N-type thermoelectric conversion material on a support so as to be spaced apart from each other; (B) filling an insulator between the chip of the P-type thermoelectric conversion material and the chip of the N-type thermoelectric conversion material to obtain an integrated body including the chip of the P-type thermoelectric conversion material, the chip of the N-type thermoelectric conversion material, and the insulator; (C) peeling the integrated body obtained in step (B) from the support; and (D) connecting the chip of the P-type thermoelectric conversion material and the chip of the N-type thermoelectric conversion material via an electrode in theType: ApplicationFiled: October 28, 2021Publication date: January 18, 2024Applicant: LINTEC CORPORATIONInventors: Yuta SEKI, Kunihisa KATO, Wataru MORITA, Mutsumi MASUMOTO
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Publication number: 20230380288Abstract: Provided is a thin thermoelectric conversion module provided with no support base material and including: an integrated body including an insulator configured to fill a gap defined by a chip of a P-type thermoelectric conversion material and a chip of an N-type thermoelectric conversion material, the chips being alternately arranged and spaced apart from each other; a common first electrode provided on one surface of the integrated body and joining one surface of the chip of the P-type thermoelectric conversion material and one surface of the chip of the N-type thermoelectric conversion material; and a common second electrode provided on another surface of the integrated body, facing the first electrode, and joining another surface of the chip of the N-type thermoelectric conversion material and another surface of the chip of the P-type thermoelectric conversion material, in which the first electrode and the second electrode provide electrically serial connection between the chip of the P-type thermoelectricType: ApplicationFiled: October 28, 2021Publication date: November 23, 2023Applicant: LINTEC CORPORATIONInventors: Yuta SEKI, Kunihisa KATO, Wataru MORITA, Katsuhiko HORIGOME, Mutsumi MASUMOTO
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Patent number: 11410875Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).Type: GrantFiled: December 19, 2018Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
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Publication number: 20220208689Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Tomoko NOGUCHI, Mutsumi MASUMOTO, Kengo AOYA, Masamitsu MATSUURA
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Publication number: 20220108955Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.Type: ApplicationFiled: November 2, 2021Publication date: April 7, 2022Inventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
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Patent number: 11183441Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.Type: GrantFiled: March 3, 2020Date of Patent: November 23, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
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Patent number: 11183460Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.Type: GrantFiled: September 17, 2018Date of Patent: November 23, 2021Assignee: Texas Instruments IncorporatedInventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
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Patent number: 11158595Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.Type: GrantFiled: July 6, 2018Date of Patent: October 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
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Publication number: 20210134729Abstract: In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.Type: ApplicationFiled: October 31, 2019Publication date: May 6, 2021Inventors: Woochan Kim, Masamitsu Matasuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar, Hideaki Matsunaga
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Publication number: 20210125959Abstract: In some examples, a wafer chip scale package (WCSP) comprises a die; multiple electrically conductive terminals coupled to a first surface of the die; and a metal covering abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.Type: ApplicationFiled: October 24, 2019Publication date: April 29, 2021Inventors: Masamitsu MATSUURA, Kengo AOYA, Mutsumi MASUMOTO
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Publication number: 20200203219Abstract: An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Hau Thanh Nguyen, Woochan Kim, Yi Yan, Luu Thanh Nguyen, Ashok Prabhu, Anindya Poddar, Masamitsu Matsuura, Kengo Aoya, Mutsumi Masumoto
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Publication number: 20200203249Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.Type: ApplicationFiled: March 3, 2020Publication date: June 25, 2020Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
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Publication number: 20200091076Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.Type: ApplicationFiled: September 17, 2018Publication date: March 19, 2020Applicant: Texas Instruments IncorporatedInventors: Woochan Kim, Mutsumi Masumoto, Kengo Aoya, Vivek Kishorechand Arora, Anindya Poddar
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Patent number: 10580715Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.Type: GrantFiled: June 14, 2018Date of Patent: March 3, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
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Publication number: 20190385924Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.Type: ApplicationFiled: June 14, 2018Publication date: December 19, 2019Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
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Publication number: 20190013288Abstract: An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.Type: ApplicationFiled: July 6, 2018Publication date: January 10, 2019Inventors: WOOCHAN KIM, MASAMITSU MATSUURA, MUTSUMI MASUMOTO, KENGO AOYA, HAU THANH NGUYEN, VIVEK KISHORECHAND ARORA, ANINDYA PODDAR
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Publication number: 20160240392Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.Type: ApplicationFiled: April 25, 2016Publication date: August 18, 2016Inventors: Anindya Poddar, Mark Allen Gerber, Mutsumi Masumoto, Masamitsu Matsuura, Kengo Aoya, Takeshi Onogami
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Publication number: 20160005705Abstract: A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.Type: ApplicationFiled: July 1, 2014Publication date: January 7, 2016Inventor: Mutsumi Masumoto
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Publication number: 20150147845Abstract: Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.Type: ApplicationFiled: November 25, 2014Publication date: May 28, 2015Inventors: Anindya Poddar, Mark Allen Gerber, Mutsumi Masumoto, Masamitsu Matsuura, Kengo Aoya, Takeshi Onogami