Patents by Inventor Mutsumi Masumoto

Mutsumi Masumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020145198
    Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.
    Type: Application
    Filed: April 4, 2001
    Publication date: October 10, 2002
    Inventors: Kensho Murata, Mutsumi Masumoto, Kenji Masumoto
  • Publication number: 20020050653
    Abstract: In semiconductor device 10 under this invention, bonding pads 20 are lined up in a staggered pattern on the main surface of semiconductor chip 14 which is mounted on isolated substrate 12. Multiple stud bumps are stacked on top of the pads 20a which are located on the inner rows, and these stud bumps comprise stud bump stack 28. Conductive wire 22 connects the lands 18 on the isolated substrate with the corresponding bonding pads 20. The wire is formed with its beginning at the land and its end at the bonding pad. Via the stud bump stacks 28, the ends of conductive wire 22a on the inner pads are in a higher position than the ends of conductive wires 22b on the outer pads, so that the problem of neighboring conductive wires coming into contact does not occur.
    Type: Application
    Filed: July 19, 2001
    Publication date: May 2, 2002
    Inventors: Kenji Masumoto, Mutsumi Masumoto, Akira Karashima
  • Patent number: 6269999
    Abstract: A semiconductor chip mounting method to prevent the occurrence of particles created while mounting the semiconductor chip onto a substrate using ultrasonic thermocompression bonding. The mounting method of the present invention utilizing ultrasonic vibrations involves the following steps: a semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a suction hole, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and ultrasonic vibrations are applied from the suction tool to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate in order to bond said conductive bumps with said connection wires.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: August 7, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Tomohiro Okazaki, Kenji Masumoto, Mutsumi Masumoto, Katsumi Yamaguchi