Abstract: A method for fabricating packaged semiconductor devices in panel format; placing a panel-sized metallic grid with openings on an adhesive tape (292); attaching semiconductor chips—coated with a polymer layer having windows for chip terminals —face-down onto the tape (293); laminating low CTE insulating material to fill gaps between chips and grid (294); turning over assembly to place carrier under backside of chips and lamination and to remove tape (295); plasma-cleaning assembly front side, sputtering uniform metal layer across assembly (296); optionally plating metal layer (297); and patterning sputtered layer to form rerouting traces and extended contact pads for assembly (298).

Abstract: The embodiments of the invention provide a semiconductor chip mounting methods to prevent the occurrence of particles created while mounting a thin semiconductor chip onto a substrate. A semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a plurality of suction holes, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and uniform pressure is applied from the oversized bonding tool suction to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate by oversized bonding tool to keep constant pressure in order to bond said conductive bumps with said connection wires.

Abstract: Methods of connecting solder bumps located on dies to leads located on substrates are disclosed herein. One embodiment includes applying a first compression force between the solder bump and the lead; relieving the first compression force between the solder bump and the lead; and applying a second compression force between the solder bump and the lead.

Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip.

Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

Abstract: A semiconductor device assembly can include a semiconductor chip, a receiving substrate, and a spacer structure interposed between the semiconductor chip and the receiving substrate. The spacer provides an unoccupied space between a pillar and a bond finger for excess conductive material, which can otherwise flow from between the pillar and bond finger and result in a conductive short. The spacer can also provide an offset between the pillar and bond finger.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

Abstract: The objective of this invention is to provide an ultrasonic flip-chip mounting method with little variance in the formed electrode joints between a semiconductor chip and a substrate. The ultrasonic method for mounting a flip chip of the present invention may include a step for forming several bump electrodes (106) on the main surface of one side of a semiconductor chip (100) and a step for respectively bringing several projecting electrodes (106) into contact with the corresponding conductor patterns (132) on a substrate and for applying ultrasonic vibration to the semiconductor chip, where the ultrasonic vibration direction is oriented in a direction oblique to the electrode patterns (132). In this way, an effective width for joining formation W1 is greater than the width of the conductor patterns W of the electrode patterns (132).

Abstract: The objective of this invention is to present a semiconductor device manufacturing method with which the formation of voids inside an underfill resin can be prevented using a simple configuration.

Abstract: A semiconductor device has one or more semiconductor chips with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments separated from the chip by gaps; the segments have first and second surfaces, wherein the second surfaces are coplanar with the passive chip surface. Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 ?m. Reflow metals may be on the passive chip surface and the second segment surfaces.

Abstract: A semiconductor device (100) has one or more semiconductor chips (110) with active and passive surfaces, wherein the active surfaces include contact pads. The device further has a plurality of metal segments (111) separated from the chip by gaps (120); the segments have first and second surfaces, wherein the second surfaces (111b) are coplanar (130) with the passive chip surface (101b). Conductive connectors span from the chip contact pads to the respective first segment surface. Polymeric encapsulation compound (150) covers the active chip surface, the connectors, and the first segment surfaces, and are filling the gaps so that the compound forms surfaces coplanar (130) with the passive chip surface and the second segment surfaces. In this structure, the device thickness may be only about 250 ?m. Reflow metals may be on the passive chip surface and the second segment surfaces.

Abstract: The objective of this invention is to prevent the generation of defects pertaining to placement of solder balls on the terminal placement parts of the electronic part main body. The solder ball 1 has spherical core 2 and coating layer 3 that covers core 2. The coating layer 3 contains a resin. The diameter of core 2 is in the range of 30-500 ?m. The thickness of coating layer 3 is in the range of 5-100 ?m. The coating layer 3 is melted at temperature in a range of 20° C. between 150 to 300° C., and the viscosity of coating layer 3 is in the range of 0.01-50 Pa-s. After solder balls 1 are set on terminal placement parts 13a in the main body of the electronic part, reflow is performed for solder balls 1. As a result, coating layer 3 is melted first, and core 2 descends under its own weight to come into contact with the terminal placement part. Core 2 is then melted, and core 2 and terminal placement part 13a are soldered and joined to each other.

Abstract: The objective of this invention is to provide an assembling method for electronic members characterized by the fact that electronic members can be joined reliably and easily without using solder paste. The semiconductor device of the present invention has the following parts: silicon substrate 100 with circuit elements formed on it, plural protrusion-shaped metal electrodes 110A, 110B formed on silicon substrate 100, and capacitor 140 having Au-plated electrodes 142, 144. The electrodes 142, 144 of capacitor 140 are metallurgically joined to protrusion-shaped metal electrodes 110A, 110B by means of ultrasonic thermo-compression bonding.

Abstract: A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates, a stage heater for heating/heat insulating a substrate is provided, respectively, at a substrate conveying portion from a substrate waiting stage for the chip mounting section to the chip mounting section, at the chip mounting section, and at a substrate conveying portion from the chip mounting section to the substrate unloader section, and the substrate unloader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates whereupon chips are mounted.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.

Abstract: A semiconductor device has a chip (101) with gold studs (212) assembled on a tape substrate (102), which has solder balls (103) for attachment to external parts. The tape substrate (about 30 to 70 ?m thick) has on its first surface first copper contact pads (221) covered with a continuous thin nickel layer (222) of about 0.04 to 0.12 ?m thickness. Gold including stud (212) is contacting the nickel. On the second substrate surface are second copper contact pads (231) covered with an alloy layer (about 2 to 3 ?m thick) including gold, copper/tin alloys, and copper/nickel/tin alloys; the alloys are metallurgically attached to the second copper pad and substantially free of unalloyed nickel. A reflow body (103) comprising tin is metallurgically attached to the alloy layer of each second pad.

Abstract: The objective of the invention is to provide a semiconductor device manufacturing method with which the generation of burrs can be suppressed while increasing the singulation speed of the package. In a manufacturing method of a QFN package of the present invention, a molding prepared by sealing a lead frame with plural semiconductor chips carried on it en bloc with a resin; the operation comprises the following processing steps: a first singulation processing step S101 in which the molding is half-cut along the cutting plane; a de-flashing processing step S102 in which the burrs on the cut portion of the half-cut molding are removed; and a second singulation processing step S103 in which the de-flashed molding is completely cut along the cutting plane.