Patents by Inventor Patrick Fleming

Patrick Fleming has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240128982
    Abstract: A hardware accelerator device is provided with circuitry to perform one or more reversible data transforms on data based on a request and compress the transformed data to generate compressed transformed data. The hardware accelerator device generates an output including the compressed transformed data and transform metadata indicating the set of reversible data transforms applied to the compressed transformed data.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Smita Kumar, Patrick Fleming
  • Patent number: 11943207
    Abstract: Methods, systems, and use cases for one-touch inline cryptographic data security are discussed, including an edge computing device with a network communications circuitry (NCC), an enhanced DMA engine coupled to a memory device and including a cryptographic engine, and processing circuitry configured to perform a secure exchange with a second edge computing device to negotiate a shared symmetric encryption key, based on a request for data. An inline encryption command for communication to the enhanced DMA engine is generated. The inline encryption command includes a first address associated with a storage location storing the data, a second address associated with a memory location in the memory device, and the shared symmetric encryption key. The data is retrieved from the storage location using the first address, the data is encrypted using the shared symmetric encryption key, and the encrypted data is stored in the memory location using the second address.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 26, 2024
    Assignee: Intel Corporation
    Inventors: Kshitij Arun Doshi, Uzair Qureshi, Lokpraveen Mosur, Patrick Fleming, Stephen Doyle, Brian Andrew Keating, Ned M. Smith
  • Publication number: 20230412459
    Abstract: Technologies for dynamically selecting resources for virtual switching include a computing device configured to identify a present demand on processing resources of the computing device that are configured to process data associated with network packets received by the computing device. Additionally, the computing device is configured to determine a present capacity of one or more acceleration resources of the computing device and configure the virtual switch based on the present demand and the present capacity of the acceleration resources. Other embodiments are described herein.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 21, 2023
    Inventors: Ciara Loftus, Chris MacNamara, John J. Browne, Patrick Fleming, Tomasz Kantecki, John BARRY, Patrick Connor
  • Patent number: 11757647
    Abstract: A security accelerator device stores a first credential that is uniquely associated with the individual security accelerator device and represents a root of trust to a trusted entity. The device establishes a cryptographic trust relationship with a client entity that is based on the root of trust, the cryptographic trust relationship being represented by a second credential. The device receives and store a secret credential of the client entity, which is received via communication secured by the second credential. Further, the device executes a cryptographic computation using the secret client credential on behalf of the client entity to produce a computation result.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: September 12, 2023
    Assignee: Intel Corporation
    Inventors: Kapil Sood, Naveen Lakkakula, Hari K. Tadepalli, Lokpraveen Mosur, Rajesh Gadiyar, Patrick Fleming
  • Patent number: 11687264
    Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming
  • Publication number: 20230185732
    Abstract: There is disclosed a computing apparatus, including: a memory; a memory encryption controller to encrypt at least a region of the memory; and a network interface to communicatively couple the computing apparatus to a remote host; wherein the memory encryption controller is configured to send an encrypted packet decryptable via an encryption key directly from the memory to the remote host via the network interface, bypassing a network protocol stack.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Applicant: Intel Corporation
    Inventors: Weigang Li, Changzheng Wei, John Barry, Maryam Tahhan, Jonas Alexander Svennebring, Niall D. McDonnell, Alexander Leckey, Patrick Fleming, Christopher MacNamara, John Joseph Browne
  • Patent number: 11651092
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 16, 2023
    Assignee: INTEL CORPORATION
    Inventors: Brian S. Hausauer, Lokpraveen B. Mosur, Tony Hurson, Patrick Fleming, Adrian R. Pearson
  • Patent number: 11598236
    Abstract: Exhaust systems for a vehicle are provided. In one example, an exhaust system includes a muffler, a first exhaust outlet pipe fluidly coupled to a first outlet of the muffler, a second exhaust outlet pipe fluidly coupled to a second outlet of the muffler, a bypass duct fluidly coupled to a third outlet of the muffler, and a combined X-Y shaped intersection at which the first exhaust outlet pipe, the second exhaust outlet pipe, and the bypass duct are fluidly coupled to each other.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 7, 2023
    Assignee: Ford Global Technologies, LLC
    Inventors: Michael Reytsman, Ya-Juan Bemman, Patrick Fleming, Alfredo Salgado, Christopher Venglar, Raymond Morelli, Jr., Omar Yuren Mendoza Bravo, Athanasios K. Teknos
  • Patent number: 11441321
    Abstract: A work platform includes a frame and a deck. The frame has a plurality of frame members that are interconnected. The frame members define a trough that extends a length of the frame and is configured to accommodate a refueling boom of an aircraft such that the refueling boom extends through the frame within the trough. The deck is mounted to the frame to provide a stand. The deck includes a first deck panel and a second deck panel spaced apart from each other to define an opening to the trough.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: September 13, 2022
    Assignee: THE BOEING COMPANY
    Inventors: Joshua Patrick Fleming, Brian Lam
  • Patent number: 11431351
    Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: David K. Cassetti, Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar, Pradnyesh S. Gudadhe, Naveen Lakkakula, Brian Will, Atul Kwatra
  • Publication number: 20220214951
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Application
    Filed: January 5, 2021
    Publication date: July 7, 2022
    Applicant: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack
  • Patent number: 11378622
    Abstract: Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: July 5, 2022
    Assignee: Raytheon Company
    Inventors: Patrick Fleming, Mustafa Amin, James Bynes, III, Patrick Llorens, Dale D. Kachuche, Brian Clebowicz, William Rowe, Alfredo Lara, Neal Pollack
  • Publication number: 20220141133
    Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments.
    Type: Application
    Filed: January 18, 2022
    Publication date: May 5, 2022
    Inventors: Eliel LOUZOUN, Manasi DEVAL, Stephen DOYLE, Noam ELATI, Patrick FLEMING, Gregory BOWERS
  • Publication number: 20220099007
    Abstract: Exhaust systems for a vehicle are provided. In one example, an exhaust system includes a muffler, a first exhaust outlet pipe fluidly coupled to a first outlet of the muffler, a second exhaust outlet pipe fluidly coupled to a second outlet of the muffler, a bypass duct fluidly coupled to a third outlet of the muffler, and a combined X-Y shaped intersection at which the first exhaust outlet pipe, the second exhaust outlet pipe, and the bypass duct are fluidly coupled to each other.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Inventors: Michael Reytsman, Ya-Juan Bemman, Patrick Fleming, Alfredo Salgado, Christopher Venglar, Raymond Morelli, JR., Omar Yuren Mendoza Bravo, Athanasios K. Teknos
  • Publication number: 20220103530
    Abstract: Examples described herein relate to a network interface device that includes circuitry, configured to perform encryption of data, generate one or more packets from the encrypted data, cause transmission of the one or more packets with the encrypted data, manage reliability of transport of the transmitted one or more packets with the encrypted data, and share protocol state information between a host system and the network interface device using connectivity based on user space accessible queues.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 31, 2022
    Inventors: Daniel DALY, Anjali Singhai JAIN, Yadong LI, Stephen DOYLE, Naru Dames SUNDAR, Chih-Jen CHANG, Sailesh BISSESSUR, Andrew CUNNINGHAM, Edwin VERPLANKE, Patrick FLEMING
  • Patent number: 11269786
    Abstract: Systems, apparatus, and/or methods to provide memory data protection. In one example, authenticated encryption may be enhanced via a modification to an authentication code that is associated with encrypted data. The authentication code may be modified, for example, with a nonce value generated for a particular write to memory Decrypted data, generated from the encrypted data, may then be validated based on a modified authentication code. Moreover, data freshness control for data stored in the memory may be provided based on iterative authentication and re-encryption. In addition, a counter used to provide a nonce value may be managed to reduce a size of the counter and/or a growth of the counter.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Anatoli Bolotov, Mikhail Grinchuk, David M. Durham, Patrick Fleming
  • Patent number: 11271856
    Abstract: An apparatus, a method and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Eliel Louzoun, Manasi Deval, Stephen Doyle, Noam Elati, Patrick Fleming, Gregory Bowers
  • Publication number: 20220021540
    Abstract: A security accelerator device stores a first credential that is uniquely associated with the individual security accelerator device and represents a root of trust to a trusted entity. The device establishes a cryptographic trust relationship with a client entity that is based on the root of trust, the cryptographic trust relationship being represented by a second credential. The device receives and store a secret credential of the client entity, which is received via communication secured by the second credential. Further, the device executes a cryptographic computation using the secret client credential on behalf of the client entity to produce a computation result.
    Type: Application
    Filed: May 14, 2021
    Publication date: January 20, 2022
    Inventors: Kapil Sood, Naveen Lakkakula, Hari K. Tadepalli, Lokpraveen Mosur, Rajesh Gadiyar, Patrick Fleming
  • Publication number: 20210281618
    Abstract: In one embodiment, a system includes a device and a host. The device includes a device stream buffer. The host includes a processor to execute at least a first application and a second application, a host stream buffer, and a host scheduler. The first application is associated with a first transmit streaming channel to stream first data from the first application to the device stream buffer. The first transmit streaming channel has a first allocated amount of buffer space in the device stream buffer. The host scheduler schedules enqueue of the first data from the first application to the first transmit streaming channel based at least in part on availability of space in the first allocated amount of buffer space in the device stream buffer. Other embodiments are described and claimed.
    Type: Application
    Filed: May 6, 2021
    Publication date: September 9, 2021
    Inventors: LOKPRAVEEN MOSUR, ILANGO GANGA, ROBERT CONE, KSHITIJ ARUN DOSHI, JOHN J. BROWNE, MARK DEBBAGE, STEPHEN DOYLE, PATRICK FLEMING, DODDABALLAPUR JAYASIMHA
  • Publication number: 20210264042
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.
    Type: Application
    Filed: April 22, 2021
    Publication date: August 26, 2021
    Applicant: INTEL CORPORATION
    Inventors: BRIAN S. HAUSAUER, Lokpraveen B. Mosur, Tony Hurson, Patrick Fleming, Adrian R. Pearson