Abstract: The invention provides a process for plasma etching silicon carbide with selectivity to an overlapping and/or underlying dielectric layer of material. The etching gas includes a hydrogen-containing fluorocarbon gas such as CH3F, an oxygen-containing gas such as O2 and an optional carrier gas such as Ar. The dielectric material can comprise silicon dioxide, silicon nitride, silicon oxynitride or various low-k dielectric materials including organic low-k materials. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrates.

Abstract: A method of etching a stack using a fluorine containing gas and an ammonia containing gas is provided. Generally, the stack is placed in a plasma processing chamber. A fluorine containing gas is flowed into the plasma processing chamber. An ammonia containing gas is flowed into the plasma processing chamber. A plasma is generated. The stack is then etched.

Abstract: A method of etching a stack is provided. Generally, a trench patterned resist layer is placed over a dielectric layer of the stack. A trench is partially etched into the dielectric layer. A simultaneous stripping of the trench patterned resist layer, etching the barrier layer, and etching the trench is then performed. As a result an etch stack may be provided with less damage. The method may be used to provide a dual damascene structure. The dual damascene structure may be provided by etching a via before placing the trench patterned resist layer over the dielectric layer of the stack.

Abstract: A method of forming a contact opening between two conductive features over a semiconductor substrate. Oxide spacers are formed adjacent to the conductive features. A doped oxide layer is then deposited over the semiconductor substrate. Finally, the contact opening is etched through the doped oxide layer between the conductive features such that the oxide spacers are exposed within the contact opening.

Abstract: A method of forming a contact opening between two conductive features over a semiconductor substrate. Oxide spacers are formed adjacent to the conductive features. A doped oxide layer is then deposited over the semiconductor substrate. Finally, the contact opening is etched through the doped oxide layer between the conductive features such that the oxide spacers are exposed within the contact opening.

Abstract: In the manufacture of memory cells, horizontal etching is controlled in a manner which prevents the formation of stringers between adjacent cells without undercutting the sidewalls of a memory cell.

Abstract: There is disclosed herein a technique for manufacturing a group of memory cells or devices on a common oxide coated silicon substrate such that the cells are arranged in rows and columns with row and column spaces separating the individual cells from one another. Each of the cells includes an array of different layers on the oxide coated top surface of the substrate including, in particular, the polysilicon layer. As disclosed, a method is provided for preventing the formation of polysilicon stringers between individual cells during their manufacture. This method is carried out by first forming the columns before the rows are formed such that continuous sidewalls of the columns are exposed to the ambient surroundings. Thereafter, these sidewalls are coated with protective layers, specifically layers of nitride.

Abstract: A calibration wafer for a patterned wafer scanner is constructed from a substrate of semiconductor material, typically silicon, in which a pattern of features has been etched into the periphery of each die by means of photolithographic techniques. Next, a layer or layers of films composed of materials which are typically used during the fabrication of integrated circuits are deposited. Then a substantially uniform distribution of particles of a known material and size distribution is deposited onto the wafer. A second embodiment of the calibration wafer is one in which a layer or layers of film are first deposited onto a substrate. Then a pattern of features is etched into the periphery of the film covering each die by means of photolithographic techniques. After this step, a substantially uniform distribution of particles is deposited. A method of using such a calibration wafer to calibrate a patterned wafer scanner is also disclosed.

Abstract: In the manufacture of memory cells, horizontal etching is controlled in a manner which prevents the formation of stringers between adjacent cells without undercutting the sidewalls of a memory cell.