Abstract: A method for forming fin structures is provided. Sacrificial structures are provided on a substrate. Fin structures are formed on the sides of the sacrificial structures. The forming of the fin structures comprises a plurality of cycles, wherein each cycle comprises a fin deposition phase and a fin profile shaping phase. The sacrificial structure is removed.

Abstract: A method for forming etch features in an etch layer over a substrate and below an organic ARC layer, which is below an immersion lithography photoresist mask is provided. The substrate with the etch layer, organic ARC layer, and immersion lithography photoresist mask is placed into a processing chamber. The organic ARC layer is opened. The organic ARC layer opening comprises flowing an organic ARC open gas mixture into the processing chamber, wherein the organic ARC open gas mixture comprises an etchant gas and a polymerization gas comprising CO, forming an organic ARC open plasma from the organic ARC open gas mixture, etching the organic ARC layer with the organic ARC open plasma until the organic ARC layer is opened, and stopping the flow of organic ARC open gas mixture into the processing chamber before the etch layer is completely etched.

Abstract: A vacuum plasma processor includes a chamber having a grounded wall and an outlet port. Plasma is excited at a first RF frequency in a chamber region spaced from the wall and outlet port. A structure confines the plasma to the region while enabling gas to flow from the region to the outlet port. RF electric power at a second frequency connected to the confining structure causes the confining structure to be at a potential different from ground to increase the size of a sheath between the plasma and confining structure and increase the confining structure effectiveness. The region includes an electrode connected to ground by a circuit that is series resonant to the first frequency and includes capacitance of the sheath.

Abstract: A method for aligning a reticle is provided. A first patterned layer with a first alignment grid is formed. Sidewall layers are formed over the first patterned layer to perform a first shrink. The first alignment grid after shrink is etched into an etch layer to form an etched first alignment grid. The patterned layer is removed. An optical pattern of a second alignment grid aligned over the etched first alignment grid is measured. The optical pattern is used to determine whether the second alignment grid is aligned over the etched first alignment grid.

Abstract: An inductively coupled power (ICP) plasma processing chamber for forming semiconductor features is provided. A plasma processing chamber is provided, comprising a vacuum chamber, at least one antenna adjacent to the vacuum chamber for providing inductively coupled power in the vacuum chamber, a substrate support for supporting a silicon substrate within the plasma processing chamber, a pressure regulator, a gas inlet for providing gas into the plasma processing chamber, and a gas outlet for exhausting gas from the plasma processing chamber. A gas distribution system is in fluid connection with the gas inlet for providing a first gas and a second gas, wherein the gas distribution system can substantially replace one of the first gas and the second gas in the plasma zone with the other of the first gas and the second gas within a period of less than 5 seconds.

Abstract: A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer.

Abstract: A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.

Abstract: A vacuum plasma processor includes a chamber having a grounded wall and an outlet port. Plasma is excited at a first RF frequency in a chamber region spaced from the wall and outlet port. A. structure confines the plasma to the region while enabling gas to flow from the region to the outlet port. RF electric power at a second frequency connected to the confining structure causes the confining structure to be at a potential different from ground to increase the size of a sheath between the plasma and confining structure and increase the confining structure effectiveness. The region includes an electrode connected to ground by a circuit that is series resonant to the first frequency and includes capacitance of the sheath.

Abstract: A method for implanting a dopant in a substrate is provided. A patterned photoresist mask is formed over the substrate, wherein the patterned photoresist mask has patterned photoresist mask features. A protective layer is deposited on the patterned photoresist mask by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over surfaces of the patterned mask of photoresist material and a profile shaping phase for providing vertical sidewalls. A dopant is implanted into the substrate using an ion beam. The protective layer and photoresist mask are removed.

Abstract: A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed.

Abstract: A method for etching an etch layer formed on a substrate is provided. A first photoresist (PR) mask with first mask features is provided on the etch layer. A protective coating is provided on the first PR mask by a process including at least one cycle. Each cycle includes (a) a deposition phase for depositing a deposition layer over the surface of the first mask features using a deposition gas, and (b) a profile shaping phase for shaping the profile of the deposition layer using a profile shaping gas. A liquid PR material is applied over the first PR mask having the protective coating. The PR material is patterned into a second mask features, where the first and second mask features form a second PR mask. The etch layer is etched though the second PR mask.

Abstract: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

Abstract: A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.

Abstract: An apparatus comprising computer readable media is provided. The computer readable media comprises computer readable code for receiving a feature layout and computer readable code for applying shrink correction on the feature layout. The computer readable code for applying the shrink correction comprises providing corner cutouts, adjusting line width and length, shape modifications, etc. for forming features in a patterned layer.

Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Abstract: A method for etching a dielectric layer disposed below an antireflection layer (ARL) is provided. The method comprises (a) forming a patterned mask with mask features over the ARL, the mask having isolated areas and dense areas of the mask features, (b) trimming and opening, and (c) etching the dielectric layer using the trimmed mask. The trimming and opening comprises a plurality of cycles, where each cycle includes (b1) a trim-etch phase which etches the ARL in a bottom of the mask features and selectively trims the isolated areas of the mask with respect to the dense areas, and (b2) a deposition-etch phase which deposits a deposition layer on the mask while further etching the ARL in the bottom of the mask features. The trimming and opening result in a net trimming of the mask in the isolated areas.

Abstract: A method for etching a dielectric layer is provided. A patterned mask with mask features is formed over a dielectric layer. The mask has isolated areas and dense areas of the mask features. The mask is trimmed by a plurality of cycles, where each cycle includes depositing a deposition layer, and selectively etching the deposition layer and the patterned mask. The selective etching selectively trims the isolated areas of the mask with respect to the dense areas of the mask. The dielectric layer is etched using the thus trimmed mask. The mask is removed.

Abstract: A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.

Abstract: A method for processing a substrate is provided. The substrate is placed in a process chamber. A gas is provided from a gas source to the process chamber. A plasma is generated from the gas in the process chamber. The gas flows through a gap adjacent to at least one confinement ring to provide physical confinement of the plasma. Magnetic confinement of the plasma is provided to enhance the physical confinement of the plasma.

Abstract: A method and apparatus is provided for using a plasma generated from a processing gas mixture including H2O to efficiently strip photoresist material without causing significant damage to exposed, underlying low k dielectric material. The method includes disposing the processing gas mixture including the H2O over the wafer. The processing gas mixture including the H2O is then transformed into a plasma. The plasma serves to remove the photoresist material from the substrate without adversely affecting the exposed low k dielectric material.