Patents by Inventor Satoru Okamoto

Satoru Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11943929
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takanori Matsuzaki, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 11922690
    Abstract: A data processing system, a data processing device, and a data processing method are provided. The data processing system includes a wearable device including a display means and an imaging means and a database that is connected to the wearable device through a network. The database includes at least one of pieces of information on a cooking recipe, a cooking method, and a material. The wearable device detects a first material by the imaging means. The wearable device collects information on the first material from the database. When the first material exists in a specific region in an imaging range of the imaging means, the information on the first material is displayed on the display means. When the first material does not exist in the specific region, the information on the first material is not displayed on the display means.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuro Kanemura, Taisuke Higashi, Hiroya Hibino, Atsuya Tokinosu, Hiromichi Godo, Satoru Okamoto
  • Publication number: 20240065600
    Abstract: An emotion estimating device, an emotion estimating system, and an emotion estimating method capable of estimating an emotion of a subject based on information obtained from daily activities can be provided. An emotion estimating device includes an interface that receives input of walking data of a subject measured by a measurement device and emotion data obtained by quantifying the emotion of the subject, a storage that stores the walking data and the emotion data, and an computer that obtains corresponding data in which a plurality of walking parameters included in the walking data stored in the storage are associated with the emotion data. When the interface newly receives the input of the walking data, the computer estimates the emotion of the subject from the plurality of walking parameters included in the newly received walking data, and outputs information indicating the estimated emotion of the subject.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 29, 2024
    Applicant: ASICS CORPORATION
    Inventors: Toshiaki OKAMOTO, Ken KUSANO, Shunsuke YAMAGATA, Masaru ICHIKAWA, Satoru ABE
  • Publication number: 20230352090
    Abstract: A highly reliable memory device is provided. The memory device includes a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor. At least third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in this order on an inner surface of the opening. The seventh conductor is provided between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 2, 2023
    Inventors: Kazuki TSUDA, Hiromichi GODO, Satoru OHSHITA, Hitoshi KUNITAKE, Satoru OKAMOTO
  • Patent number: 11791201
    Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: October 17, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Yuta Iida, Satoru Okamoto
  • Patent number: 11776966
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: October 3, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Motomu Kurata, Shinya Sasagawa, Satoru Okamoto, Shunpei Yamazaki
  • Publication number: 20230309308
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Application
    Filed: March 31, 2023
    Publication date: September 28, 2023
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Kiyoshi KATO, Satoru OKAMOTO
  • Patent number: 11749445
    Abstract: A laminated coil component includes an element body, a coil, and a pair of conductors. The pair of conductors is disposed on the element body. Each of the pair of conductors has an L shape when viewed from the third direction. Each of the pair of conductors includes a first conductor portion and a second conductor portion. The first conductor portion is disposed on one of first side faces. The second conductor portion is disposed on a pair of end faces. The coil includes a first coil portion and a second coil portion. The first coil portion includes a first straight portion and a pair of second straight portions. The pair of second straight portions is connected to both ends of the first straight portion. The second coil portion is curved as a whole.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: September 5, 2023
    Assignee: TDK CORPORATION
    Inventors: Hajime Kato, Yuto Shiga, Kazuya Tobita, Youichi Kazuta, Yuya Ishima, Satoru Okamoto, Shunji Aoki
  • Patent number: 11626422
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: April 11, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takanori Matsuzaki, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 11569020
    Abstract: A laminated coil component 1 includes an element body 2, a coil 8 disposed in the element body 2, and a first external electrode 4 and a second external electrode 5, and at least a part of the coil 8 is disposed in a first region A1 and a second region A2 when seen in a facing direction of the pair of side surfaces 2e and 2f, and the coil 8 is not disposed in a third region A3 and a fourth region A4 when seen in the facing direction of the pair of side surfaces 2e and 2f.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: January 31, 2023
    Assignee: TDK CORPORATION
    Inventors: Hajime Kato, Satoru Okamoto, Masahiro Kato, Makoto Yoshino, Kazuya Tobita, Yuto Shiga, Youichi Kazuta, Noriaki Hamachi
  • Publication number: 20230014711
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Application
    Filed: September 19, 2022
    Publication date: January 19, 2023
    Inventors: Satoru OKAMOTO, Shinya SASAGAWA
  • Publication number: 20220367509
    Abstract: A semiconductor device having a large storage capacity per unit area is provided.
    Type: Application
    Filed: June 23, 2020
    Publication date: November 17, 2022
    Inventors: Shunpei YAMAZAKI, Tatsuya ONUKI, Satoru OKAMOTO
  • Publication number: 20220351509
    Abstract: A data processing system, a data processing device, and a data processing method are provided. The data processing system includes a wearable device including a display means and an imaging means and a database that is connected to the wearable device through a network. The database includes at least one of pieces of information on a cooking recipe, a cooking method, and a material. The wearable device detects a first material by the imaging means. The wearable device collects information on the first material from the database. When the first material exists in a specific region in an imaging range of the imaging means, the information on the first material is displayed on the display means. When the first material does not exist in the specific region, the information on the first material is not displayed on the display means.
    Type: Application
    Filed: June 12, 2020
    Publication date: November 3, 2022
    Inventors: Takuro KANEMURA, Taisuke HIGASHI, Hiroya HIBINO, Atsuya TOKINOSU, Hiromichi GODO, Satoru OKAMOTO
  • Patent number: 11489065
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shinya Sasagawa
  • Patent number: 11488761
    Abstract: A laminated electronic component includes an element body and a conductor. The element body is formed by laminating a plurality of element-body layers. The element body has a first face, a second face, and a pair of third faces. The conductor is disposed on the element body and has an L shape. The conductor has an exposed face exposed on the first face and the second face. The exposed face includes a plurality of divided regions divided by the element body. The length of each divided region in a dividing direction is longer than a distance with which the plurality of divided regions is separated from each other and longer than a distance with which the exposed face and the pair of third faces are separated from each other.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 1, 2022
    Assignee: TDK CORPORATION
    Inventors: Yuto Shiga, Hajime Kato, Kazuya Tobita, Youichi Kazuta, Yuya Ishima, Satoru Okamoto, Shunji Aoki
  • Publication number: 20220262858
    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
    Type: Application
    Filed: July 31, 2020
    Publication date: August 18, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO, Hiromichi GODO, Kazuki TSUDA, Hitoshi KUNITAKE
  • Publication number: 20220262438
    Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.
    Type: Application
    Filed: July 22, 2020
    Publication date: August 18, 2022
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Tatsuya ONUKI, Yuki OKAMOTO, Hideki UOCHI, Satoru OKAMOTO
  • Publication number: 20220222293
    Abstract: A search system and a search method are provided. The search system includes a means to input first circuit diagram information to a terminal, a database in which second circuit diagram information is registered, a means to convert the input first circuit diagram information into a first graph, an arithmetic means to calculate similarity between the first graph and a second graph based on the second circuit diagram information, and a means to display the similarity on the terminal.
    Type: Application
    Filed: April 30, 2020
    Publication date: July 14, 2022
    Inventors: Hiromichi GODO, Takahiro FUKUTOME, Satoru OKAMOTO
  • Publication number: 20220199831
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Application
    Filed: February 3, 2022
    Publication date: June 23, 2022
    Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
  • Publication number: 20220076876
    Abstract: A laminated coil component includes an element body, a coil, and a pair of conductors, the pair of conductors is disposed on the element body. Each of the pair of conductors has an L shape when viewed from the third direction. Each of the pair of conductors includes a first conductor portion and a second conductor portion. The first conductor portion is disposed on one of first side faces. The second conductor portion is disposed on a pair of end faces. The coil includes a first coil portion and a second coil portion. The first coil portion includes a first straight portion and a pair of second straight portions. The pair of second straight portions is connected to both ends of the first straight portion. The second coil portion is curved as a whole.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TDK CORPORATION
    Inventors: Hajime KATO, Yuto SHIGA, Kazuya TOBITA, Youichi KAZUTA, Yuya ISHIMA, Satoru OKAMOTO, Shunji AOKI