Patents by Inventor Satoru Okamoto

Satoru Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190092711
    Abstract: A method for producing 1,2-dichloro-3,3,3-trifluoropropene according to the present invention includes the step of reacting 1,1,2,3,3-pentachloropropene with a fluorinating agent where hydrogen fluoride is used as the fluorinating agent.
    Type: Application
    Filed: April 10, 2017
    Publication date: March 28, 2019
    Inventors: Kei MATSUNAGA, Hideaki IMURA, Masatomi KANAI, Masahiko TANI, Naoto TAKADA, Kohei SUMIDA, Satoru OKAMOTO
  • Patent number: 10215455
    Abstract: A heat transmission method using a high-temperature heat pump system accommodating a heat transmission composition includes the step of evaporating the heat transmission composition, the step of compressing the heat transmission composition, the step of condensing the heat transmission composition, and the step of decreasing the pressure of the heat transmission composition at a temperature of 70° C. or higher, which are performed sequentially. The heat transmission composition contains cis-1,3,3,3-tetrafluoropropene at a mass ratio of 95.0% by mass or more and 99.9% by mass or less, and contains trans-1,3,3,3-tetrafluoropropene or 2,3,3,3-tetrafluoropropene at a mass ratio of 0.1% by mass or more and 5.0% by mass or less; and the heat transmission composition has a condensation temperature of 70° C. or higher.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: February 26, 2019
    Assignee: CENTRAL GLASS COMPANY, LIMITED
    Inventors: Yoshio Nishiguchi, Satoru Okamoto, Masatomi Kanai
  • Publication number: 20190043655
    Abstract: A laminated coil component includes an element body, a coil, and a pair of conductors. The pair of conductors is disposed on the element body. Each of the pair of conductors has an L shape when viewed from the third direction. Each of the pair of conductors includes a first conductor portion and a second conductor portion. The first conductor portion is disposed on one of first side faces. The second conductor portion is disposed on a pair of end faces. The coil includes a first coil portion and a second coil portion. The first coil portion includes a first straight portion and a pair of second straight portions. The pair of second straight portions is connected to both ends of the first straight portion. The second coil portion is curved as a whole.
    Type: Application
    Filed: July 26, 2018
    Publication date: February 7, 2019
    Applicant: TDK CORPORATION
    Inventors: Hajime KATO, Yuto SHIGA, Kazuya TOBITA, Youichi KAZUTA, Yuya ISHIMA, Satoru OKAMOTO, Shunji AOKI
  • Publication number: 20190031583
    Abstract: The present invention provides a method for efficiently producing 1-chloro-3,3,3-trifluoropropene from a low-reactivity intermediate product. More specifically, provided is a method for producing trans-1-chloro-3,3,3-trifluoropropene, characterized by reacting a halogenated C3 hydrocarbon compound represented by the following general formula (1) with hydrogen fluoride in a gas phase in the presence of a solid catalyst and chlorine C3HXClYFZ ??(1) wherein X is 2 or 3; when X=2, Y is an integer of 1 to 4, Z is an integer of 0 to 3, and Y+Z=4; and, when X=3, Y is an integer of 1 to 5, Z is an integer of 0 to 4, and Y+Z=5; provided that the general formula (1) represents any halogenated C3 hydrocarbon compound other than trans-1-chloro-3,3,3-trifluoropropene.
    Type: Application
    Filed: January 12, 2017
    Publication date: January 31, 2019
    Inventors: Satoru OKAMOTO, Koji UEDA, Takamasa KITAMOTO
  • Patent number: 10181531
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Satoru Okamoto, Shunpei Yamazaki
  • Publication number: 20190006386
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Application
    Filed: June 11, 2018
    Publication date: January 3, 2019
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Kiyoshi KATO, Satoru OKAMOTO
  • Publication number: 20190006084
    Abstract: A laminated electronic component includes an element body and a conductor. The element body is formed by laminating a plurality of element-body layers. The element body has a first face, a second face, and a pair of third faces. The conductor is disposed on the element body and has an L shape. The conductor has an exposed face exposed on the first face and the second face. The exposed face includes a plurality of divided regions divided by the element body. The length of each divided region in a dividing direction is longer than a distance with which the plurality of divided regions is separated from each other and longer than a distance with which the exposed face and the pair of third faces are separated from each other.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 3, 2019
    Applicant: TDK CORPORATION
    Inventors: Yuto SHIGA, Hajime KATO, Kazuya TOBITA, Youichi KAZUTA, Yuya ISHIMA, Satoru OKAMOTO, Shunji AOKI
  • Patent number: 10164120
    Abstract: A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: December 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Katsuaki Tochibayashi, Satoru Okamoto, Akihisa Shimomura
  • Publication number: 20180342341
    Abstract: A laminated electronic component includes an element body and a pair of conductors. The element body is formed by laminating a plurality of element-body layers in a first direction. The pair of conductors is formed by laminating a plurality of conductor layers in the first direction. The pair of conductors is provided to the element body in such a way as to be separated from each other in a second direction orthogonal to the first direction. At a cross section orthogonal to the first direction, the pair of conductors has an uneven portion and the element body has an uneven portion engaged with the uneven portion of the pair of conductors.
    Type: Application
    Filed: May 24, 2018
    Publication date: November 29, 2018
    Applicant: TDK CORPORATION
    Inventors: Shunji AOKI, Yuya ISHIMA, Hajime KATO, Yuto SHIGA, Kazuya TOBITA, Youichi KAZUTA, Satoru OKAMOTO
  • Publication number: 20180330855
    Abstract: A laminated coil component includes an element assembly formed by laminating a plurality of insulation layers and a coil unit formed inside the element assembly by a plurality of coil conductors. The element assembly includes a coil unit arrangement layer which has the coil unit arranged therein, and at least a pair of shape retention layers which is provided to have the coil unit arrangement layer interposed therebetween to retain a shape of the coil unit arrangement layer. The shape retention layer is made from glass-ceramic containing SrO, and a softening point of the coil unit arrangement layer is lower than a softening point or a melting point of the shape retention layer.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Applicant: TDK CORPORATION
    Inventors: Takahiro SATO, Yuya ISHIMA, Shusaku UMEMOTO, Takashi SUZUKI, Satoru OKAMOTO, Yoshikazu SAKAGUCHI
  • Patent number: 10101065
    Abstract: A heat transmission method using a heat pump system according to the present invention uses a heat transmission medium containing at least one compound represented by general formula (1). In the formula, R1 is a CHmF3-m group, m is an integer of 0 or more and 3 or less, R2, R3 and R4 are each independently a fluorine atom, a chlorine atom, a bromine atom, an iodine atom or a hydrogen atom, and at least one fluorine atom is contained in a molecule. The heat transmission method includes (A) step of gasifying the heat transmission medium; (B) step of compressing the heat transmission medium into a supercritical state; (C) step of causing heat exchange between the heat transmission medium in the supercritical state and a medium to be heated; and (D) step of decreasing the pressure of the heat transmission medium.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 16, 2018
    Assignee: CENTRAL GLASS COMPANY, LIMITED
    Inventors: Yoshio Nishiguchi, Satoru Okamoto, Masatomi Kanai
  • Publication number: 20180254291
    Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Shunpei YAMAZAKI, Yuta ENDO, Kiyoshi KATO, Satoru OKAMOTO
  • Publication number: 20180248043
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Application
    Filed: April 23, 2018
    Publication date: August 30, 2018
    Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
  • Publication number: 20180248010
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 30, 2018
    Inventors: Yuta ENDO, Hideomi SUZAWA, Kazuya HANAOKA, Shinya SASAGAWA, Satoru OKAMOTO
  • Patent number: 10043608
    Abstract: A laminated coil component includes an element assembly formed by laminating a plurality of insulation layers and a coil unit formed inside the element assembly by a plurality of coil conductors. The element assembly includes a coil unit arrangement layer which has the coil unit arranged therein, and at least a pair of shape retention layers which is provided to have the coil unit arrangement layer interposed therebetween to retain a shape of the coil unit arrangement layer. The shape retention layer is made from glass-ceramic containing SrO, and a softening point of the coil unit arrangement layer is lower than a softening point or a melting point of the shape retention layer.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 7, 2018
    Assignee: TDK CORPORATION
    Inventors: Takahiro Sato, Yuya Ishima, Shusaku Umemoto, Takashi Suzuki, Satoru Okamoto, Yoshikazu Sakaguchi
  • Publication number: 20180215689
    Abstract: A method for isomerizing a hydrohalofluoroolefin isomer to produce a corresponding hydrohalofluoroolefin isomer includes a step contacting a composition that contains at least a hydrohalofluoroolefin isomer and that has been adjusted to 100 ppm or lower in moisture concentration, with a catalyst in a gas phase, thereby obtaining a product. This method makes it possible to suppress the catalyst performance lowering.
    Type: Application
    Filed: May 27, 2016
    Publication date: August 2, 2018
    Applicant: Central Glass Company, Limited
    Inventors: Takamasa KITAMOTO, Satoru OKAMOTO, Masahiko TANI, Masatomi KANAI, Kohei SUMIDA
  • Publication number: 20180210561
    Abstract: Provided is an input unit and input method for an information terminal for easy input work and avoiding an operating error. Included are a support, an input unit including a laser device on the support, an information terminal including a sensor in a display portion, and a switch connected with or without a wire to at least one of the laser device and the information terminal. A desired region of the display portion is irradiated with laser light output from the input unit. Information is input to the region by operation of the switch in the state where the region is irradiated with laser light.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 26, 2018
    Inventors: Isamu SHIGEMORI, Satoru OKAMOTO
  • Publication number: 20180151742
    Abstract: A minute transistor is provided. Alternatively, a transistor with low parasitic capacitance is provided. Alternatively, a transistor having high frequency characteristics is provided. Alternatively, a novel transistor is provided. A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.
    Type: Application
    Filed: May 18, 2016
    Publication date: May 31, 2018
    Inventors: Motomu KURATA, Shinya SASAGAWA, Katsuaki TOCHIBAYASHI, Satoru OKAMOTO, Akihisa SHIMOMURA
  • Patent number: 9978774
    Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: May 22, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Kiyoshi Kato, Satoru Okamoto
  • Publication number: 20180138213
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Ryota HODO, Motomu KURATA, Shinya SASAGAWA, Satoru OKAMOTO, Shunpei YAMAZAKI