Patents by Inventor Satoru Okamoto

Satoru Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200010388
    Abstract: A manufacturing method of 1-chloro-3,3,3-trifluoropropene (1233zd) is provided. This manufacturing method includes a reaction in which a halogenated hydrocarbon compound having a carbon number of 3 and represented by a general formula (1) is heated: CFaCl3-a—CH2—CHFbCl2-b??(1) In the formula, a is an integer from 0 to 2, b is 1 or 2 when a=0, b is 0 or 1 when a=1, and b is 0 when a=2.
    Type: Application
    Filed: September 17, 2019
    Publication date: January 9, 2020
    Inventors: Masamune OKAMOTO, Kohei SUMIDA, Kei MATSUNAGA, Yoshio NISHIGUCHI, Satoru OKAMOTO
  • Patent number: 10519083
    Abstract: The present invention provides a method for efficiently producing 1-chloro-3,3,3-trifluoropropene from a low-reactivity intermediate product. More specifically, provided is a method for producing trans-1-chloro-3,3,3-trifluoropropene, characterized by reacting a halogenated C3 hydrocarbon compound represented by the following general formula (1) with hydrogen fluoride in a gas phase in the presence of a solid catalyst and chlorine C3HXClYFZ??(1) wherein X is 2 or 3; when X=2, Y is an integer of 1 to 4, Z is an integer of 0 to 3, and Y+Z=4; and, when X=3, Y is an integer of 1 to 5, Z is an integer of 0 to 4, and Y+Z=5; provided that the general formula (1) represents any halogenated C3 hydrocarbon compound other than trans-1-chloro-3,3,3-trifluoropropene.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: December 31, 2019
    Assignee: Central Glass Company, Limited
    Inventors: Satoru Okamoto, Koji Ueda, Takamasa Kitamoto
  • Publication number: 20190393079
    Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 26, 2019
    Inventors: Motomu KURATA, Shinya SASAGAWA, Ryota HODO, Yuta IIDA, Satoru OKAMOTO
  • Patent number: 10513479
    Abstract: A method for isomerizing a hydrohalofluoroolefin isomer to produce a corresponding hydrohalofluoroolefin isomer includes a step contacting a composition that contains at least a hydrohalofluoroolefin isomer and that has been adjusted to 100 ppm or lower in moisture concentration, with a catalyst in a gas phase, thereby obtaining a product. This method makes it possible to suppress the catalyst performance lowering.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 24, 2019
    Assignee: Central Glass Company, Limited
    Inventors: Takamasa Kitamoto, Satoru Okamoto, Masahiko Tani, Masatomi Kanai, Kohei Sumida
  • Publication number: 20190378918
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 12, 2019
    Inventors: Satoru OKAMOTO, Shinya SASAGAWA
  • Patent number: 10457911
    Abstract: Culture media which contain a water-soluble polymer, such as polyvinyl alcohol and the like, and albumin, and the like, are useful for the proliferation of stem cells, and show good culture results, particularly with iPS cells, and maintain the stability of the medium properties, as well as using a reduced amount of albumin.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 29, 2019
    Assignee: AJINOMOTO CO., INC.
    Inventors: Yoko Kuriyama, Satoru Okamoto, Manabu Kitazawa, Nao Sugimoto, Takuya Matsumoto
  • Patent number: 10460984
    Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Yuta Iida, Satoru Okamoto
  • Patent number: 10446671
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: October 15, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shinya Sasagawa
  • Patent number: 10443899
    Abstract: An object of the present invention is to provide a refrigerant circulation device and method that can suppress acid generation caused by decomposition of a refrigerant containing an HFO or HCFO. The refrigerant circulation device has a compressor, a condenser, expansion valves and an evaporator connected by a main pipe to form a refrigerant circulation circuit through which a refrigerant is circulated, the refrigerant circulation circuit being filled with a refrigerant containing a hydrofluoroolefin or a hydrochlorofluoroolefin having a carbon-carbon double bond within the molecular structure, wherein the refrigerant circulation device includes a drive that drives the compressor via a speed increaser, and a drive cooling unit that cools the drive with the refrigerant condensed in the condenser, and a desiccant that can trap moisture is disposed in the evaporator or the drive cooling unit.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 15, 2019
    Assignees: MITSUBISHI HEAVY INDUSTRIES THERMAL SYSTEMS, LTD., CENTRAL GLASS CO., LTD.
    Inventors: Noriyuki Matsukura, Kenji Ueda, Naoki Kobayashi, Ryosuke Suemitsu, Norihisa Horaguchi, Satoru Okamoto, Yoshio Nishiguchi
  • Patent number: 10424676
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Satoru Okamoto, Shunpei Yamazaki
  • Publication number: 20190251049
    Abstract: Processing by an information processing system is speeded up. A first semiconductor integrated circuit designates a first address of a memory connected to a second semiconductor integrated circuit that is a data transmission destination, based on first memory map information in which addresses of memories respectively used by the semiconductor integrated circuits are defined, converts the first address to a second address of the memory defined in second memory map information referred to by the data transmission destination, and outputs the second address and transmission data by using a PCIe interface. A switch transfers the second address and the transmission data to the data transmission destination by using PCIe interfaces. The data transmission destination receives the second address and the transmission data by using a PCIe interface and writes the transmission data into the reception buffer region of the memory corresponding to the second address.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Seiji GOTO, Eiichi NIMODA, Satoru OKAMOTO
  • Publication number: 20190237239
    Abstract: A laminated coil component 1 includes an element body 2, a coil 8 disposed in the element body 2, and a first external electrode 4 and a second external electrode 5, and at least a part of the coil 8 is disposed in a first region A1 and a second region A2 when seen in a facing direction of the pair of side surfaces 2e and 2f, and the coil 8 is not disposed in a third region A3 and a fourth region A4 when seen in the facing direction of the pair of side surfaces 2e and 2f.
    Type: Application
    Filed: January 16, 2019
    Publication date: August 1, 2019
    Applicant: TDK CORPORATION
    Inventors: Hajime KATO, Satoru OKAMOTO, Masahiro KATO, Makoto YOSHINO, Kazuya TOBITA, Yuto SHIGA, Youichi KAZUTA, Noriaki HAMACHI
  • Publication number: 20190237584
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Application
    Filed: April 9, 2019
    Publication date: August 1, 2019
    Inventors: Yoshinobu ASAMI, Yutaka OKAZAKI, Satoru OKAMOTO, Shinya SASAGAWA
  • Patent number: 10367096
    Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinya Sasagawa, Satoru Okamoto, Motomu Kurata, Yuta Endo
  • Patent number: 10367005
    Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuta Endo, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 10367015
    Abstract: Provided is a semiconductor device which can reduce leakage of current between wirings. Included steps are forming a first insulator over a first conductor which is formed over substrate; forming a first hard mask thereover; forming a first resist mask comprising a first opening, over the first hard mask; etching the first hard mask to form a second hard mask comprising a second opening; etching the first insulator using the second hard mask to form a second insulator comprising a third opening; forming a second conductor embedded in the second opening and the third opening; performing polishing treatment on the second hard mask and the second conductor to form a third conductor embedded in the third opening; forming a fourth conductor thereover; forming a second resist mask in a pattern over the fourth conductor; and dry-etching the fourth conductor to form a fifth conductor. The second hard mask can be dry-etched.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shunpei Yamazaki
  • Publication number: 20190189643
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Application
    Filed: February 20, 2019
    Publication date: June 20, 2019
    Inventors: Ryota HODO, Motomu KURATA, Shinya SASAGAWA, Satoru OKAMOTO, Shunpei YAMAZAKI
  • Publication number: 20190136202
    Abstract: Cultivating a pluripotent stem cell in a medium comprising at least one member selected from the group consisting of ethanolamine, an ethanolamine analog, and a s pharmaceutically acceptable salt thereof, and which is substantially free of ?-mercaptoethanol or contains ?-mercaptoethanol at a concentration of not more than 9 ?M, and the like, is effective for the proliferation of a pluripotent stem cell while maintaining an undifferentiated state.
    Type: Application
    Filed: January 8, 2019
    Publication date: May 9, 2019
    Applicant: AJINOMOTO CO., INC.,
    Inventors: Sho SENDA, Tomomi YOSHIDA, Satoru OKAMOTO, Yoko KURIYAMA, Manabu KITAZAWA, Ikue HARATA, Nao SUGIMOTO
  • Publication number: 20190115478
    Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Inventors: Shinya SASAGAWA, Motomu KURATA, Satoru OKAMOTO, Shunpei YAMAZAKI
  • Patent number: 10256348
    Abstract: A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Kazuya Hanaoka, Shinya Sasagawa, Satoru Okamoto