Patents by Inventor Satoru Okamoto

Satoru Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220076876
    Abstract: A laminated coil component includes an element body, a coil, and a pair of conductors, the pair of conductors is disposed on the element body. Each of the pair of conductors has an L shape when viewed from the third direction. Each of the pair of conductors includes a first conductor portion and a second conductor portion. The first conductor portion is disposed on one of first side faces. The second conductor portion is disposed on a pair of end faces. The coil includes a first coil portion and a second coil portion. The first coil portion includes a first straight portion and a pair of second straight portions. The pair of second straight portions is connected to both ends of the first straight portion. The second coil portion is curved as a whole.
    Type: Application
    Filed: November 19, 2021
    Publication date: March 10, 2022
    Applicant: TDK CORPORATION
    Inventors: Hajime KATO, Yuto SHIGA, Kazuya TOBITA, Youichi KAZUTA, Yuya ISHIMA, Satoru OKAMOTO, Shunji AOKI
  • Patent number: 11245039
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: February 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
  • Patent number: 11245040
    Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a first conductor and a second conductor that are apart from each other over the first oxide; a second insulator covering the first insulator, the first oxide, the first conductor, and the second conductor; a third insulator over the second insulator; a fourth insulator in contact with a first conductor, a side surface of the second conductor, a side surface of the second insulator, and a side surface of the third insulator; a fifth insulator that is over the first oxide and on an inner side of the fourth insulator; a third conductor on an inner side of the fifth insulator; and a sixth insulator that is in contact with a top surface of the fourth insulator and over the third insulator, the fifth insulator, and the third conductor. The fourth insulator is divided to be apart from each other over the first oxide.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Katsuaki Tochibayashi, Satoru Okamoto
  • Publication number: 20220020883
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second insulator provided between the first insulator and the first oxide, a second oxide in contact with the first insulator and in contact with a side surface of the first oxide, and a third insulator over the first insulator, the second oxide, and the first oxide. The third insulator includes a region in contact with a top surface of the first oxide. The second insulator and the third insulator include a material which is less likely to pass oxygen than the second oxide.
    Type: Application
    Filed: February 18, 2020
    Publication date: January 20, 2022
    Inventors: Yuichi YANAGISAWA, Ryota HODO, Satoru OKAMOTO
  • Patent number: 11217376
    Abstract: A laminated electronic component includes an element body and a pair of conductors. The element body is formed by laminating a plurality of element-body layers in a first direction. The pair of conductors is formed by laminating a plurality of conductor layers in the first direction. The pair of conductors is provided to the element body in such a way as to be separated from each other in a second direction orthogonal to the first direction. At a cross section orthogonal to the first direction, the pair of conductors has an uneven portion and the element body has an uneven portion engaged with the uneven portion of the pair of conductors.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: January 4, 2022
    Assignee: TDK CORPORATION
    Inventors: Shunji Aoki, Yuya Ishima, Hajime Kato, Yuto Shiga, Kazuya Tobita, Youichi Kazuta, Satoru Okamoto
  • Patent number: 11211192
    Abstract: A laminated coil component includes an element body, a coil, and a pair of conductors. The pair of conductors is disposed on the element body. Each of the pair of conductors has an L shape when viewed from the third direction. Each of the pair of conductors includes a first conductor portion and a second conductor portion. The first conductor portion is disposed on one of first side faces. The second conductor portion is disposed on a pair of end faces. The coil includes a first coil portion and a second coil portion. The first coil portion includes a first straight portion and a pair of second straight portions. The pair of second straight portions is connected to both ends of the first straight portion. The second coil portion is curved as a whole.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: December 28, 2021
    Assignee: TDK CORPORATION
    Inventors: Hajime Kato, Yuto Shiga, Kazuya Tobita, Youichi Kazuta, Yuya Ishima, Satoru Okamoto, Shunji Aoki
  • Publication number: 20210366926
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Application
    Filed: May 13, 2021
    Publication date: November 25, 2021
    Inventors: Shunpei YAMAZAKI, Hajime KIMURA, Takanori MATSUZAKI, Kiyoshi KATO, Satoru OKAMOTO
  • Publication number: 20210288077
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 16, 2021
    Inventors: Ryota HODO, Motomu KURATA, Shinya SASAGAWA, Satoru OKAMOTO, Shunpei YAMAZAKI
  • Publication number: 20210265353
    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; a third conductor including a region that is over the oxide and overlaps with a region between the first conductor and the second conductor; a first insulator over the third conductor; a fourth conductor that is electrically connected to the first conductor through a first opening provided in the first insulator; a second insulator that is provided over the first insulator and that is provided over the fourth conductor in the first opening; a fifth conductor overlapping with the fourth conductor with the second insulator positioned therebetween in the first opening; and a sixth conductor electrically connected to the second conductor in a second opening provided in the first insulator and the second insulator.
    Type: Application
    Filed: June 27, 2019
    Publication date: August 26, 2021
    Inventors: Satoru OKAMOTO, Ryo TOKUMARU, Ryota HODO
  • Patent number: 11101293
    Abstract: First to third insulators are successively formed in this order over a first conductor over a semiconductor substrate; a hard mask with a first opening is formed thereover; a resist mask with a second opening is formed thereover; a third opening is formed in the third insulator; a fourth opening is formed in the second insulator; the resist mask is removed; a fifth opening is formed in the first to third insulators; a second conductor is formed to cover an inner wall and a bottom surface of the fifth opening; a third conductor is formed thereover; polishing treatment is performed so that the hard mask is removed, and that levels of top surfaces of the second and third conductors and the third insulator are substantially equal to each other; and an oxide semiconductor is formed thereover. The second insulator is less permeable to hydrogen than the first and third insulators, the second conductor is less permeable to hydrogen than the third conductor.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 24, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Motomu Kurata, Shinya Sasagawa, Satoru Okamoto, Shunpei Yamazaki
  • Patent number: 11101386
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 24, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Ryota Hodo, Daigo Ito, Hiroaki Honda, Satoru Okamoto
  • Publication number: 20210257251
    Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: Motomu KURATA, Shinya SASAGAWA, Ryota HODO, Yuta IIDA, Satoru OKAMOTO
  • Patent number: 11024743
    Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 1, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
  • Patent number: 11011542
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: May 18, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hajime Kimura, Takanori Matsuzaki, Kiyoshi Kato, Satoru Okamoto
  • Patent number: 11004727
    Abstract: A minute transistor is provided. A transistor having low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. An electrode including the transistor is provided. A novel electrode is provided. The electrode includes a first conductive layer containing a metal, an insulating layer, and a second conductive layer. The insulating layer is formed over the first conductive layer. A mask layer is formed over the insulating layer. The insulating layer is etched using plasma with the mask layer used as a mask, whereby an opening is formed in the insulating layer so as to reach the first conductive layer. Plasma treatment is performed on at least the opening in an oxygen atmosphere. By the plasma treatment, a metal-containing oxide is formed on the first conductive layer in the opening. The oxide is removed, and then the second conductive layer is formed in the opening.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 11, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Yuta Iida, Satoru Okamoto
  • Patent number: 11003611
    Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 11, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Eiichi Nimoda, Seiji Goto, Satoru Okamoto, Shuichi Yamane, Yasuo Nishiguchi
  • Publication number: 20210119053
    Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first insulator; a first oxide over the first insulator; a first conductor and a second conductor that are apart from each other over the first oxide; a second insulator covering the first insulator, the first oxide, the first conductor, and the second conductor; a third insulator over the second insulator; a fourth insulator in contact with a first conductor, a side surface of the second conductor, a side surface of the second insulator, and a side surface of the third insulator; a fifth insulator that is over the first oxide and on an inner side of the fourth insulator; a third conductor on an inner side of the fifth insulator; and a sixth insulator that is in contact with a top surface of the fourth insulator and over the third insulator, the fifth insulator, and the third conductor. The fourth insulator is divided to be apart from each other over the first oxide.
    Type: Application
    Filed: February 21, 2019
    Publication date: April 22, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Katsuaki TOCHIBAYASHI, Satoru OKAMOTO
  • Publication number: 20210074834
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Application
    Filed: October 19, 2020
    Publication date: March 11, 2021
    Inventors: Satoru OKAMOTO, Shinya SASAGAWA
  • Publication number: 20210011873
    Abstract: A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Eiichi Nimoda, Seiji Goto, Satoru Okamoto, Shuichi Yamane, Yasuo Nishiguchi
  • Patent number: 10879381
    Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: December 29, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoru Okamoto, Shinya Sasagawa