Patents by Inventor Shinn-Sheng Yu

Shinn-Sheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9535316
    Abstract: The present disclosure provides one embodiment of a mask for a lithography exposure process. The mask includes a mask substrate; a first mask material layer patterned to have a first plurality of openings that define a first layer pattern; and a second mask material layer patterned to have a second plurality of openings that define a second layer pattern.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20160377983
    Abstract: A process of an extreme ultraviolet lithography is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask, an EUV radiation source and an illuminator. The process also includes exposing the EUV mask by a radiation, originating from the EUV radiation source and directed by the illuminator, with a less-than-three-degree chief ray angle of incidence at the object side (CRAO). The process further includes removing most of the non-diffracted light and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.
    Type: Application
    Filed: September 9, 2016
    Publication date: December 29, 2016
    Inventors: Shinn-Sheng YU, Anthony YEN, Yen-Cheng LU
  • Patent number: 9529250
    Abstract: The present disclosure also provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over the substrate. A capping layer is disposed over the reflective structure. An absorber layer is disposed over the capping layer. The absorber layer contains an indium tin oxide (ITO) material. In some embodiments, the ITO material has a SnO6 crystalline structure.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Ling Hsieh, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9529249
    Abstract: A system of an extreme ultraviolet lithography (EUVL) is disclosed. The system includes a mask having reflective phase-shift-grating-blocks (PhSGBs). The system also includes an illumination to expose the mask to produce a resultant reflected light from the mask. The resultant reflected light contains mainly diffracted lights. The system also has projection optics to collect and direct resultant reflected light to expose a target.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9529272
    Abstract: A process of an extreme ultraviolet lithography (EUVL) is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask with multiple states. These different states of the EUV mask are assigned to adjacent polygons and adjacent assist polygons. The EUV mask is exposed by a nearly on-axis illumination (ONI) with partial coherence ? less than 0.3 to produce diffracted lights and non-diffracted lights. Most of the non-diffracted lights reflected from main polygons and reflected lights from assist polygons are removed. The diffracted lights and the not removed non-diffracted lights reflected from main polygons are collected and directed to expose a target by a projection optics box.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20160363857
    Abstract: The present disclosure relates to an extreme ultraviolet (EUV) pellicle having a pellicle film connected to a pellicle frame. In some embodiments, the EUV pellicle has a substrate, and an adhesive material disposed onto the substrate. A pellicle frame is connected to the substrate by way of the adhesive material. The pellicle frame is configured to mount the substrate to an extreme ultraviolet (EUV) reticle.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20160329240
    Abstract: A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9488905
    Abstract: A method of forming a mask for semiconductor fabrication is disclosed. The method includes providing a substrate and forming a first reflective layer over the substrate, wherein the first reflective layer comprises pairs of alternating materials. The method further includes forming a buffer layer over the first reflective layer and forming a second reflective layer over the buffer layer. The second reflective layer has a total thickness less than 90 nanometer (nm). The method further includes patterning the second reflective layer to form a first state and a second state of the mask. A first reflection coefficient of the first state and a second reflection coefficient of the second state have a phase difference of about 180 degrees.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20160306272
    Abstract: An extreme ultraviolet lithography (EUVL) system is disclosed. The system includes an extreme ultraviolet (EUV) mask with three states having respective reflection coefficient is r1, r2 and r3, wherein r3 is a pre-specified value that is a function of r1 and r2. The system also includes a nearly on-axis illumination (ONI) with partial coherence a less than 0.3 to expose the EUV mask to produce diffracted light and non-diffracted light. The system further includes a projection optics box (PUB) to remove a portion of the non-diffracted light and to collect and direct the diffracted light and the remaining non-diffracted light to expose a target.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Publication number: 20160306282
    Abstract: The present disclosure provides an extreme ultraviolet (EUV) lithography system. The EUV lithography system includes a collector having a coating surface designed to collect and reflect EUV radiation; a gas supply module; and a gas pipeline integrated with the collector and connected to the gas supply module. The gas pipeline includes inward and outward entrances into the collector. The inward and outward entrances are configured and operable to form a gas curtain on the coating surface of the collector.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Chia-Ching Huang, Tsung-Yu Chen, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen
  • Publication number: 20160291482
    Abstract: Systems and methods for monitoring the focus of an EUV lithography system are disclosed. Another aspect includes a method having operations of measuring a first shift value for a first patterned set of sub-structures of a focus test structure on a wafer and measuring a second shift value for a second patterned set of sub-structures of the test structure on the wafer. The test structure may be formed on the wafer using asymmetric illumination, with the first patterned set of sub-structures having a first pitch and the second patterned set of sub-structures having a second pitch that is different from the first pitch. The method may further include determining a focus shift compensation for an illumination system based on a difference between the first shift value and the second shift value.
    Type: Application
    Filed: September 14, 2015
    Publication date: October 6, 2016
    Inventors: Chih-Tsung Shih, Chieh-Jen Cheng, Jeng-Horng Chen, Chia-Chen Chen, Shinn-Sheng Yu, Anthony Yen, Wei-Chih Lai
  • Patent number: 9448491
    Abstract: A system of an extreme ultraviolet lithography (EUVL) is disclosed. an extreme ultraviolet lithography (EUVL) system includes an extreme ultraviolet (EUV) reflection-type mask having a patterned flare-suppressing-by-phase-shifting (FSbPhS) layer disposed over a patterned absorption layer. The system also includes a radiation to expose the EUV mask and a projection optics box (POB) to collect and direct the radiation that reflects from the EUV mask to expose a target.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9442368
    Abstract: The present disclosure relates to a method of forming an extreme ultraviolet (EUV) pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate. A pellicle frame is attached to an upper surface of the substrate, and the substrate is cleaved along the cleaving plane to form a pellicle film attached to the pellicle frame. The method forms the pellicle without using a support structure, which may block EUV radiation and cause substantial non-uniformities in the intensity of EUV radiation incident on an EUV reticle.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9442365
    Abstract: A mask and method of fabricating same are disclosed. In an example, a mask includes a substrate, a reflective multilayer coating disposed over the substrate and a patterned absorption layer disposed over the reflective multilayer. The patterned absorption layer has a mask image region and a mask border region. The exemplary mask also includes a mask border frame disposed over the mask border region. The mask border frame has a top surface and a bottom surface. The top surface is not parallel to the bottom surface.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9442384
    Abstract: The present disclosure is directed towards lithography processes. In one embodiment, a patterned mask is provided. An information of a position of diffraction light (PDL) on a pupil plane of a projection optics box (POB) is used to define as a light-transmitting region of a pupil filter. The patterned mask is exposed by an on-axis illumination (ONI) with partial coherence ? less than 0.3. The pupil filter is used to transmit diffraction light to a target.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9442387
    Abstract: A process of an extreme ultraviolet lithography is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask, an EUV radiation source and an illuminator. The process also includes exposing the EUV mask by a radiation, originating from the EUV radiation source and directed by the illuminator, with a less-than-three-degree chief ray angle of incidence at the object side (CRAO). The process further includes removing most of the non-diffracted light and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9417534
    Abstract: A lithography process in a lithography system includes loading a mask that includes two mask states defining an integrated circuit (IC) pattern. The IC pattern includes a plurality of main polygons, wherein adjacent main polygons are assigned to different mask states; and a background includes a field in one of the mask states and a plurality of sub-resolution polygons in another of the two mask states. The lithography process further includes configuring an illuminator to generate an illuminating pattern on an illumination pupil plane of the lithography system; configuring a pupil filter on a projection pupil plane of the lithography system with a filtering pattern determined according to the illumination pattern; and performing an exposure process to a target with the illuminator, the mask, and the pupil filter. The exposure process produces diffracted light and non-diffracted light behind the mask and the pupil filter removes most of the non-diffracted light.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9418862
    Abstract: A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Min Huang, Chieh-Han Wu, Chung-Ju Lee, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu
  • Publication number: 20160231647
    Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.
    Type: Application
    Filed: February 5, 2015
    Publication date: August 11, 2016
    Inventors: Pei-Cheng Hsu, Chih-Tsung Shih, Jeng-Horng Chen, Chih-Cheng Lin, Hsin-Chang Lee, Shinn-Sheng Yu, Ta-Cheng Lien, Anthony Yen
  • Patent number: 9412647
    Abstract: A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen