Patents by Inventor Shinn-Sheng Yu

Shinn-Sheng Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Extreme Ultraviolet Lithography Process and Mask
    Publication number: 20160048071
    Abstract: An apparatus comprises a low EUV reflectivity (LEUVR) mask. The LEUVR mask includes a low thermal expansion material (LTEM) layer; a reflective multilayer (ML) over the LTEM layer; and a patterned absorption layer over the reflective ML. The reflective ML has less than 2% EUV reflectivity.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 18, 2016
    Inventors: YEN-CHENG LU, JENG-HORNG CHEN, SHINN-SHENG YU, ANTHONY YEN
  • Extreme ultraviolet lithography process and mask with reduced shadow effect and enhanced intensity
    Patent number: 9261774
    Abstract: The present disclosure provides one embodiment of an extreme ultraviolet (EUV) mask. The EUV mask includes a first state and a second state different from each other; a first main polygon and a second main polygon adjacent to the first main polygon; a plurality of sub-resolution assist polygons; and a field. Each of the first and second main polygons, the sub-resolution assist polygons, and the field has an associated state. The state assigned to the first main polygon is different from the state assigned to the second main polygon. The plurality of assist polygons are assigned a same state, which is different from a state assigned to the field.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method of making an extreme ultraviolet pellicle
    Patent number: 9256123
    Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method of semiconductor integrated circuit fabrication
    Patent number: 9257282
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Tsung-Min Huang, Chung-Ju Lee, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method to Mitigate Defect Printability for ID Pattern
    Publication number: 20160033866
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes loading a mask to a lithography system, wherein the mask includes an one-dimensional integrated circuit (1D IC) pattern; utilizing a pupil phase modulator in the lithography system to modulate phase of light diffracted from the mask; and performing a lithography exposing process to a target in the lithography system with the mask and the pupil phase modulator.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chien, Jeng-Horng Chen, Anthony Yen
  • Metal and via definition scheme
    Patent number: 9252048
    Abstract: A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9244366
    Abstract: An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Assist Feature for a Photolithographic Process
    Publication number: 20160011501
    Abstract: A photomask having a partial-thickness assist feature and a technique for manufacturing the photomask are disclosed. In an exemplary embodiment, the photomask includes a mask substrate, a reflective structure disposed on the mask substrate, and an absorptive layer formed on the reflective structure. A printing feature region and an assist feature region are defined on the mask. The absorptive layer has a first thickness in the printing feature region and a second thickness in the assist feature region that is different from the first thickness. In some such embodiments, the second thickness is configured such that radiation reflected by the assist feature region does not exceed an exposure threshold of a photoresist of a target.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventors: Tao-Min HUANG, Chia-Jen CHEN, Hsin-Chang LEE, Chih-Tsung SHIH, Shinn-Sheng YU, Jeng-Horng CHEN, Anthony YEN
  • Method for integrated circuit patterning
    Patent number: 9229326
    Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shu-Hao Chang, Shinn-Sheng Yu, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
  • Lithography and mask for resolution enhancement
    Patent number: 9223197
    Abstract: A lithography process in a lithography system includes loading a mask having multiple mask states and having a mask pattern consisting of a plurality of polygons and a field. Different mask states are assigned to adjacent polygons and the field. The lithography process further includes configuring an illuminator to generate an illumination pattern on an illumination pupil plane of the lithography system; configuring a pupil filter on a projection pupil plane of the lithography system with a filtering pattern determined according to the illumination pattern; and performing an exposure process to a target with the illuminator, the mask, and the pupil filter. The exposure process produces diffracted light and non-diffracted light behind the mask and the pupil filter removes most of the non-diffracted light.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shinn-Sheng Yu, Yen-Cheng Lu, Anthony Yen
  • Reflective mask and method of making same
    Patent number: 9213232
    Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and where the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Cheng Hsu, Chih-Tsung Shih, Chia-Jen Chen, Tsiao-Chen Wu, Shinn-Sheng Yu, Hsin-Chang Lee, Anthony Yen
  • Extreme Ultraviolet Lithography Process and Mask
    Publication number: 20150346596
    Abstract: An extreme ultraviolet lithography (EUVL) process is disclosed. The process comprises receiving a mask. The mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML)over one surface of the LTEM substrate, a first region having a phase-shifting layer over the reflective ML, and a second region having no phase-shifting layer over the reflective ML. The EUVL process also comprises exposing the mask by a nearly on-axis illumination with partial coherence less than 0.3 to produce diffracted light and non-diffracted light, removing at least a portion of the non-diffracted light, and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 3, 2015
    Inventors: Yen-Cheng Lu, JENG-HORNG CHEN, SHINN-SHENG YU, ANTHONY YEN
  • Method for mask fabrication and repair
    Patent number: 9195135
    Abstract: A method for repairing a phase-defect region in a patterned mask for extreme ultraviolet lithography (EUVL) is disclosed. A patterned mask for EUVL is received. The patterned mask includes an absorptive region having an absorption layer over a defect-repairing-enhancement (DRE) layer, a reflective region having the DRE layer without the absorption layer on top of it, a defect and a phase-defect region resulting from the defect and intruding the reflective region. A location and a shape of the phase-defect region is determined. A portion or portions of the DRE layer in the reflective region is removed according to the location and the shape of the phase-defect region to compensate the effect of the phase-defect region.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme Ultraviolet Light (EUV) Photomasks and Fabrication Methods Thereof
    Publication number: 20150331307
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9182659
    Abstract: A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. An EUVL process includes receiving a mask pair having a same pattern. The mask pair includes an extreme ultraviolet (EUV) mask and a low EUV reflectivity mask. A first exposure process is performed by using the EUV mask to expose a substrate. A second exposure process is performed by using the low EUV reflectivity mask to expose the same substrate. The first exposure process is conducted according to a first exposure dose matrix and the second exposure process is conducted according to a second exposure dose matrix.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method for integrated circuit patterning
    Patent number: 9184054
    Abstract: Provided is a method of patterning a substrate. The method includes forming a resist layer over the substrate, wherein a layer of resist scum forms in between a first portion of the resist layer and the substrate. The method further includes patterning the resist layer to form a plurality of trenches in the first portion, wherein the layer of resist scum provides a floor for the plurality of trenches. The method further includes forming a first material layer in the plurality of trenches, wherein the first material layer has a higher etch resistance than the resist layer and the layer of resist scum. The method further includes etching the first material layer, the resist layer, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chih-Tsung Shih, Chung-Ju Lee, Chieh-Han Wu, Shinn-Sheng Yu, Jeng-Horng Chen
  • Method of Semiconductor Integrated Circuit Fabrication
    Publication number: 20150318173
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Tsung-Min Huang, Chung-Ju Lee, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method for Integrated Circuit Patterning
    Publication number: 20150311075
    Abstract: Provided is a method of patterning a substrate. The method includes forming a resist layer over the substrate, wherein a layer of resist scum forms in between a first portion of the resist layer and the substrate. The method further includes patterning the resist layer to form a plurality of trenches in the first portion, wherein the layer of resist scum provides a floor for the plurality of trenches. The method further includes forming a first material layer in the plurality of trenches, wherein the first material layer has a higher etch resistance than the resist layer and the layer of resist scum. The method further includes etching the first material layer, the resist layer, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chih-Tsung Shih, Chung-Ju Lee, Chieh-Han Wu, Shinn-Sheng Yu, Jeng-Horng Chen
  • METHOD OF MAKING AN EXTREME ULTRAVIOLET PELLICLE
    Publication number: 20150309405
    Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Benjamin Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method to Define Multiple Layer Patterns with a Single Exposure by Charged Particle Beam Lithography
    Publication number: 20150287596
    Abstract: The present disclosure provides a method that includes forming a first patternable material layer on a substrate; forming a second patternable material layer over the first patternable material layer; and performing a charged particle beam lithography exposure process to the first patternable material layer and the second patternable material layer, thereby forming a first latent feature in the first patternable material layer and a second latent feature in the second patternable material layer.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 8, 2015
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen