Abstract: When a tile is evicted from the cache, an attempt is made to compress the tile using any compression algorithm. The difference is that the colors of the tile are compressed as they are, but the colors can also be transformed with a color transform (for example, lossless YCoCg), and after that those colors are compressed with the same compression algorithm. Several different color transforms may be tried, and selection of which one to use can be done in several ways.

Abstract: An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if the draw call's fragment passes for all pixels, it indicates that tile will contain exactly the same pixel color values as the previous frame. Hence, there is no requirement to run the pixel shader for the tile of pixels, and the color values of the tile can instead be reused from the previous frame.

Abstract: A palette compressed representation may be stored in the index bits, when that is possible. The savings are considerable in some embodiments. In uncompressed mode, the data uses 2304 (2048+256) bits, and in compressed mode, the data uses 1280 bits. However, with this technique, the data only uses the index bits, (e.g. 256 bits) with a 5:1 compression improvement over the already compressed representation, and with respect to the uncompressed representation it is a 9:1 compression ratio.

Abstract: In accordance with some embodiments, a zero coverage test may determine whether a primitive such as a triangle relies on lanes between rows or columns or lines of samples. If so, the primitive can be culled in a zero coverage culling test.

Abstract: A color buffer cache may be implemented in a way that reduces memory bandwidth. In one embodiment this may be done by determining whether a corresponding tile being rendered is completely inside a triangle. If so, the cache lines that correspond to this tile may be marked as “less useful”. As a result of being marked as less useful, those cache lines may be replaced before other cache lines in one embodiment. Thus a color buffer cache is used for those tiles that overlap with at least one triangle edge. The use of such a color buffer cache scheme may be more efficient and therefore may reduce memory bandwidth in some embodiments.

Abstract: A simple technique for zmax-culling on a per-tile basis conservatively estimates the maximum depth of the samples in a tile using a layer of masks and a number of zmax-values. No feedback loop is needed from the depth unit, in some embodiments. In addition, the occlusion test may be masked.

Abstract: Depth of field may be rasterized by culling half-space regions on a lens from which a triangle to be rendered is not visible. Then, inside tests are only performed on the remaining unculled half-space regions. Separating planes between the triangle to be rendered and the tile being processed can be used to define the half-space regions.

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.

Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.

Abstract: In accordance with some embodiments, a control surface stores the index bits in a tile using multi-sampling anti-aliasing. By determining whether all the samples in a tile point to plane 0, one can use only two bits in a control surface for the tile to indicate that all the samples on the tile point to plane 0. Otherwise more than two bits may be stored in the control surface to indicate planes pointed to by the samples of the tile.

Abstract: In accordance with some embodiments, the knowledge that a capped frame time is used can be exploited to reduce power consumption. Generally a capped frame time is a pre-allocated amount of time to apply power for rendering in graphics processing. Generally the frame time involves the application of power and some down time in which only idle power is applied pending the next frame time. By making better use of that down time, power consumption reductions can be achieved in some embodiments.

Abstract: We present a technique that utilizes a motion blur (three dimensional) rasterizer to augment the PCS culling technique so that it can be used for continuous collision detection, which to the best of our knowledge has not been done before for motion blur using a graphics processor.

Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.

Abstract: A depth buffer compression scheme uses bilinear patches as a predictor for depth. The scheme targets compression of scenes rendered with stochastic blur rasterization. A tile of fragments may be split into two or more regions and a higher-degree function may be fit to each region. The residuals are then stored as delta corrections.

Abstract: Techniques related to graphics rendering including techniques for improved multi-sampling anti-aliasing compression by use of unreachable bit combinations as described.

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

Abstract: Techniques related to graphics rendering including lossy color merge for multi-sampling anti-aliasing compression.

Abstract: Zmin and Zmax are determined for depth offset compression. Then a check determines whether Zmin is equal to Zmax. If so, only one of Zmin and Zmax is used for depth offset compression and no index mask may be used. The bits that are saved thereby may be used for other purposes, including improving precision.

Abstract: Data destined for memory, i.e., data that was evicted at some level in the cache hierarchy is intercepted and subjected to compression before being sent to memory. Thereby, when the compression is successful, the memory bandwidth requirement is reduced, potentially resulting in higher performance and/or energy efficiency in some embodiments.

Abstract: Multi-view rasterization may be performed by calculating visibility over a camera line. Edge equations may be evaluated iteratively along a scanline. The edge equations may be evaluated using single instruction multiple data instruction sets.