Abstract: Data destined for memory, i.e., data that was evicted at some level in the cache hierarchy is intercepted and subjected to compression before being sent to memory. Thereby, when the compression is successful, the memory bandwidth requirement is reduced, potentially resulting in higher performance and/or energy efficiency in some embodiments.

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a thread dispatcher to assign a priority class to each of a plurality of processing threads prior to dispatching the one or more processing threads, a plurality of execution units to process the threads, a shared resource coupled to each of the plurality of execution units and an arbitration unit to grant access to the shared resource to a first of the plurality of execution units based on the priority class of a thread being executed at the first execution unit.

Abstract: Described herein are several embodiments which provide for enhanced data caching in combination with adaptive and dynamic compression to increase the storage efficiency and reduce the transmission bandwidth of data during input and output from a GPU. The techniques described herein can reduce the need to access off-chip memory, resulting in improved performance and reduced power for GPU operations. One embodiment provides for a graphics processing apparatus comprising a shader engine; one or more cache memories; cache control logic to control at least one of the one or more cache memories; and a codec unit coupled with the one or more cache memories, the codec unit configurable to perform lossless compression of read-only surface data upon storage to or eviction from the one or more cache memories.

Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.

Abstract: Embodiments described herein enable a hierarchical-Z unit of a graphics processor to be primed using Hi-Z data generated by occlusion culling operations performed on a general purpose processor. One embodiment provides for instructions to cause operations including performing occlusion culling for a scene via the general purpose processor and storing generated hierarchical-Z data. The Hierarchical-Z data generated during the occlusion culling operations can be shared with the graphics processor and used to prime a hierarchical-Z unit of the graphics processor. The at least a portion of the scene can then be rendered using the hierarchical-Z data after priming the hierarchical-Z unit, improving the effectiveness of hierarchical-Z operations of the graphics processor for the scene.

Abstract: An apparatus and method are described for performing an efficient depth prepass. For example, one embodiment of a method comprising: a method comprising: performing a first pass through a specified portion of a graphics pipeline with only depth rendering active; initializing a coarse depth buffer within the specified portion of the graphics pipeline during the first pass, the coarse depth buffer storing depth data at a level of granularity less than that stored in a per-pixel depth buffer, which is not initialized during the first pass; and performing a second pass through the graphics pipeline following the first pass, the second pass utilizing the full graphics pipeline and using values in the coarse depth buffer initialized by the first pass.

Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimized shadow mapping are described. In an embodiment, a processor performs one or more operations on depth data of an image tile in response to a determination that the depth data includes a minimum depth value inside the image tile and a maximum depth value inside the image tile. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for efficient ray tracing. For example, one embodiment of an apparatus comprises: a general purpose processor to generate a plurality of ray streams; a first hardware queue to receive the ray streams generated by the general purpose processor; a graphics processing unit (GPU) comprising a plurality of execution units (EUs) to process the ray streams from the first hardware queue; a second hardware queue to store graphics processing jobs submitted by the GPU; the general purpose processor to process the jobs submitted by the GPU and share results with the GPU.

Abstract: A graphics processing apparatus and method are described.

Abstract: Methods and apparatus relating to techniques for provision of hierarchical Z-Culling (HiZ) optimization for texture-dependent discard operations are described. In an embodiment, a processor performs one or more operations (such as HiZ or Hierarchical Stencil test) on depth data of an image tile in response to a determination that texture space bounds of the image tile is fully opaque. The processor performs the one or more operations regardless of whether a discard operation is enabled. Other embodiments are also disclosed and claimed.

Abstract: A virtual reality apparatus and method are described for tile-based rendering. For example, one embodiment of an apparatus comprises: a set of on-chip geometry buffers including a first buffer to store geometry data, and a set of pointer buffers to store pointers to the geometry data; a tile-based immediate mode rendering (TBIMR) module to perform tile-based immediate mode rendering using geometry data and pointers stored within the set of on-chip geometry buffers; spill circuitry to determine when the on-chip geometry buffers are over-subscribed and responsively spill additional geometry data and/or pointers to an off-chip memory; and a prefetcher to start prefetching the geometry data from the off-chip memory as space becomes available within the on-chip geometry buffers, the TBIMR module to perform tile-based immediate mode rendering using the geometry data prefetched from the off-chip memory.

Abstract: A virtual reality apparatus and method are described.

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

Abstract: An apparatus and method are described for dynamic polygon or primitive sorting for improved culling. For example, one embodiment of an apparatus comprises: a rasterization unit to receive a plurality of polygons to be rasterized in an original ordering; and depth test evaluation logic to determine whether a current polygon is fully visible, partially visible or occluded; and reordering logic to incrementally alter the original ordering by swapping each occluded polygon with another polygon positioned relatively lower in the original ordering and by swapping each fully visible polygon with another polygon positioned relatively higher in the original ordering.

Abstract: Methods and apparatus relating to techniques for varying image quality rendering in a sort middle architecture. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to divide a display into a plurality of sections, assign a plurality of image quality parameters to the plurality of sections, and render images in each of the plurality of sections at a quality level determined at least in part by the image quality parameter assigned to each of the plurality of sections, wherein the plurality of image quality parameters assigned to the plurality of sections vary. Other embodiments are also disclosed and claimed.

Abstract: Briefly, in accordance with one or more embodiments, an architecture to load balance tessellation distribution apparatus comprises a memory to store one or more patches representing an object in an image, and a processor, coupled to the memory, to perform one or more tessellation operations on the one or more patches. The one or more tessellation operations including splitting one or more of the patches into one or more subpatches, and load balancing the one or more patches and the one or more subpatches among two or more geometry and setup fixed-function pipelines (GSPs).

Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.

Abstract: An apparatus and method for load balancing in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: an intersection unit engine to test a plurality of rays against a plurality of primitives to identify a closest primitive that each ray intersects; an intersection unit queue to store work to be performed by the intersection unit engine; and an intersection unit offload engine to monitor the intersection unit queue to determine a pressure level on the intersection unit engine, the intersection unit offload engine to responsively offload some of the work in the intersection unit queue to intersection program code executed on one or more execution units of the graphics processor.

Abstract: In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.