Patents by Inventor Tomas G. Akenine-Moller

Tomas G. Akenine-Moller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9501860
    Abstract: An importance map indicates, for each of a plurality of pixels, whether the pixel is considered important enough to be rendered. A hierarchical tree for pixels is created to generate a hierarchical importance map. The hierarchical importance map may be used to stop traversal of a primitive that does not overlap a pixel indicated to be important.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Rasmus Barringer, Tomas G. Akenine-Moller
  • Publication number: 20160328820
    Abstract: Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.
    Type: Application
    Filed: July 18, 2016
    Publication date: November 10, 2016
    Inventors: Juan Fernandez, Javier Carretero Casado, Pedro Marcuello, Tomas G. Akenine-Moller
  • Patent number: 9491490
    Abstract: A mechanism is described for facilitating environment-based lossy compression of data for efficient rendering of contents at computing devices. A method of embodiments, as described herein, includes collecting, in real time, sensory input data relating to characteristics of at least one of a user and a surrounding environment. The method may further include evaluating the sensory input data to mark one or more data portions of data relating to contents, where the one or more data portions are determined to be suitable for compression based on the sensory input data. The method may further include dynamically performing, in real time, the compression of the one or more data portions, where the compression triggers loss of one or more content portions of the contents corresponding to the one or more data portions of the data.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: November 8, 2016
    Assignee: Intel Corporation
    Inventors: Robert M. Toth, Jim K. Nilsson, Tomas G. Akenine-Möller, Franz P. Clarberg
  • Patent number: 9483869
    Abstract: Real-time light field reconstruction for defocus blur may be used to handle the case of simultaneous defocus and motion blur. By carefully introducing a few approximations, a very efficient sheared reconstruction filter is derived, which produces high quality images even for a very low number of input samples in some embodiments. The algorithm may be temporally robust, and is about two orders of magnitude faster than previous work, making it suitable for both real-time rendering and as a post-processing pass for high quality rendering in some embodiments.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: November 1, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Karthik Vaidyanathan, Jon N. Hasselgren, Franz P. Clarberg, Tomas G. Akenine-Moller, Marco Salvi
  • Publication number: 20160307297
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: April 20, 2015
    Publication date: October 20, 2016
    Inventors: TOMAS G. AKENINE-MOLLER, ROBERT T. TOTH, BJORN JOHNSSON, JON N. HASSELGREN
  • Patent number: 9466124
    Abstract: A palette compressed representation may be stored in the index bits, when that is possible. The savings are considerable in some embodiments. In uncompressed mode, the data uses 2304 (2048+256) bits, and in compressed mode, the data uses 1280 bits. However, with this technique, the data only uses the index bits, (e.g. 256 bits) with a 5:1 compression improvement over the already compressed representation, and with respect to the uncompressed representation it is a 9:1 compression ratio.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: October 11, 2016
    Assignee: Intel Corporation
    Inventor: Tomas G. Akenine-Moller
  • Patent number: 9466090
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described. In one example, compression in graphics rendering may include determining a plurality of color values associated with individual pixels of a tile of pixels, generating a subset of the plurality of color values such that the subset of the plurality of color values include one or more distinct color values from the plurality of color values, associating an index value with each color value of the subset of the plurality of color values, determining, for each of the individual pixels, an associated pixel index value to generate a plurality of pixel index values associated with the individual pixels of the tile of pixels, storing, in memory, graphics data including the subset of the plurality of color values, the associated index values, and the plurality of pixel index values.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: October 11, 2016
    Assignee: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim. K. Nilsson
  • Patent number: 9460365
    Abstract: Color values may be compressed using a palette based encoder. Clusters of color values may be identified and encoded color values within the cluster with respect to a color value having a predefined characteristic. Clusters that have pixels or samples with constant color value may also be encoded.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson
  • Publication number: 20160283391
    Abstract: In accordance with some embodiments, compaction, as contrasted with compression, is used to reduce the footprint of a near memory. In compaction, the density of data storage within a storage device is increased. In compression, the number of bits used to represent information is reduced. Thus you can have compression while still having sparse or non-contiguously arranged storage. As a result, compression may not always reduce the memory footprint. By compacting compressed data, the footprint of the information stored within the memory may be reduced. Compaction may reduce the need for far memory accesses in some cases.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 29, 2016
    Inventors: Jim K. Nilsson, Tomas G. Akenine-Moller, Franz P. Clarberg
  • Publication number: 20160283825
    Abstract: Color values may be compressed using a palette based encoder. Clusters of color values may be identified and encoded color values within the cluster with respect to a color value having a predefined characteristic. Clusters that have pixels or samples with constant color value may also be encoded.
    Type: Application
    Filed: March 24, 2015
    Publication date: September 29, 2016
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson
  • Patent number: 9443347
    Abstract: We present a technique that utilizes a motion blur (three dimensional) rasterizer to augment the PCS culling technique so that it can be used for continuous collision detection, which to the best of our knowledge has not been done before for motion blur using a graphics processor.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: September 13, 2016
    Assignee: Intel Corporation
    Inventors: Jim K. Nilsson, Tomas G. Akenine-Moller
  • Patent number: 9430818
    Abstract: A rasterizer, based on time-dependent edge equations, computes analytical visibility in order to render accurate motion blur. An oracle-based compression algorithm for the time intervals lowers the frame buffer requirements. High quality motion blurred scenes can be rendered using a rasterizer with rather low memory requirements. The resulting images may contain motion blur for both opaque and transparent objects.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Carl Johan Gribel, Michael Doggett, Tomas G. Akenine-Moller
  • Patent number: 9406100
    Abstract: Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Jon N. Hasselgren, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9401046
    Abstract: Micropolygon splatting may involve tessellating by subdividing a mesh until triangle edges are shorter than 0.75 pixels. In some cases, rasterizing the primitive may be avoided.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 26, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Tomas G. Akenine-Möller, Jon N. Hasselgren, Robert M. Toth
  • Patent number: 9396582
    Abstract: A per-tile test in the 5D rasterizer outputs intervals for both lens parameters, (u,v), and for time, t, as well as for depth z. These intervals are conservative bounds for the current tile for 1) the visible lens region, 2) the time the triangle overlaps the tile, and 3) the depth range for the triangle inside the tile.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson, Carl J. Munkberg
  • Patent number: 9390550
    Abstract: Efficient overlap tests between a screen space tile and a moving triangle with per-vertex motion following Bézier curves report conservative time bounds in which the moving triangle overlaps with a tile. The tests can be used in designing efficient hierarchical traversal algorithms for higher order motion blur rendering.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Carl J. Munkberg, Jon N. Hasselgren, Tomas G. Akenine-Moller
  • Patent number: 9390539
    Abstract: A graphics processing pipeline may include at least two or more pipes, such that a lower frequency operation may be executed on one pipe while a higher frequency operation in the same instruction stream is executed at the same time on another pipe. In some cases, the lower frequency operation result may be held for later use in connection with the higher frequency operation on a different pipe. Especially where unused slots can be used for the lower frequency operation, efficiency may be improved.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Rahul P. Sathe
  • Patent number: 9390541
    Abstract: In accordance with some embodiments, a tile shader executes on a group of pixels prior to a pixel shader. The tile of pixels may be rectangular in some embodiments. The tile may be executed hierarchically, refining each tile into smaller subtiles until the pixel or sample level is reached. The tile shader program can be written to discard groups of pixels, thereby quickly removing areas of the bounding triangles that lie outside the shape being rasterized or quickly discarding groups of pixel shader executions that will not contribute to the final image.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: July 12, 2016
    Assignee: Intel Corporation
    Inventors: Jon N. Hasselgren, Tomas G. Akenine-Moller, Carl J. Munkberg, Jim K. Nilsson, Robert M. Toth, Franz P. Clarberg
  • Publication number: 20160189338
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Inventors: Tomas G. AKENINE-MOLLER, Jim K. NILSSON, Prasoonkumar SURTI, Jon N. HASSELGREN, Carl J. MUNKBERG
  • Publication number: 20160171756
    Abstract: In the cull pipe, positions of the vertices of a triangle have already been computed and these coordinates may be exploited by taking and sorting triangle groups based on these coordinates. As one example, all the triangles in a tile may constitute a group. The triangle groups are sorted into bins. Within each bin the triangles are sorted based on their depths.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Tomas G. Akenine-Moller, Magnus Andersson, Bjorn Johnsson