Patents by Inventor Tomas G. Akenine-Moller

Tomas G. Akenine-Moller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9886740
    Abstract: In one embodiment the table pointed to by visibility samples in Degradation Coverage-Based Anti-Aliasing is split up so that more values can fit (but each value uses fewer bits). This way, more values can be represented in a pixel, and this leads to better image quality in some embodiments. This also opens up the possibility of using as few as two values per pixel, whereas the CSAA uses four or more. Hence, this also saves bandwidth and therefore, also reduces power consumption in some embodiments.
    Type: Grant
    Filed: May 14, 2014
    Date of Patent: February 6, 2018
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jim K. Nilsson
  • Publication number: 20180005350
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of indexed subsets are described.
    Type: Application
    Filed: August 31, 2016
    Publication date: January 4, 2018
    Inventors: Prasoonkumar Surti, Tomas G. Akenine-Moller, Jon N. Hasselgren, Carl J. Munkberg, Jim. K. Nilsson
  • Publication number: 20180005348
    Abstract: An apparatus and method for frame buffer compression. For example, one embodiment of a method comprises: identifying a wavelet function to compress an original frame buffer image; performing a wavelet transform on the original frame buffer image using the wavelet function; using a specified subset of wavelet coefficients of the wavelet function to construct an approximated image function; determining residuals comprising differences between the original frame buffer image and the approximated image function; and storing the residuals for subsequent use in recreating the original frame buffer image from the approximated image function.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventor: TOMAS G. AKENINE-MOLLER
  • Publication number: 20170372450
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Application
    Filed: July 10, 2017
    Publication date: December 28, 2017
    Inventors: TOMAS G. AKENINE-MOLLER, ROBERT M. TOTH, BJORN JOHNSSON, JON N. HASSELGREN
  • Publication number: 20170371662
    Abstract: A mechanism is described for facilitating extension of register files in computing environments. A method of embodiments, as described herein, includes facilitating, inside an extended register file, performance of one or more tasks relating to an instruction, where the one or more tasks are performed by an extension mechanism being hosted inside the extended register file of a computing device.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventor: Tomas G. AKENINE-MOLLER
  • Publication number: 20170345206
    Abstract: An apparatus and method are described for occlusion queries for accelerated rendering. For example, one embodiment of a method comprises: performing an occlusion query for a plurality of tiles of an image, the occlusion query to determine whether one or more of the tiles are occluded; generating a bit mask in response to the occlusion query, the bit mask comprising data indicating which of the tiles are occluded; and reading the bit mask when rendering the image to remove work associated with those tiles which are occluded.
    Type: Application
    Filed: May 27, 2016
    Publication date: November 30, 2017
    Inventors: TOMAS G. AKENINE-MOLLER, MAGNUS ANDERSSON, JON N. HASSELGREN, LARRY SEILER
  • Patent number: 9824412
    Abstract: In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: November 21, 2017
    Assignee: Intel Corporation
    Inventors: Saurabh Sharma, Subramaniam Maiyuran, Thomas A. Piazza, Kalyan K. Bhiravabhatla, Peter L. Doyle, Paul A. Johnson, Bimal Poddar, Jon N. Hasselgren, Carl J. Munkberg, Tomas G. Akenine-Moller, Harri Syrja, Kevin Rogovin, Robert L. Farrell
  • Patent number: 9799091
    Abstract: An apparatus and method are described for the frame-to-frame coherency algorithm for sort-last architecture. In one embodiment of the invention, if a tile of pixels is covered completely by one triangle from a static draw call in one frame, then that tile is marked with that draw call's identifier. For the next frame, if the same static draw call is drawn, the same tile will be visited, and if the draw call's fragment passes for all pixels, it indicates that tile will contain exactly the same pixel color values as the previous frame. Hence, there is no requirement to run the pixel shader for the tile of pixels, and the color values of the tile can instead be reused from the previous frame.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: October 24, 2017
    Assignee: INTEL CORPORATION
    Inventor: Tomas G. Akenine-Moller
  • Publication number: 20170264106
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Publication number: 20170256079
    Abstract: According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering.
    Type: Application
    Filed: April 20, 2017
    Publication date: September 7, 2017
    Inventors: Tomas G. Akenine-Moller, Carl J. Munkberg, Franz P. Clarberg
  • Patent number: 9754345
    Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G Akenine-Moller, Jim K Nilsson, Prasoonkumar Surti, Jon N Hasselgren, Carl J Munkberg
  • Publication number: 20170236247
    Abstract: A mechanism is described for facilitating ray compression for efficient graphics data processing at computing devices. A method of embodiments, as described herein, includes forwarding a set of rays to a ray compression unit hosted by a graphics processor at a computing device, and facilitating the ray compression unit to compress the set of rays, wherein the set of rays are compressed into a compressed representation.
    Type: Application
    Filed: February 17, 2016
    Publication date: August 17, 2017
    Applicant: INTEL CORPORATION
    Inventor: TOMAS G. AKENINE-MOLLER
  • Patent number: 9734597
    Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Jon N. Hasselgren, Jim K. Nilsson
  • Publication number: 20170206700
    Abstract: An apparatus and method are described for texture space shading. For example, one embodiment of a method comprises: performing texture mapping to map one or more textures to surfaces of one or more objects in texture space within a ray tracing architecture; and performing sampling and reconstruction directly on the surfaces of the objects in the texture space.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 20, 2017
    Inventors: CARL J. MUNKBERG, JON N. HASSELGREN, FRANZ P. CLARBERG, MAGNUS ANDERSSON, ROBERT M. TOTH, JIM K. NILSSON, TOMAS G. AKENINE-MOLLER
  • Patent number: 9704217
    Abstract: An apparatus and method are described for a non-uniform rasterizer. For example, one embodiment of an apparatus comprises: a graphics processor to process graphics data and render images using the graphics data; and a non-uniform rasterizer within the graphics processor to determine different resolutions to be used for different regions of an image, the non-uniform rasterizer to receive a plurality of polygons to be rasterized and to responsively rasterize the polygons in accordance with the different resolutions.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Tomas G. Akenine-Moller, Robert M. Toth, Bjorn Johnsson, Jon N. Hasselgren
  • Publication number: 20170186128
    Abstract: An apparatus and method are described for primitive pair merging. For example, one embodiment of a graphics processing apparatus comprises: primitive merging logic to generate merged primitive data for two or more primitives sharing at least one edge, wherein the merged primitive data includes a single set of vertices defining the at least one shared edge; and an intersection unit to test a plurality of rays against the merged primitive data to identify a closest primitive that each ray intersects, the intersection unit to perform shared computations for the shared edge.
    Type: Application
    Filed: December 26, 2015
    Publication date: June 29, 2017
    Inventors: Tomas G. Akenine-Moller, Rasmus Barringer, Magnus Andersson
  • Publication number: 20170178385
    Abstract: An apparatus and method for load balancing in a ray tracing architecture. For example, one embodiment of a graphics processing apparatus comprises: an intersection unit engine to test a plurality of rays against a plurality of primitives to identify a closest primitive that each ray intersects; an intersection unit queue to store work to be performed by the intersection unit engine; and an intersection unit offload engine to monitor the intersection unit queue to determine a pressure level on the intersection unit engine, the intersection unit offload engine to responsively offload some of the work in the intersection unit queue to intersection program code executed on one or more execution units of the graphics processor.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Inventor: Tomas G. Akenine-Moller
  • Publication number: 20170178276
    Abstract: A mechanism is described for facilitating efficient clustering and compression of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device. The method may further include splitting the tile into a plurality of clusters, where each cluster includes a set of pixels of one or more colors. The method may further include determining a center color for each cluster of the plurality of colors, where determining further includes deciding whether the center color is classified as acceptable for compression. The method may further include compressing contents of one or more of clusters if one or more center colors of the one or more clusters are classified as acceptable.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: TOMAS G. AKENINE-MOLLER, JIM K. NILSSON
  • Publication number: 20170178362
    Abstract: A mechanism is described for facilitating interpolated minimum-maximum compression/decompression for efficient processing of graphics data at computing devices. A method of embodiments, as described herein, includes detecting a tile having pixels representing graphics contents capable of being processed by a graphics processor of a computing device; computing a minimum color value and a maximum color value of the tile. The method may further include splitting the tile into a plurality of interpolation tiles, where each interpolation tile includes a set of pixels of one or more colors. The method may further include computing a plurality of local minimum color values for the plurality of interpolation tiles, computing, based on the plurality of local minimum values, a plurality of residuals for the plurality of interpolation tiles to reduce spreads from the plurality of interpolation tiles, and compressing the reduced plurality of interpolation tiles based on the plurality of residuals.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: TOMAS G. AKENINE-MOLLER, JON N. HASSELGREN, JIM K. NILSSON
  • Publication number: 20170178387
    Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Sven Woop, Carsten Benthin, Rasmus Barringer, Tomas G. Akenine-Moller