Patents by Inventor Toshio Miyamoto
Toshio Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134369Abstract: According to one embodiment, an anomaly sign detection system comprising one or more computers configured to: calculate a correction value for correcting at least one actual process value from the at least one actual process value and at least one reference process value; determine whether each of plurality of actual process values is correlated with the at least one reference process value or not, based on correction-necessity coefficient of determination; use the correction value for correcting at least one actual process value determined to be correlated with the at least one reference process value among the plurality of actual process values; generate learning input data including at least one corrected process value as the at least one actual process value corrected by the correction value; and perform machine learning by inputting the learning input data to anomaly sign detection model.Type: ApplicationFiled: August 23, 2023Publication date: April 25, 2024Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ENERGY SYSTEMS & SOLUTIONS CORPORATIONInventors: Naoyuki TAKADO, Chikashi MIYAMOTO, Toshio AOKI, Shinya TOMINAGA, Ryota MIYAKE
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Patent number: 11913813Abstract: A power generation element includes a magnetic member that produces a large Barkhausen effect and magnetism collection members including an insertion part having the magnetic member inserted therethrough. The magnetism collection member includes a first component on an opposite side of a boundary plane to a magnetic field generation unit and a second component on the same side of the boundary plane as the magnetic field generation unit, the boundary plane passing through a center of an imaginary circle inscribed in the insertion part and having a diameter equal to a length of the insertion part in a third direction perpendicular to first and second directions, the first direction is a direction of the insertion of the magnetic member, and the second direction is a direction in which the magnetic field generation unit is disposed. A volume of the second component is larger than a volume of the first component.Type: GrantFiled: December 27, 2021Date of Patent: February 27, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshitomo Nakamura, Yoshinori Miyamoto, Shinichiro Yoshida, Hisanori Torii, Takeshi Musha, Masanori Nimura, Shizuka Ueda, Takuya Noguchi, Toshio Mekata, Yuji Kubo, Hitoshi Hasegawa
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Patent number: 9618889Abstract: A fixing device configured to fix an image on a recording material, includes: a rotary member including an electroconductive layer; a coil which has a spiral shaped portion and is disposed in the inside of the rotary member; and a core disposed in the spiral shaped portion; with magnetic resistance of the core being, with an area from one end to the other end of the maximum passage region of the image on the recording material regarding the generatrix direction, equal to or smaller than 30% of combined magnetic resistance made up of magnetic resistance of the electroconductive layer and magnetic resistance of a region between the electroconductive layer and the core.Type: GrantFiled: April 18, 2016Date of Patent: April 11, 2017Assignee: CANON KABUSHIKI KAISHAInventors: Yuki Nishizawa, Hiroshi Mano, Minoru Hayasaki, Aoji Isono, Akira Kuroda, Toshio Miyamoto, Michio Uchida, Seiji Uchiyama
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Publication number: 20160231679Abstract: A fixing device configured to fix an image on a recording material, includes: a rotary member including an electroconductive layer; a coil which has a spiral shaped portion and is disposed in the inside of the rotary member; and a core disposed in the spiral shaped portion; with magnetic resistance of the core being, with an area from one end to the other end of the maximum passage region of the image on the recording material regarding the generatrix direction, equal to or smaller than 30% of combined magnetic resistance made up of magnetic resistance of the electroconductive layer and magnetic resistance of a region between the electroconductive layer and the core.Type: ApplicationFiled: April 18, 2016Publication date: August 11, 2016Inventors: Yuki Nishizawa, Hiroshi Mano, Minoru Hayasaki, Aoji Isono, Akira Kuroda, Toshio Miyamoto, Michio Uchida, Seiji Uchiyama
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Patent number: 9377733Abstract: A fixing device configured to fix an image on a recording material, includes: a rotary member including an electroconductive layer; a coil which has a spiral shaped portion and is disposed in the inside of the rotary member; and a core disposed in the spiral shaped portion; with magnetic resistance of the core being, with an area from one end to the other end of the maximum passage region of the image on the recording material regarding the generatrix direction, equal to or smaller than 30% of combined magnetic resistance made up of magnetic resistance of the electroconductive layer and magnetic resistance of a region between the electroconductive layer and the core.Type: GrantFiled: June 13, 2013Date of Patent: June 28, 2016Assignee: Canon Kabushiki KaishaInventors: Yuki Nishizawa, Hiroshi Mano, Minoru Hayasaki, Aoji Isono, Akira Kuroda, Toshio Miyamoto, Michio Uchida, Seiji Uchiyama
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Patent number: 9342009Abstract: A fixing device configured to fix an image on a recording material, includes: a rotary member including an electroconductive layer; a coil which has a spiral shaped portion and is disposed in the inside of the rotary member; and a core disposed in the spiral shaped portion; with magnetic resistance of the core being, with an area from one end to the other end of the maximum passage region of the image on the recording material regarding the generatrix direction, equal to or smaller than 30% of combined magnetic resistance made up of magnetic resistance of the electroconductive layer and magnetic resistance of a region between the electroconductive layer and the core.Type: GrantFiled: June 13, 2013Date of Patent: May 17, 2016Assignee: Canon Kabushiki KaishaInventors: Yuki Nishizawa, Hiroshi Mano, Minoru Hayasaki, Aoji Isono, Akira Kuroda, Toshio Miyamoto, Michio Uchida, Seiji Uchiyama
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Publication number: 20150132035Abstract: A fixing device configured to fix an image on a recording material, includes: a rotary member including an electroconductive layer; a coil which has a spiral shaped portion and is disposed in the inside of the rotary member; and a core disposed in the spiral shaped portion; with magnetic resistance of the core being, with an area from one end to the other end of the maximum passage region of the image on the recording material regarding the generatrix direction, equal to or smaller than 30% of combined magnetic resistance made up of magnetic resistance of the electroconductive layer and magnetic resistance of a region between the electroconductive layer and the core.Type: ApplicationFiled: June 13, 2013Publication date: May 14, 2015Inventors: Yuki Nishizawa, Hiroshi Mano, Minoru Hayasaki, Aoji Isono, Akira Kuroda, Toshio Miyamoto, Michio Uchida, Seiji Uchiyama
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Patent number: 8629481Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: GrantFiled: February 22, 2011Date of Patent: January 14, 2014Assignee: Renesas Electronics CorporationInventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Publication number: 20110140185Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: ApplicationFiled: February 22, 2011Publication date: June 16, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Patent number: 7910922Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: GrantFiled: August 11, 2010Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Patent number: 7910960Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: GrantFiled: April 30, 2009Date of Patent: March 22, 2011Assignee: Renesas Electronics CorporationInventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Publication number: 20100301334Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: ApplicationFiled: August 11, 2010Publication date: December 2, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Publication number: 20090230448Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: ApplicationFiled: April 30, 2009Publication date: September 17, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Patent number: 7550763Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: GrantFiled: June 13, 2007Date of Patent: June 23, 2009Assignee: Renesas Technology Corp.Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Publication number: 20070256582Abstract: A processing device includes a transport cylinder, processing cylinder, and press roller. The transport cylinder includes a hold device which holds a sheet, and a plate support device which supports a plate to be mounted on an outer surface of the counter cylinder. The processing cylinder opposes the counter cylinder and processes the sheet. The press roller is supported to be movable between an operative position and retreat position. At the operative position, the press roller is close to the outer surface of the transport cylinder. At the retreat position, the press roller separates away from the outer surface of the transport cylinder, the plate being pressed against the outer surface of the transport cylinder by the press roller.Type: ApplicationFiled: April 19, 2007Publication date: November 8, 2007Inventors: Motoyasu Hirata, Toshio Miyamoto
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Publication number: 20070241330Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: ApplicationFiled: June 13, 2007Publication date: October 18, 2007Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Patent number: 7247879Abstract: In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.Type: GrantFiled: June 23, 2004Date of Patent: July 24, 2007Assignee: Renesas Technology Corp.Inventors: Asao Nishimura, Syouji Syukuri, Gorou Kitsukawa, Toshio Miyamoto
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Patent number: 7155136Abstract: The image heating apparatus for heating a toner image formed on a recording material, comprising, a rotatable member; heating device for heating an outer peripheral surface of the rotatable member, the heating device including a heater for forming a heating nip portion in cooperation with the rotatable member; back-up device for forming a conveying nip portion in cooperation with the rotatable member, the conveying nip portion conveying the recording material; and control device for controlling a temperature of the heater and a rotation of the rotatable member, wherein the apparatus has a cleaning mode to remove toner from the heating device, and the control device rotates or reversely rotates the rotatable member in a condition that the heater dissipates heat in the cleaning mode. By the virtue of the present invention, it prevents stain caused by the off-set of toner the recording material in an image heating apparatus.Type: GrantFiled: February 1, 2005Date of Patent: December 26, 2006Assignee: Canon Kabushiki KaishaInventors: Koji Nihonyanagi, Toshio Miyamoto, Masahiko Suzumi
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Patent number: 7138722Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: February 15, 2005Date of Patent: November 21, 2006Assignee: Renesas Technology Corp.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 7125059Abstract: A hand device for working robot which can be downsized is provided. The device consists of a robot hand 10, a link means 40 and a workpiece drop prevention means. The robot hand 10 includes a hand base 20, a pair of fingers 21, 21 protruding from the hand base 20 and a movable core 25 provided with a cylinder 24. The link means 40 includes a lever and a connecting pad 43 for connecting the lever and the movable core 25. A workpiece drop prevention means 60 includes a protrusion stick 50 which is supported by a supporting rail 51, a coil spring and an air cylinder for recess 53.Type: GrantFiled: March 12, 2004Date of Patent: October 24, 2006Assignee: Yutaka Electronics Industry Co., Ltd.Inventor: Toshio Miyamoto