Patents by Inventor Toshio Miyamoto
Toshio Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6701102Abstract: In a method and apparatus for controlling the temperature of a fixing device of the film heating type and the pressure rotary member driving type and an image forming apparatus provided with this fixing device, at the start of printing, the output of a thermistor near a heater is detected, and when the temperature difference &Dgr;T=T2−T1 between the detected temperature T1 and the fixing temperature T2 is smaller than a desired temperature T0, the raising timing of the heater is delayed. Thereby, a pressure roller is not-excessively warmed at hot start and slip can be prevented. Also, in the image forming apparatus having the film heating type fixing device, in the next printing after the lapse of a predetermined time after the termination of a printing operation, the target temperature and heater electrical energization starting timing of the fixing device are changed in conformity with the temperature of the fixing device.Type: GrantFiled: November 30, 2001Date of Patent: March 2, 2004Assignee: Canon Kabushiki KaishaInventors: Hiroto Hasegawa, Toshio Miyamoto, Satoru Izawa, Masahiko Suzumi, Kenji Kanari
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Patent number: 6664616Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is smaller in thickness than the tape base material 1a, and then sealing is performed using a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a is set to correspond to a stress neutral plane of the TCP as a whole.Type: GrantFiled: July 20, 1999Date of Patent: December 16, 2003Assignee: Hitachi, Ltd.Inventors: Kunihiro Tsubosaki, Toshio Miyamoto
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Patent number: 6656829Abstract: A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.Type: GrantFiled: December 31, 2002Date of Patent: December 2, 2003Assignee: Hitachi, Ltd.Inventor: Toshio Miyamoto
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Publication number: 20030209740Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: ApplicationFiled: April 25, 2003Publication date: November 13, 2003Applicant: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 6630731Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: January 22, 2002Date of Patent: October 7, 2003Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Publication number: 20030162326Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is smaller in thickness than the tape base material 1a, and then sealing is performed by a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a is set to correspond to a stress neutral plane of the TCP as a whole.Type: ApplicationFiled: May 1, 2003Publication date: August 28, 2003Inventors: Kunihiro Tsubosaki, Toshio Miyamoto
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Patent number: 6611012Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: January 22, 2002Date of Patent: August 26, 2003Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 6589855Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.Type: GrantFiled: November 26, 2001Date of Patent: July 8, 2003Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
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Publication number: 20030124830Abstract: A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.Type: ApplicationFiled: December 31, 2002Publication date: July 3, 2003Inventor: Toshio Miyamoto
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Publication number: 20030118363Abstract: An image heating apparatus includes a rotatable member; back-up means for cooperating with the rotatable member to form a feeding nip for feeding a recording material; heating means for heating an outer peripheral surface of the rotatable member, the heating means including a heater in the form of a plate cooperable with the rotatable member to form a heating nip.Type: ApplicationFiled: October 4, 2002Publication date: June 26, 2003Applicant: Canon Kabushiki KaishaInventors: Satoru Izawa, Masahiro Goto, Toshio Miyamoto, Masahiko Suzumi, Eiji Uekawa, Koji Nihonyanagi
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Publication number: 20030116835Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.Type: ApplicationFiled: December 31, 2001Publication date: June 26, 2003Applicant: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Toshio Sugano
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Patent number: 6573158Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.Type: GrantFiled: November 26, 2001Date of Patent: June 3, 2003Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Kunihiro Tsubosaki, Mitsuo Usami
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Publication number: 20030089978Abstract: The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, /TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.Type: ApplicationFiled: December 23, 2002Publication date: May 15, 2003Applicant: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Toshio Sugano
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Patent number: 6531768Abstract: A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.Type: GrantFiled: September 14, 2001Date of Patent: March 11, 2003Assignee: Hitachi, Ltd.Inventor: Toshio Miyamoto
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Patent number: 6518664Abstract: A laser beam is irradiated onto a photocurable resin layer formed on an electrode part before rearrangement. By scanning the resin on the periphery of a metal wiring formation area extending from the electrode part before rearrangement to a bump electrode contact area, is cured. As a result, a cured resin part is formed which works as a guide layer and a protection film for protecting the metal wire in which the metal wiring formation area has a hollow shape. Thereafter, the metal wire is formed inside the cured resin part.Type: GrantFiled: March 14, 2001Date of Patent: February 11, 2003Assignee: Hitachi, Ltd.Inventor: Toshio Miyamoto
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Publication number: 20030024452Abstract: The present invention, the objective of which is to provide a threading device for embroidery machinery realized in such a way that it performs threading accurately regardless of the type of thread, for embroidery machinery, etc. capable of performing the processing for change of colored thread automatically without intervention of an operator, for example, comprises a needle support mechanism (7), disposed movably facing the hooking member (61a), for preventing deflection of the needle (10), by correcting deflection of the needle (10), when inserting the hooking member (61a) formed in the shape of a hook at the tip of the thread pull-out mechanism (61) in the needle hole (10a).Type: ApplicationFiled: September 5, 2002Publication date: February 6, 2003Inventors: Toshio Miyamoto, Teruya Miyamoto
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Patent number: 6492719Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.Type: GrantFiled: October 26, 2001Date of Patent: December 10, 2002Assignee: Hitachi, Ltd.Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
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Patent number: 6493521Abstract: An object of the present invention is to provide an image forming apparatus having a fixing device, which can obtain good fixing ability while preventing occurrence of hot offset. The present invention provides an image forming apparatus that has image forming means for forming an image on a recording material, a heating member for heating the image on the recording material, a backup roller forming a nip with the heating member, a temperature detecting element for detecting a temperature of an atmosphere, and control means for controlling a power supply to the heating member, wherein when a print signal is inputted, the control means controls power supply (electrical communication) to the heating member in such a manner that the heating member maintains a set temperature in accordance with a detection temperature of the temperature detecting element, and, thereafter, a fixing operation is effected.Type: GrantFiled: February 8, 2001Date of Patent: December 10, 2002Assignee: Canon Kabushiki KaishaInventors: Toshio Miyamoto, Hiroto Hasegawa, Satoru Izawa, Masahiko Suzumi
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Publication number: 20020180010Abstract: A semiconductor chip 2 is disposed within a device hole as formed in a tape base material 1a of a tape carrier 1, which chip is less in thickness than the tape base material 1a, while sealing by a seal resin 3 to permit both the principal surface and back surface of such semiconductor chip 2 to be coated therewith. And, let the position of the semiconductor chip 2 in a direction along the thickness of the tape base 1a be identical to a stress neutral plane of the TCP as a whole.Type: ApplicationFiled: July 20, 1999Publication date: December 5, 2002Inventors: KUNIHIRO TSUBOSAKI, TOSHIO MIYAMOTO
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Publication number: 20020153539Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.Type: ApplicationFiled: April 23, 2002Publication date: October 24, 2002Inventors: Toshio Miyamoto, Ichiro Anjo, Asao Nishimura, Yoshihide Yamaguchi