Patents by Inventor Toshiyuki Sasaki

Toshiyuki Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490415
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes simultaneously flowing a first gas with a second gas containing a metal element to form a first opening in the second film and forming a third film containing the metal element on a side surface of the first opening. The method further includes forming a second opening in the first film below the first opening using the second film as a mask.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: November 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsubasa Imamura, Atsushi Takahashi, Toshiyuki Sasaki
  • Publication number: 20190291290
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Toshiyuki SASAKI
  • Publication number: 20190290102
    Abstract: There is provided a medical observation apparatus, including: a medical imaging section configured to image an observation target; a support section configured to support the medical imaging section on a front end side; at least one grip detecting section installed on an outer circumference of the medical imaging section and configured to detect a grip of a user; and a control section configured to control the medical imaging section or the support section on the basis of a detection result of the grip detecting section.
    Type: Application
    Filed: February 13, 2019
    Publication date: September 26, 2019
    Applicant: Sony Olympus Medical Solutions Inc.
    Inventor: Toshiyuki Sasaki
  • Patent number: 10369715
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: August 6, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Toshiyuki Sasaki
  • Publication number: 20190074249
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked body that alternately includes a plurality of first films and a plurality of second films on a substrate. The method further includes performing a first process of forming N2 holes having N kinds of depths in the stacked body where N is an integer of three or more. The method further includes performing a second process of processing the N2 holes so as to have N2 kinds of depths after performing the first process.
    Type: Application
    Filed: February 5, 2018
    Publication date: March 7, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki SASAKI
  • Patent number: 10176543
    Abstract: [Object] To generate a color image with further improved image quality. [Solution] Provided is an image processing device including: an image acquisition unit that acquires a far-infrared image, a near-infrared image, and a visible light image in which a common imaged object is captured; and a generation unit that generates a color image by filtering filter taps including pixels of the far-infrared image, the near-infrared image, and the visible light image.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: January 8, 2019
    Assignee: SONY CORPORATION
    Inventors: Kenichiro Hosokawa, Takuro Kawai, Masatoshi Yokokawa, Toshiyuki Sasaki, Kazunori Kamio
  • Publication number: 20180280855
    Abstract: A medical electronic apparatus includes: a casing including a lid portion provided with: a first inlet duct; a second inlet duct; and an outlet duct, the lid portion being configured to open the second inlet duct when the first inlet duct is blocked; a detection unit configured to detect an open/close state of the lid portion; and an output unit configured to output information regarding blockage of the first inlet duct based on a detection result of the detection unit.
    Type: Application
    Filed: February 26, 2018
    Publication date: October 4, 2018
    Applicant: Sony Olympus Medical Solutions Inc.
    Inventor: Toshiyuki SASAKI
  • Publication number: 20180261466
    Abstract: A method of manufacturing a semiconductor device includes forming a mask layer including aluminum or an aluminum compound on a layer to be etched comprising at least one first metal selected from tungsten, tantalum, zirconium, hafnium, molybdenum, niobium, ruthenium, osmium, rhenium, and iridium. The method of manufacturing a semiconductor device further includes patterning the mask layer, and etching the layer to be etched by using the patterned mask layer to form a hole or a groove in the layer to be etched.
    Type: Application
    Filed: September 5, 2017
    Publication date: September 13, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi YAMAZAKI, Kazuhito FURUMOTO, Kosuke HORIBE, Keisuke KIKUTANI, Atsuko SAKATA, Junichi WADA, Toshiyuki SASAKI
  • Patent number: 10068796
    Abstract: A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Sasaki
  • Patent number: 10038032
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Toshiyuki Sasaki
  • Publication number: 20180090369
    Abstract: A semiconductor device manufacturing method includes forming a first hole in a first processed layer. A first sacrificial film is formed in the first hole. A hole portion is formed in the first sacrificial film. A second sacrificial film is formed in the hole portion. A second processed layer is formed above the first sacrificial film and the second sacrificial film, and a second hole is formed in the second processed layer to expose the second sacrificial film. A third sacrificial film is formed on an inner side surface of the second hole, and a fourth sacrificial film is formed on the third sacrificial film. The second sacrificial film is etched using the fourth sacrificial film as a mask. The third sacrificial film exposed by etching the second sacrificial film is etched. The second processed layer is etched using the third sacrificial film as a mask.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 29, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki SASAKI
  • Publication number: 20180079096
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Application
    Filed: November 21, 2017
    Publication date: March 22, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Toshiyuki Sasaki
  • Patent number: 9876022
    Abstract: A method for manufacturing a semiconductor device includes forming a resist film on a film to be processed. An upper portion of the film to be processed is processed using the resist film as a first mask. Tungsten or a tungsten compound is selectively formed on the resist film. A lower portion of the film to be processed is processed with a reducing gas using the tungsten or the tungsten compound as a second mask.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomo Hasegawa, Kazuhisa Matsuda, Toshiyuki Sasaki, Mitsuhiro Omura
  • Patent number: 9871054
    Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 16, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tsubasa Imamura, Atsushi Takahashi, Toshiyuki Sasaki
  • Patent number: 9865618
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Toshiyuki Sasaki
  • Patent number: 9857829
    Abstract: There is provided an information processing apparatus including a case which is provided with an opening. Two or more functional units are allocated to the opening.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 2, 2018
    Assignee: SONY CORPORATION
    Inventors: Shuhei Yukawa, Masayoshi Koganei, Toshiyuki Sasaki, Takashi Enomoto
  • Publication number: 20170372444
    Abstract: [Object] To generate a color image with further improved image quality. [Solution] Provided is an image processing device including: an image acquisition unit that acquires a far-infrared image, a near-infrared image, and a visible light image in which a common imaged object is captured; and a generation unit that generates a color image by filtering filter taps including pixels of the far-infrared image, the near-infrared image, and the visible light image.
    Type: Application
    Filed: November 2, 2015
    Publication date: December 28, 2017
    Inventors: KENICHIRO HOSOKAWA, TAKURO KAWAI, MASATOSHI YOKOKAWA, TOSHIYUKI SASAKI, KAZUNORI KAMIO
  • Publication number: 20170366722
    Abstract: [Object] To effectively avoid image capturing competition in a scene in which a large number of infrared cameras capture images. [Solution] Provided is an imaging control apparatus including: an image acquisition unit that acquires an infrared image generated by an infrared camera imaging reflected light of emitted infrared rays; and a control unit that controls a setting for the generation of the infrared image on the basis of a control parameter transmitted to another apparatus or received from another apparatus via a communication interface.
    Type: Application
    Filed: November 26, 2015
    Publication date: December 21, 2017
    Inventors: TAKURO KAWAI, MASATOSHI YOKOKAWA, TOSHIYUKI SASAKI
  • Publication number: 20170352290
    Abstract: To make it possible to reduce a human load for a cutaneous sensation control setting corresponding to an image. Provided is an image processing device including: an infrared image acquisition unit that acquires an infrared image of an imaged object; a visible light image acquisition unit that acquires a visible light image of the imaged object; a generation unit that generates cutaneous sensation control parameters on the basis of the infrared image acquired by the infrared image acquisition unit; and a data processing unit that associates the visible light image acquired by the visible light image acquisition unit with the cutaneous sensation control parameters generated by the generation unit.
    Type: Application
    Filed: October 9, 2015
    Publication date: December 7, 2017
    Inventors: TOSHIYUKI SASAKI, TAKAHIRO NAGANO, MASATOSHI YOKOKAWA, TAKEFUMI NAGUMO
  • Publication number: 20170301686
    Abstract: According to one embodiment, the stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers have a plurality of terrace portions arranged in a stairstep configuration with a difference in levels. The insulating layer is provided above the terrace portions. The columnar portions extend in a stacking direction of the stacked body through the insulating layer and through the stacked body under the insulating layer. The columnar portions are insulative. The contact portions are provided at side surfaces of the columnar portions on the terrace portions. The contact portions are connected to the terrace portions.
    Type: Application
    Filed: September 6, 2016
    Publication date: October 19, 2017
    Inventors: Tsubasa IMAMURA, Atsushi Takahashi, Toshiyuki Sasaki