Patents by Inventor Toshiyuki Sasaki

Toshiyuki Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170263611
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a substrate. The method further includes forming a second film on the first film. The method further includes simultaneously flowing a first gas with a second gas containing a metal element to form a first opening in the second film and forming a third film containing the metal element on a side surface of the first opening. The method further includes forming a second opening in the first film below the first opening using the second film as a mask.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 14, 2017
    Inventors: Tsubasa IMAMURA, Atsushi TAKAHASHI, Toshiyuki SASAKI
  • Patent number: 9754888
    Abstract: A semiconductor memory device according to one embodiment includes a plurality of lower electrode films stacked separated from each other, an upper electrode film provided above the plurality of lower electrode films, a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film, a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film, and a metal-containing layer provided at least one of on a lower surface and an upper surface of the one of the plurality of lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films. The upper electrode film is in contact with the memory film.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: September 5, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuhito Furumoto, Toshiyuki Sasaki
  • Patent number: 9701142
    Abstract: A small, compact multifunction printing device provides excellent ease of use with little possibility of slips and continuous paper jamming inside. The multifunction printer has a check processing unit and a continuous paper processing unit. The check processing unit has a U-shaped check conveyance path P1 that opens to the front of the printer and enables handling slips to be processed and the processed slips from the front of the printer. A continuous paper conveyance path P2 that conveys continuous paper fed from a paper roll in the roll paper compartment from the back to the front of the printer is formed on the inside of the check conveyance path P1, enabling replacing roll paper and removing processed continuous paper from the front. The conveyance paths P1 and P2 are independent of each other, the printing positions thereof are separated, and conveyed slips and continuous paper will not interfere with each other.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 11, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Toshiyuki Sasaki, Yoshiki Kinoshita, Shogo Mizuyama
  • Publication number: 20170170125
    Abstract: A semiconductor memory device according to one embodiment includes a plurality of lower electrode films stacked separated from each other, an upper electrode film provided above the plurality of lower electrode films, a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode film, a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the semiconductor pillar and the upper electrode film, and a metal-containing layer provided at least one of on a lower surface and an upper surface of the one of the plurality of lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing layer having a composition different from a composition of the plurality of lower electrode films. The upper electrode film is in contact with the memory film.
    Type: Application
    Filed: April 20, 2016
    Publication date: June 15, 2017
    Inventors: Kazuhito FURUMOTO, Toshiyuki SASAKI
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Publication number: 20170148816
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventor: Toshiyuki SASAKI
  • Patent number: 9627404
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes exposing the first sacrificial film on the bottom by removing the second sacrificial film on the bottom. The method includes making a gap between the second sacrificial film and a side surface of the lower portion of the hole by causing etching of the first sacrificial film to progress along the side surface of the lower portion of the hole from the exposed portion on the bottom. The method includes causing an end of at least one portion of the lower layer portion of the etching layer to recede in a diametrical direction of the hole by causing side etching to progress from an end of the lower layer portion of the etching layer exposed in the gap.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Sasaki
  • Patent number: 9608002
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: March 28, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Sasaki
  • Publication number: 20170062458
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes exposing the first sacrificial film on the bottom by removing the second sacrificial film on the bottom. The method includes making a gap between the second sacrificial film and a side surface of the lower portion of the hole by causing etching of the first sacrificial film to progress along the side surface of the lower portion of the hole from the exposed portion on the bottom. The method includes causing an end of at least one portion of the lower layer portion of the etching layer to recede in a diametrical direction of the hole by causing side etching to progress from an end of the lower layer portion of the etching layer exposed in the gap.
    Type: Application
    Filed: January 15, 2016
    Publication date: March 2, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiyuki SASAKI
  • Patent number: 9519849
    Abstract: An image processing device allows for easy removal of a process medium stuck in the conveyance path while protecting the image processing unit from the outside. In many embodiments, the device includes a conveyance path for conveying process media in a specific conveyance direction, an image processing unit having an ejection surface (process surface) disposed facing the conveyance path, and a first cover and a second cover disposed along the conveyance path and covering the conveyance path. Typically, the first and second covers open and close by pivoting on first and second pivot pins disposed in a direction intersecting the conveyance direction, and the first and second pivot pins are disposed adjacent the conveyance path upstream and downstream of the portion of the conveyance path facing the ejection surface.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 13, 2016
    Assignee: Seiko Epson Corporation
    Inventor: Toshiyuki Sasaki
  • Publication number: 20160357218
    Abstract: There is provided an information processing apparatus including a case which is provided with an opening. Two or more functional units are allocated to the opening.
    Type: Application
    Filed: August 19, 2016
    Publication date: December 8, 2016
    Inventors: SHUHEI YUKAWA, MASAYOSHI KOGANEI, TOSHIYUKI SASAKI, TAKASHI ENOMOTO
  • Publication number: 20160347096
    Abstract: A small, compact multifunction printing device provides excellent ease of use with little possibility of slips and continuous paper jamming inside. The multifunction printer has a check processing unit and a continuous paper processing unit. The check processing unit has a U-shaped check conveyance path P1 that opens to the front of the printer and enables handling slips to be processed and the processed slips from the front of the printer. A continuous paper conveyance path P2 that conveys continuous paper fed from a paper roll in the roll paper compartment from the back to the front of the printer is formed on the inside of the check conveyance path P1, enabling replacing roll paper and removing processed continuous paper from the front. The conveyance paths P1 and P2 are independent of each other, the printing positions thereof are separated, and conveyed slips and continuous paper will not interfere with each other.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 1, 2016
    Inventors: Toshiyuki Sasaki, Yoshiki Kinoshita, Shogo Mizuyama
  • Patent number: 9502470
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate including a major surface; a plurality of first films having conductivity or semiconductivity, the first films being provided above the substrate and extending in a first direction inclined with respect to the major surface; a plurality of second films having conductivity, the second films being provided above the substrate and extending in a second direction inclined with respect to the major surface and crossing the first direction; and a plurality of storage films provided in crossing sections of the first films and the second films.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: November 22, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Takahashi, Toshiyuki Sasaki, Tsubasa Imamura
  • Publication number: 20160329346
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Application
    Filed: July 19, 2016
    Publication date: November 10, 2016
    Inventor: Toshiyuki SASAKI
  • Publication number: 20160268339
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first wirings, second wirings, a plurality of memory cells, selection gate transistors, and a third wiring. The first wirings are disposed in a first direction along a surface of a substrate and in a second direction intersecting with the surface of the substrate. The selection gate transistors are connected to respective one ends of the second wirings. The third wiring is connected in common to one end of the selection gate transistors. The selection gate transistor includes first to third semiconductor layers laminated on the third wiring and a gate electrode. The gate electrode is opposed to the second semiconductor layer in the first direction. The second semiconductor layer has a length in the first direction smaller than lengths of the first semiconductor layer and the third semiconductor layer in the first direction.
    Type: Application
    Filed: March 7, 2016
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiwamu SAKUMA, Shosuke FUJII, Masumi SAITOH, Toshiyuki SASAKI
  • Patent number: 9436216
    Abstract: There is provided an information processing apparatus including a case which is provided with an opening. Two or more functional units are allocated to the opening.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: September 6, 2016
    Assignee: SONY CORPORATION
    Inventors: Shuhei Yukawa, Masayoshi Koganei, Toshiyuki Sasaki, Takashi Enomoto
  • Patent number: 9425211
    Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toshiyuki Sasaki
  • Patent number: 9413911
    Abstract: A media processing device enables conveying media fed from different paths into a common path in a stable conveyance state to the scanning position of a scanner. A check processing device has a path switching member that selectively bridges a back path for conveying checks and a card path to a downstream path, which is a common path. The path switching member changes position and switches the connected paths in conjunction with movement of a shutter that covers the open part of a nozzle cap used to cap the nozzle face of the inkjet head at the back path.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 9, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Toshiyuki Sasaki, Nobuhiro Inoue
  • Publication number: 20160197090
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked mask on a layer to be processed. The stacked mask has a plurality of intermediate films and a plurality of mask films alternately stacked. The method includes forming a stair-shaped portion in a top-layer first intermediate film. The forming the stair-shaped portion includes sliming a top-layer mask film, and etching the first intermediate film exposed by the slimming of the top-layer mask film. The method includes forming a first stair-shaped portion in a second intermediate film by transferring the stair-shaped portion of an upper intermediate film. The method includes forming a second stair-shaped portion following the first stair-shaped portion in the second intermediate film. The forming the second stair-shaped portion includes slimming a mask film immediately above the second intermediate film, and etching the second intermediate film.
    Type: Application
    Filed: June 1, 2015
    Publication date: July 7, 2016
    Inventor: Toshiyuki SASAKI
  • Patent number: 9381753
    Abstract: A small, compact multifunction printing device provides excellent ease of use with little possibility of slips and continuous paper jamming inside. The multifunction printer has a check processing unit and a continuous paper processing unit. The check processing unit has a U-shaped check conveyance path P1 that opens to the front of the printer and enables handling slips to be processed and the processed slips from the front of the printer. A continuous paper conveyance path P2 that conveys continuous paper fed from a paper roll in the roll paper compartment from the back to the front of the printer is formed on the inside of the check conveyance path P1, enabling replacing roll paper and removing processed continuous paper from the front. The conveyance paths P1 and P2 are independent of each other, the printing positions thereof are separated, and conveyed slips and continuous paper will not interfere with each other.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 5, 2016
    Assignee: Seiko Epson Corporation
    Inventors: Toshiyuki Sasaki, Yoshiki Kinoshita, Shogo Mizuyama