Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate.

Abstract: A method for producing Si ingot single crystal by NOC growth method including a Si ingot single crystal growing step and a continuous growing step is provided. The growing step includes providing a low temperature region in the Si melt where the Si ingot single crystal is grown along the surface of the Si melt or toward the inside of the Si melt, and the Si ingot single crystal has distribution of a vacancy concentration and an interstitial concentration in which respectively a vacancy concentration and an interstitial concentration vary with a distance from the growth interface; and adjusting a temperature gradient and a growth rate in the Si melt, so that along with the increasing of the distance from the growth interface, the vacancy concentration and the interstitial concentration in the Si ingot single crystal respectively decrease come near to each other.

Abstract: A method of manufacturing an epitaxy substrate is provided. A handle substrate is provided. A beveling treatment is performed on an edge of a device substrate such that a bevel is formed at the edge of the device substrate, wherein a thickness of the device substrate is greater than 100 ?m and less than 200 ?m. An ion implantation process is performed on a first surface of the device substrate to form an implantation region within the first surface. A second surface of the device substrate is bonded to the handle substrate for forming the epitaxy substrate, wherein a bonding angle greater than 90° is provided between the bevel of the device substrate and the handle substrate, and a projection length of the bevel toward the handle substrate is between 600 ?m and 800 ?m.

Abstract: A mono-crystalline silicon growth apparatus is provided. The mono-crystalline silicon growth apparatus includes a furnace, a support base disposed in the furnace, a crucible disposed on the support base, and a heating module. The support base and the crucible do not rotate relative to the heating module, and an axial direction is defined to be along a central axis of the crucible. The heating module is disposed at an outer periphery of the support base and includes a first heating unit, a second heating unit, and a third heating unit. The first heating unit, the second heating unit, and the third heating unit are respectively disposed at positions with different heights corresponding to the axial direction.

Abstract: A semiconductor device includes a substrate, an initial layer, and a superlattice stack. The initial layer is located on the substrate and includes aluminum nitride (AlN). The superlattice stack is located on the initial layer and includes a plurality of first films, a plurality of second films and at least one doped layer, and the first films and the second films are alternately stacked on the initial layer, wherein the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.

Abstract: A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 ?-cm.

Abstract: A mono-crystalline silicon growth apparatus includes a furnace, a support base, a crucible, a heating module disposed outside of the crucible, and a heat adjusting module above the crucible. The heat adjusting module includes a diversion tube, a plurality of heat preservation sheets, and a hard shaft. The diversion tube includes a tube body and a carrying body connected to the tube body. The heat preservation sheets are sleeved around the tube body and are stacked and disposed on the carrying body. The hard shaft passes through the tube body and does not rotate. The hard shaft includes a water flow channel disposed therein and a clamping portion configured to clamp a seed crystal. Therefore, a fluid injected into the water flow channel takes away the heat near the clamping portion. A heat adjusting module and a hard shaft of the mono-crystalline silicon growth apparatus are provided.

Abstract: A mono-crystalline silicon growth method includes: providing a furnace, a supporting base and a crucible which do not rotate relative to the furnace, and a heating module disposed at an outer periphery of the supporting base. After solidifying a liquid surface of a silicon melt in the crucible to form a crystal, the heating power of the heating module is successively reduced to appropriately adjust the temperature around the crucible to effectively control a temperature gradient of a thermal field around the crucible, so as to form a mono-crystalline silicon ingot by solidifying the silicon melt.

Abstract: A bonded substrate for epitaxial growth and a method for forming the same are disclosed. The method includes steps of providing a first substrate, which has a first dopant concentration; providing a second substrate, which has a second dopant concentration, wherein the second dopant concentration is lower than the first dopant concentration; directly bonding a first surface of the first substrate with a second surface of the second substrate to form a bonded substrate; annealing the bonded substrate to form a high impedance layer in the bonded substrate; and removing part of the second substrate to expose the high impedance layer depending on the requirements whereby, the bonded substrate formed by the method could have a heavily doped substrate which includes a stronger strength and the impedance layer formed thereon, which could effectively increase the substrate strength, reduce the leakage current, and sustains a higher breakdown voltage.

Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a silicon substrate and a silicon carbide layer. The silicon substrate has a first surface and a second surface opposite to each other, and the first surface is an epitaxy surface. The silicon carbide layer is located in the silicon substrate, and a distance between the silicon carbide layer and the first surface is between 100 angstroms (?) and 500 angstroms.

Abstract: A wafer carrier for processing a plurality of wafers includes a carrier body which rotatable about a central axis, and a plurality of pockets formed in the carrier body. Each of the pockets has an access opening and an inner periphery surface extending from the access opening to terminate at a floor surface. A lower periphery region of the inner periphery surface has a most distal region which is most distal from the central axis. When the carrier body is rotated about the central axis, a corresponding one of the wafers is less likely to be damaged due to a centrifugal force applied to the corresponding one of the wafers.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate has an epitaxy region located at a central portion of a main plane of the semiconductor substrate, a periphery region surrounding the epitaxy region and an injured region distributed inside the periphery region.

Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.

Abstract: An epitaxy substrate and a method of manufacturing the same are provided. The epitaxy substrate includes a device substrate and a handle substrate. The device substrate has a first surface and a second surface opposite to each other, and a bevel disposed between the first and the second surfaces. The handle substrate is bonded to the second surface of the device substrate, wherein the oxygen content of the device substrate is less than the oxygen content of the handle substrate, and a bonding angle greater than 90° is between the bevel of the device substrate and the handle substrate.

Abstract: An epitaxial substrate and a method of manufacturing the same are provided. The epitaxial substrate includes a handle substrate, a heat dissipation layer on the handle substrate, a high-resistance silicon substrate on the heat dissipation layer, and a III-V semiconductor layer grown on the high-resistance silicon substrate. The heat dissipation layer has high thermal conductivity. The high-resistance silicon substrate has a resistance more than 100 ohm·cm. Diameters of the high-resistance silicon substrate and the III-V semiconductor film are smaller than a diameter of the handle substrate, such that the epitaxial substrate is a convex substrate.

Abstract: A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition AlxInyGa1-x-yN, where x?1 and y?0; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers.

Abstract: A polycrystalline silicon column is provided. The polycrystalline silicon column includes a plurality of silicon grains grown along a crystal-growing direction. In the crystal-growing direction, the average grain size of the silicon grains and the resistivity of the polycrystalline silicon column have opposite variation in their trends, the average grain size of the silicon grains and the oxygen content of the polycrystalline silicon column have opposite variation in their trends, and the average grain size of the silicon grains and the defect area ratio of the polycrystalline silicon column have the same variation in their trends. The overall average defect area ratio of the polycrystalline silicon column is less than or equal to 2.5%.

Abstract: A solar cell wafer is provided. It is a silicon wafer, and a surface of the silicon wafer has a plurality of pores, wherein based on a total amount of 100% of the plurality of pores, 60% or more of the pores has a circularity greater than 0.5. Therefore, the reflectance of the solar cell wafer can be efficiently reduced.

Abstract: A crystalline silicon ingot and a method of fabricating the same are disclosed. The crystalline silicon ingot of the invention includes multiple silicon crystal grains growing in a vertical direction of the crystalline silicon ingot. The crystalline silicon ingot has a bottom with a silicon crystal grain having a first average crystal grain size of less than about 12 mm. The crystalline silicon ingot has an upper portion, which is about 250 mm away from said bottom, with a silicon crystal grain having a second average crystal grain size of greater than about 14 mm.

Abstract: The present disclosure provides a polycrystalline silicon ingot. The polycrystalline silicon ingot has a vertical direction and includes a nucleation promotion layer located at a bottom of the polycrystalline silicon ingot, and silicon grains grown along the vertical direction, wherein the silicon grains include at least three crystal directions. The coefficient of variation of grain area in a section above the nucleation promotion layer of the polycrystalline silicon ingot increases along the vertical direction.