Patents by Inventor Yusuke Igarashi

Yusuke Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9024446
    Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 5, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Ryosuke Usui, Yusuke Igarashi, Yasunori Inoue, Mayumi Nakasato, Masayuki Nagamatsu, Yasuhiro Kohara
  • Publication number: 20130199827
    Abstract: A mounting board includes: a core layer made of an insulating resin; a first conductive pattern provided on a front side of the core layer; a second conductive pattern provided on a back side of the core layer; and a via provided between a first electrode for a high current in the first conductive pattern and an external electrode including the second conductive pattern, the external electrode provided so as to correspond to the first electrode, the first conductive pattern and the second conductive pattern having the same film thickness, the via set at a resistance value lower than a resistance value of the first conductive pattern so that the high current flows to the external electrode through the via.
    Type: Application
    Filed: August 9, 2012
    Publication date: August 8, 2013
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Atsushi Kato, Toshimichi Naruse
  • Patent number: 8436250
    Abstract: A circuit device of the present invention includes a wiring board 45, and circuit elements such as semiconductor elements 32 mounted on the wiring board 45. The wiring board 45 includes: a conductive pattern 12, which is a metal core layer; a first insulating layer 14 and a second insulating layer 16 respectively covering an upper surface and a lower surface of the conductive pattern 12; and a first wiring layer 18 and a second wiring layer 20 formed respectively on an upper surface of the first insulating layer 14 and a lower surface of the second insulating layer 16. The conductive pattern 12 is made of rolled metal. With this configuration, the thermal resistance of the conductive pattern 12, which is the metal core, is reduced, and the thermal dissipation of the entire device can be improved.
    Type: Grant
    Filed: November 29, 2007
    Date of Patent: May 7, 2013
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Kouji Takahashi, Yusuke Igarashi, Jun Sakano
  • Publication number: 20130003314
    Abstract: Provided is a substrate wherein wiring layers laminated onto the top and bottom surfaces of a core layer are connected to each other by a simple means. Also provided is a method for manufacturing said substrate. In the provided substrate (10A), a connection substrate (13) is placed in a removed region (12) which goes all the way through a part of a thick core layer (11). Said connection substrate (13) electrically connects a first wiring layer (16A) laminated onto the top surface of the core layer (11) to a second wiring layer (16B) laminated onto the bottom surface of the core layer (11). This eliminates the requirement of providing a through-hole through the core layer (11) for each connection, resulting in a small form-factor substrate (10A) with a high wiring density.
    Type: Application
    Filed: February 21, 2011
    Publication date: January 3, 2013
    Applicant: SANYO ELECTRONIC CO., LTD.
    Inventors: Yusuke Igarashi, Takeshi Nakamura
  • Publication number: 20120098137
    Abstract: Conventional printed circuit boards had a problem of being inferior in heat-radiation characteristic, and metal-core printed circuit boards adopted to improve the heat-radiation characteristic had problems in having low rigidity and a tendency to bend. The ductility of the metal can be obstructed, and the metal protected; by covering substantially the whole area of the front and back sides of the metal core, consisting of metal as the main material, with a first ceramic film and a second ceramic film that obstruct the ductility of the aforementioned metal-core; and covering each of the ceramic films with insulated resin films, to cover the fragility of these ceramics.
    Type: Application
    Filed: June 30, 2010
    Publication date: April 26, 2012
    Inventors: Ryosuke Usui, Yusuke Igarashi, Yasunori Inoue, Mayumi Nakasato, Masayuki Nagamatsu, Yasuhiro Kohara
  • Patent number: 8115316
    Abstract: A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having an opening at least in part in an area over the pad electrode; and a joint layer formed on the pad electrode inside the opening. The surface of the joint layer is lower than the top lip of the opening.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: February 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Kohara, Ryosuke Usui, Takeshi Nakamura, Yusuke Igarashi
  • Publication number: 20110241203
    Abstract: A semiconductor module includes a device mounting board and a semiconductor device. The semiconductor device and the device mounting board are flip-chip connected to each other, and a device electrode provided in the semiconductor device and a substrate electrode provided in the device mounting board are connected by soldering. In a cross section along a line connecting the adjacent substrate electrodes, the width L1 of the substrate electrode is narrower than the width L2 of the device electrode corresponding to the substrate electrode.
    Type: Application
    Filed: December 10, 2009
    Publication date: October 6, 2011
    Inventors: Mayumi Nakasato, Katsumi Ito, Ryosuke Usui, Yusuke Igarashi
  • Patent number: 7936569
    Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Patent number: 7854062
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: December 21, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Takeshi Nakamura
  • Patent number: 7768132
    Abstract: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: August 3, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Ryosuke Usul, Hideki Mizuhara
  • Patent number: 7714232
    Abstract: Provided are a hybrid integrated circuit device in which fine patterns can be formed while current-carrying capacitances are ensured, and a method of manufacturing the same. The hybrid integrated circuit device of the present invention includes conductive patterns formed on a front surface of a circuit substrate and circuit elements electrically connected respectively to the conductive patterns. The conductive patterns include a first conductive pattern and a second conductive pattern formed more thickly than the first conductive pattern. The second conductive pattern includes a protruding portion protruding in a thickness direction thereof.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 11, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Motoichi Nezu, Takaya Kusabe
  • Publication number: 20100012360
    Abstract: A circuit device of the present invention includes a wiring board 45, and circuit elements such as semiconductor elements 32 mounted on the wiring board 45. The wiring board 45 includes: a conductive pattern 12, which is a metal core layer; a first insulating layer 14 and a second insulating layer 16 respectively covering an upper surface and a lower surface of the conductive pattern 12; and a first wiring layer 18 and a second wiring layer 20 formed respectively on an upper surface of the first insulating layer 14 and a lower surface of the second insulating layer 16. The conductive pattern 12 is made of rolled metal. With this configuration, the thermal resistance of the conductive pattern 12, which is the metal core, is reduced, and the thermal dissipation of the entire device can be improved.
    Type: Application
    Filed: November 29, 2007
    Publication date: January 21, 2010
    Inventors: Kouji Takahashi, Yusuke Igarashi, Jun Sakano
  • Publication number: 20090194322
    Abstract: A device mounting board has a double-layer wiring structure where a first wiring layer and a second wiring layer are stacked together with an insulating layer held between the first and second wiring layers. The first wiring layer and the second wiring layer are electrically connected by way of a via conductor provided on a side wall of a through-hole that penetrates the insulating layer. The through-hole that penetrates the insulating layer has a stepped portion. The via conductor, provided along the insulating layer in the via conductor, has a step associated with the stepped portion of the via conductor.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Inventors: Ryosuke USUI, Takeshi Nakamura, Tomohiro Kuzuu, Yusuke Igarashi
  • Patent number: 7565738
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: July 28, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato Abe
  • Publication number: 20090119915
    Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.
    Type: Application
    Filed: January 12, 2009
    Publication date: May 14, 2009
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato Aba, Takeshi Nakamura
  • Publication number: 20080123299
    Abstract: A circuit device exhibiting excellent heat radiation properties and a manufacturing method thereof are hereby provided. A circuit device comprises a circuit board, an insulating layer formed on the circuit board, a conductive pattern formed on the insulating layer, a circuit element electrically connected to the conductive pattern, wherein a protrusion partially extending and being buried in the insulating layer is provided on the circuit board. Accordingly, heat generated inside the device can be efficiently discharged to the exterior via the protrusion.
    Type: Application
    Filed: March 24, 2005
    Publication date: May 29, 2008
    Inventors: Sadamichi Takakusaki, Yusuke Igarashi, Motoichi Nezu, Takaya Kusabe
  • Publication number: 20080106875
    Abstract: Provided are a hybrid integrated circuit device in which fine patterns can be formed while current-carrying capacitances are ensured, and a method of manufacturing the same. The hybrid integrated circuit device of the present invention includes conductive patterns formed on a front surface of a circuit substrate and circuit elements electrically connected respectively to the conductive patterns. The conductive patterns include a first conductive pattern and a second conductive pattern formed more thickly than the first conductive pattern. The second conductive pattern includes a protruding portion protruding in a thickness direction thereof.
    Type: Application
    Filed: February 18, 2005
    Publication date: May 8, 2008
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Motoichi Nezu, Takaya Kusabe
  • Patent number: 7364941
    Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: April 29, 2008
    Assignees: Sanyo Electric Co., Ltd., Kanto SANYO Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20080061437
    Abstract: A technology is provided for a packaging board adapted to mount a device capable of improving handleability and securing connection reliability. The packaging board includes: a pad electrode formed on a substrate; an insulating layer covering the substrate, having an opening at least in part in an area over the pad electrode; and a joint layer formed on the pad electrode inside the opening. The surface of the joint layer is lower than the top lip of the opening.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 13, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasuhiro Kohara, Ryosuke Usui, Takeshi Nakamura, Yusuke Igarashi
  • Patent number: 7329957
    Abstract: A method of manufacturing a circuit device includes the steps of preparing a conductive foil, forming conductive patterns in convex shapes by forming an isolation trench on a surface of the conductive foil, covering the surface of the conductive foil with a resin film so as to form the resin film covering the isolation trench thicker than the resin film covering upper surfaces of the conductive patterns, exposing the upper surfaces of the conductive patterns out of the resin film by removing the resin film, electrically connecting the conductive pattern exposed out of the resin film to a circuit element, forming sealing resin to seal the circuit element, and removing a rear surface of the conductive foil until the conductive patterns are mutually isolated.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: February 12, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Jun Sakano, Kouji Takahashi, Yusuke Igarashi