Patents by Inventor Yusuke Igarashi

Yusuke Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040256711
    Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).
    Type: Application
    Filed: August 29, 2003
    Publication date: December 23, 2004
    Applicant: Sanyo Electric Co., Ltd., a Osaka, Japan Corporation
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Patent number: 6812410
    Abstract: A first metal film 14 made of a Cu plated film is formed on a radiation substrate 13A made of Al, and an island 15 exposed from a back surface of a semiconductor device 10 is adhered thereto. At that time, the back surface of the semiconductor device 10 is brought into contact with contact areas, and a first opening portion OP is opened larger than an arranging area of the semiconductor device 10. Accordingly, the cleaning can be executed via the first opening portion OP exposed from peripheries of the semiconductor device 10. In addition, the heat generated from semiconductor elements 16 can be radiated excellently from the island 15 via a second supporting member 13A.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 2, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20040198050
    Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Since a conductive plated layer 4 is formed after through holes 21 are formed in the insulation resin 2 by using an insulation resin sheet 1 overcoated on a single side of the conductive layer 3 with insulation resin 2, a multi-layer connection structure can be achieved by the second conductive path layer 6 which is connected, in multi layers, to the first conductive path layer 5 formed by etching the conductive plated layer 4.
    Type: Application
    Filed: April 14, 2004
    Publication date: October 7, 2004
    Applicant: Sanyo Electric Co., Ltd., an Osaka Japan Corporation
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Patent number: 6791199
    Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided. Thickness of an electric connection means SD is substantially made definite as the electric connection means SD does not flow to a conductive path 11B by using a flow-prevention film DM.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: September 14, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20040169271
    Abstract: A circuit device 10 comprises conductive patterns 11, separated by separation grooves 41, circuit elements 12, affixed onto conductive patterns 11, and an insulating resin 13, covering circuit elements 12 and conductive patterns 11 and filling separation grooves 41 while exposing the rear surfaces of conductive patterns 11. Constricted parts 19 are formed at side surfaces of separation grooves 41. At constricted parts 19, the width of separation grooves 41 is made narrower than at other locations. Thus by making insulating resin 13 adhere closely to constricted parts 19, the adhesion of insulating resin 13 with conductive patterns 11 is improved.
    Type: Application
    Filed: December 11, 2003
    Publication date: September 2, 2004
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Patent number: 6780676
    Abstract: A conductive plated layer 4 is fanned after through holes 21 are formed in the insulation resin 2 by using an insulation resin sheet 1 overcoated on a single side of the conductive layer 3 with insulation resin 2. A multi-layer connection structure can be achieved by the second conductive path layer 6 which is connected, in multi layers, to the first conductive path layer 5 formed by etching the conductive plated layer 4. Further, since semiconductor elements 7 are adhered to and fixed at the overcoating resin 8 that covers the first conductive path layer 5, the first conductive path layer 5 is finely patterned, and routing thereof can be made free. Further, since the second conductive layer 4 that has been fanned to be thick can be thinly etched, the second conductive path layers 6 can be finely patterned.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: August 24, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Publication number: 20040159913
    Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.
    Type: Application
    Filed: December 11, 2003
    Publication date: August 19, 2004
    Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
  • Publication number: 20040152234
    Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, a reformed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.
    Type: Application
    Filed: December 1, 2003
    Publication date: August 5, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040152241
    Abstract: A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns 21 are removed using plasma to thereby improve the adhesion of conductive patterns 21 to a sealing resin 28. By selective etching of a conductive foil 10, separation grooves 11 are formed, thereby forming conductive patterns 21. A semiconductor element 22A and other circuit elements are mounted onto desired locations of conductive patterns 21 and electrically connected with conductive patterns 21. By irradiating plasma onto conductive foil 10 from above, contaminants attached to the surfaces of separation grooves 11 are removed.
    Type: Application
    Filed: December 1, 2003
    Publication date: August 5, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040140551
    Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.
    Type: Application
    Filed: December 3, 2003
    Publication date: July 22, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Kojima, Noriaki Sakamoto
  • Publication number: 20040136123
    Abstract: A shielding layer 14 is formed onto the circuit device 10. The backface of a conductive pattern 11 is exposed, and a shielding layer 14 made of a metal, such as copper, is formed on the upper surface of an insulating resin 13 with which a circuit element 12, a fine metal wire 16, and a conductive pattern 11 are covered. A connecting means 15 is formed on a through-hole 20 formed by removing a part of the insulating resin 13. The shielding layer 14 and the conductive pattern 11B are electrically connected together through the connecting means 15. Since the conductive pattern 11B at the part where the through-hole 20 is formed is a conductive pattern serving as an ground potential, the shielding layer 14 can be set at zero potential.
    Type: Application
    Filed: September 23, 2003
    Publication date: July 15, 2004
    Inventors: Takeshi Nakamura, Yusuke Igarashi, Noriaki Sakamoto, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040124516
    Abstract: A second conductive pattern 14 is provided on the upper surface of a circuit device 10. A second conductive pattern 14 is provided on the upper surface of an insulating resin 13 which seals a built-in first circuit element 12, etc., and a first conductive pattern 11 and the second conductive pattern 14 are electrically connected via connection means 15. Second circuit elements 22 are mounted on the second conductive pattern 14. Thus, circuit elements can be three-dimensionally mounted. Furthermore, since the circuit device 10 eliminates the need for a mounting substrate, a low-profile circuit device is provided.
    Type: Application
    Filed: November 5, 2003
    Publication date: July 1, 2004
    Inventors: Takeshi Nakamura, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040104043
    Abstract: The present invention discloses a method of manufacturing circuit devices 10 with arbitrary external shapes, comprising the steps of: forming, on a conductive foil 30, conductive patterns 11 constituting circuit devices 10 of the same type or different types; affixing circuit elements 12 onto conductive patterns 11; molding with insulating resin 13 so as to cover circuit elements 12; and using a laser to cut insulating resin 13 at locations of the outer peripheral part of each circuit device 10 that are in accordance with a desired shape to thereby perform separation into each of circuit devices 10. Circuit devices 10 with arbitrary shapes can thus be manufactured and circuit devices that accommodate the shapes of the frames of sets can be provided.
    Type: Application
    Filed: September 22, 2003
    Publication date: June 3, 2004
    Inventors: Noriyasu Sakai, Yusuke Igarashi
  • Publication number: 20040106235
    Abstract: Conventionally, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used. In a step for forming a conductive wiring layer 11A by etching the first conductive film 11, etching depth can be controlled by stopping etching at the third conductive film 13. Accordingly, forming the first conductive film 11 to be thin makes it possible to form the conductive wiring layer 11A into a fine pattern.
    Type: Application
    Filed: September 23, 2003
    Publication date: June 3, 2004
    Inventors: Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040106288
    Abstract: Semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur in that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin, first conductive film 11 and a thick, second conductive film 12 have been laminated via a third conductive film 13 is used. In a step for forming a first conductive wiring layer 11A by etching the first conductive film 11, etching depth can be controlled by a stop of etching at the third conductive film 13. Accordingly, forming the first conductive film 11 thin makes it possible to form the first conductive wiring layer 11A into a fine pattern.
    Type: Application
    Filed: September 22, 2003
    Publication date: June 3, 2004
    Inventors: Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040101995
    Abstract: In order to prevent, in a resin sealing step, a conductive foil 10 from locally rising because of concentration of air intervening between the conductive foil 10 and lower mold 28A due to the charged pressure, a method for manufacturing circuit devices is provided. The method for manufacturing circuit devices includes the step of forming conductive patterns 21, which form a plurality of mounting portions 15 of a circuit element 22 on a conductive foil 10, in each block 12, the step of disposing the circuit element 22 on each mounting portion 15 of the conductive pattern 21 in each block 12, the step of performing resin sealing by bringing the lower mold 28A having an air vent 30 into contact with the backface of the conductive foil 10 in each block 12 and by performing transfer molding with an insulating resin 20 while disposing each mounting portion 15 of the block 12 in the same cavity, and the step of separating each mounting portion 15 by dicing.
    Type: Application
    Filed: September 22, 2003
    Publication date: May 27, 2004
    Inventors: Noriyasu Sakai, Yusuke Igarashi, Masato Noguchi
  • Publication number: 20040097081
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a first conductive film 11 and a second conductive film 12 have been laminated via a third conductive film 13 is used. After forming a conductive pattern layer 11A by etching the first conductive film 11, anchor portions 15 are formed by overetching the third conductive film 13 by use of the conductive pattern layer 11A as a mask, and a sealing resin layer 22 is made to bite into the anchor portions 15 so as to strengthen bonding of the sealing resin layer 22 with the conductive pattern layer 11A.
    Type: Application
    Filed: September 17, 2003
    Publication date: May 20, 2004
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamota
  • Publication number: 20040097086
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.
    Type: Application
    Filed: September 17, 2003
    Publication date: May 20, 2004
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Publication number: 20040092129
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.
    Type: Application
    Filed: September 16, 2003
    Publication date: May 13, 2004
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Patent number: 6720209
    Abstract: A conductive plated layer 4 is formed after through holes 21 are formed in the insulation resin 2 by using an insulation resin sheet 1 overcoated on a single side of the conductive layer 3 with insulation resin 2. A multi-layer connection structure can be achieved by the second conductive path layer 6 which is connected, in multi layers, to the first conductive path layer 5 formed by etching the conductive plated layer 4. Further, since semiconductor elements 7 are adhered to and fixed at the overcoating resin 8 that covers the first conductive path layer 5, the first conductive path layer 5 is finely patterned, and routing thereof can be made free.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: April 13, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura