Patents by Inventor Yusuke Igarashi

Yusuke Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6706547
    Abstract: After conductive patterns are formed on the conductive foil every block by employing isolation trenches, conductive plating layers are arranged selectively on the conductive patterns. Therefore, it is possible to accomplish the circuit device manufacturing method by which the die bonding of the circuit elements can be applied stably and the wire bonding can also be applied stably and which can fit to the mass-production while saving the resource.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: March 16, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20040038471
    Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.
    Type: Application
    Filed: June 12, 2003
    Publication date: February 26, 2004
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi, Takeshi Nakamura
  • Publication number: 20040006869
    Abstract: The invention is to form plated films on a conductive foil a thigh precision, and simplify a procedure of forming the plated film. A resin film composed of a thermosetting resin is formed on the surface of the conductive foil. The resin film of parts which become bonding pads and die pads is eliminated by a laser etching. A clamper presses of the periphery of the block so as to form hermetically sealed spaces on the block. The interior of the clamper is filled with a plating liquid by means of an injection means and an evacuation means, and subsequently, and Ag plated film is formed by an electroplating method.
    Type: Application
    Filed: July 10, 2003
    Publication date: January 15, 2004
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Takeshi Nakamura, Yoshiyuki Kobayashi
  • Patent number: 6664138
    Abstract: A method for fabricating a circuit device is provided. An insulation resin sheet having the first conductive layer 3 and the second conductive layer 4 adhered to each other by insulation resin 2 is used, the first conductive path layer 5 is formed by the first conductive layer 3, and semiconductor elements 7 are adhered to and fixed on overcoating resin 8 that covers the first conductive path layer 5, thereby freely routing the first conductive path layer 5 having fine patterns below the semiconductor elements 7. Furthermore, the second conductive layer 4 that has been formed to be thick is removed after a package is sealed with a sealing resin layer 13, and external electrodes 14 are formed in through holes of the insulation resin 2.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: December 16, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Patent number: 6646331
    Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 11, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Patent number: 6635956
    Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: October 21, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Patent number: 6596564
    Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: July 22, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20030054659
    Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Therefore, a circuit device and a method for fabricating the same according to the invention solves the above-described and other problems by the structure, wherein an insulation resin sheet in which the first conductive layer 3 and the second conductive layer 4 are adhered to each other by insulation resin 2 is used, the first conductive path layer 5 is formed by the first conductive layer 3, the second conductive path layer 6 is formed by the second conductive layer 4, and both of the conductive path layers are connected by multi-layer connecting means 12.
    Type: Application
    Filed: June 14, 2002
    Publication date: March 20, 2003
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Patent number: 6531370
    Abstract: After mounting portions (65) are formed in each block (62), circuit elements are mounted on the mounting portions (65) and molded with insulating resin (50). Then, the back surface of conductive foil (60) is etched to form conductive patterns 51in each block. Further, a plurality of blocks are bonded onto a adhesive sheet so that a testing step and a dicing step are carried out upon the blocks in a lump.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: March 11, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20030011058
    Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).
    Type: Application
    Filed: September 9, 2002
    Publication date: January 16, 2003
    Applicant: Sanyo Electric Co., Ltd., a Japan corporation
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20030011065
    Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.
    Type: Application
    Filed: September 6, 2002
    Publication date: January 16, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Patent number: 6501162
    Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to the heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: December 31, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20020192875
    Abstract: A totally molded semiconductor apparatus in which a flexible sheet having conductive patterns are employed as a supporting substrate and semiconductor elements are assembled thereon has conventionally been developed. In this case, a problem occurs, by which warping of an insulation resin sheet becomes remarkable in the fabrication process. In order to solve such a problem, the invention discloses a method for fabricating a circuit device, wherein an insulation resin sheet having the first conductive layer 3 and the second conductive layer 4 adhered to each other by insulation resin 2 is used, the first conductive path layer 5 is formed by the first conductive layer 3, and semiconductor elements 7 are adhered to and fixed on overcoating resin 8 that covers the first conductive path layer 5, thereby freely routing the first conductive path layer 5 having fine patterns below the semiconductor elements 7.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 19, 2002
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Publication number: 20020190377
    Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Therefore, a circuit device and a method for fabricating the same according to the invention solves the above-described and other problems by the structure, wherein an insulation resin sheet in which the first conductive layer 3 and the second conductive layer 4 are adhered to each other by insulation resin 2 is used, the first conductive path layer 5 is formed by the first conductive layer 3, the second conductive path layer 6 is formed by the second conductive layer 4, and both of the conductive path layers are connected by multi-layer connecting means 12.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 19, 2002
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Publication number: 20020192858
    Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Since a conductive plated layer 4 is formed after through holes 21 are formed in the insulation resin 2 by using an insulation resin sheet 1 overcoated on a single side of the conductive layer 3 with insulation resin 2, a multi-layer connection structure can be achieved by the second conductive path layer 6 which is connected, in multi layers, to the first conductive path layer 5 formed by etching the conductive plated layer 4.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 19, 2002
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Publication number: 20020192857
    Abstract: An entirely molded semiconductor apparatus in which a flexible sheet having a conductive pattern is employed as a supporting substrate and semiconductor elements are assembled thereon has been developed, wherein such a semiconductor apparatus has various problems by which no multi-layered connection structure is enabled, and warping of insulation resin sheets becomes remarkable in the fabrication process. Since a conductive plated layer 4 is formed after through holes 21 are formed in the insulation resin 2 by using an insulation resin sheet 1 overcoated on a single side of the conductive layer 3 with insulation resin 2, a multi-layer connection structure can be achieved by the second conductive path layer 6 which is connected, in multi layers, to the first conductive path layer 5 formed by etching the conductive plated layer 4.
    Type: Application
    Filed: June 14, 2002
    Publication date: December 19, 2002
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kabayashi, Takeshi Nakamura
  • Patent number: 6462418
    Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: October 8, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20020133943
    Abstract: After conductive patterns are formed on the conductive foil every block by employing isolation trenches, conductive plating layers are arranged selectively on the conductive patterns. Therefore, it is possible to accomplish the circuit device manufacturing method by which the die bonding of the circuit elements can be applied stably and the wire bonding can also be applied stably and which can fit to the mass-production while saving the resource.
    Type: Application
    Filed: December 6, 2001
    Publication date: September 26, 2002
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20020053722
    Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).
    Type: Application
    Filed: March 16, 2001
    Publication date: May 9, 2002
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
  • Publication number: 20020052062
    Abstract: A conductive pattern of a first layer isolated by an isolation trench is formed on a conductive foil, and a plurality of layers of the conductive patterns are formed thereon to create a multilayered wiring structure, and furthermore, a circuit element is mounted and molded with an insulating resin and the back surface of the conductive foil is etched. It is possible to implement a method of manufacturing a circuit device which provides very power saving and is suitable for mass production, then the circuit device having conductive patterns of a multilayered structure are provided.
    Type: Application
    Filed: October 2, 2001
    Publication date: May 2, 2002
    Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi