Patents by Inventor Yusuke Igarashi

Yusuke Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7329957
    Abstract: A method of manufacturing a circuit device includes the steps of preparing a conductive foil, forming conductive patterns in convex shapes by forming an isolation trench on a surface of the conductive foil, covering the surface of the conductive foil with a resin film so as to form the resin film covering the isolation trench thicker than the resin film covering upper surfaces of the conductive patterns, exposing the upper surfaces of the conductive patterns out of the resin film by removing the resin film, electrically connecting the conductive pattern exposed out of the resin film to a circuit element, forming sealing resin to seal the circuit element, and removing a rear surface of the conductive foil until the conductive patterns are mutually isolated.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: February 12, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Jun Sakano, Kouji Takahashi, Yusuke Igarashi
  • Patent number: 7315083
    Abstract: A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing method thereof, a first conductive film is laminated on a first insulating layer, and a first wiring layer is formed by patterning the first conductive film. Next, a second conductive film is laminated on a second insulating layer. Thereafter, by partially removing the second insulating layer and the second conductive film in a desired spot, a connection part for connecting the wiring layers to each other is formed.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: January 1, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui
  • Patent number: 7301228
    Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: November 27, 2007
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Kojima, Noriaki Sakamoto
  • Publication number: 20070221704
    Abstract: A method of manufacturing a circuit device of the present invention comprises the steps of: forming a conductive pattern including a first pad and a second pad on the surface of a substrate; applying a solder paste to the surface of the first pad and then thermally melting the solder paste, thus forming solder; fixing a circuit element to the second pad; and fixing a circuit element to the first pad with the solder therebetween. Furthermore, a flux constituting the solder paste contains sulfur. Since the sulfur is mixed into the solder paste, surface tension of the solder paste is lowered; accordingly occurrence of sink is suppressed.
    Type: Application
    Filed: January 30, 2006
    Publication date: September 27, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Publication number: 20070205017
    Abstract: In a hybrid integrated circuit device that is a circuit device of the present invention, a conductive pattern including pads is formed on a surface of a substrate. A first pad is formed to be relatively large since a heat sink is mounted thereon. A second pad is a small pad to which a chip component or a small signal transistor is fixed. In the present invention, a plated film made of nickel is formed on a surface of the first pad. Therefore, the first pad and a solder never come into contact with each other. Thus, a Cu/Sn alloy layer having poor soldering properties is not generated but a Ni/Sn alloy layer having excellent soldering properties is generated. Consequently, occurrence of sink in the melted solder is suppressed.
    Type: Application
    Filed: January 30, 2006
    Publication date: September 6, 2007
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Sadamichi Takakusaki, Noriaki Sakamoto, Motoichi Nezu, Yusuke Igarashi
  • Patent number: 7221049
    Abstract: A circuit device having a multilayered wiring structure and an excellent heat dissipation property, and a method of manufacturing the circuit device are provided. In a circuit device, a multilayered wiring structure including a first conductive pattern and a second conductive pattern is formed on a surface of a circuit substrate. A first insulating layer is formed entirely on the surface of the circuit substrate. The first conductive pattern and the second conductive pattern are mutually insulated by a second insulating layer. An amount and grain sizes of filler included in the second insulating layer are smaller than an amount and grain sizes of filler included in the first insulating layer. Therefore, it is easier to connect the above two conductive patterns by way of penetrating the second insulating layer.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: May 22, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Hideki Mizuhara, Ryosuke Usui
  • Patent number: 7186921
    Abstract: A circuit device which enables formation of a minute pattern while securing a current capacity and has excellent heat release properties, and a manufacturing method thereof are provided. In a circuit device of the present invention, among multiple wiring layers, a first wiring layer is formed of a thin first conductive pattern and a thick second conductive pattern. Therefore, formation of the minute patterns is realized while securing the current capacity. Moreover, a small-signal circuit element is mounted on the first conductive pattern, and a large-current circuit element is mounted on the second conductive pattern. Thus, circuit elements having different sizes of currents to be handled are mounted on the same board. Furthermore, heat release properties are improved by the second conductive pattern which is formed to be thick.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: March 6, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Sadamichi Takakusaki
  • Patent number: 7163841
    Abstract: To provide a method of manufacturing a highly reliable circuit device realizing a smaller, thinner and lighter configuration. In the method of manufacturing a circuit device according to the invention, a resin sealed body is separated from a supporting substrate, after the resin sealed body containing a circuit device is formed on a top surface of the supporting substrate. Therefore, manufacture of a circuit device having no substrate becomes possible and it realizes a thinner and lighter circuit device with improved heat dissipation. Moreover, since sealing with a sealing resin can be performed on the supporting substrate, warps, caused by the differences in thermal expansion coefficients between the sealing resin and conductive patterns and between the sealing resin and circuit components, can be prevented.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: January 16, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Sadamichi Takakusaki, Yusuke Igarashi, Motoichi Nezu, Takaya Kusabe
  • Patent number: 7163846
    Abstract: In order to prevent, in a resin sealing step, a conductive foil 10 from locally rising because of concentration of air intervening between the conductive foil 10 and lower mold 28A due to the charged pressure, a method for manufacturing circuit devices is provided. The method for manufacturing circuit devices includes the step of forming conductive patterns 21, which form a plurality of mounting portions 15 of a circuit element 22 on a conductive foil 10, in each block 12, the step of disposing the circuit element 22 on each mounting portion 15 of the conductive pattern 21 in each block 12, the step of performing resin sealing by bringing the lower mold 28A having an air vent 30 into contact with the backface of the conductive foil 10 in each block 12 and by performing transfer molding with an insulating resin 20 while disposing each mounting portion 15 of the block 12 in the same cavity, and the step of separating each mounting portion 15 by dicing.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: January 16, 2007
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Noriyasu Sakai, Yusuke Igarashi, Masato Noguchi
  • Patent number: 7141509
    Abstract: A method for fabricating a circuit device includes preparing a laminating sheet comprising a conductive film, insulation resin formed on the surface of the conductive film, and a first conductive path layer formed on the surface of the insulation resin. Semiconductor elements are adhered and fixed on the first conductive path layer. A sealing resin is provided as an overcoat to the first conductive path layer and the semiconductor elements. The method includes forming a second conductive path layer by etching the conductive film into a predetermined pattern and forming an external electrode at predetermined points of the second conductive path layer.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: November 28, 2006
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
  • Patent number: 7105384
    Abstract: A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns 21 are removed using plasma to thereby improve the adhesion of conductive patterns 21 to a sealing resin 28. By selective etching of a conductive foil 10, separation grooves 11 are formed, thereby forming conductive patterns 21. A semiconductor element 22A and other circuit elements are mounted onto desired locations of conductive patterns 21 and electrically connected with conductive patterns 21. By irradiating plasma onto conductive foil 10 from above, contaminants attached to the surfaces of separation grooves 11 are removed.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: September 12, 2006
    Assignees: Sanyo Electric Co., Ltd, Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Patent number: 7045393
    Abstract: Conventionally, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate (10) in which a thin first conductive film (11) and a thick second conductive film (12) have been laminated via a third conductive film (13) is used. In a step for forming a conductive wiring layer (11A) by etching the first conductive film (11), etching depth can be controlled by stopping etching at the third conductive film (13). Accordingly, forming the first conductive film (11) to be thin makes it possible to form the conductive wiring layer (11A) into a fine pattern.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: May 16, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Noriaki Sakamoto
  • Patent number: 7030033
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: April 18, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Publication number: 20060065421
    Abstract: Warping of a hybrid integrated circuit device 10 due to shrinkage on curing of a sealing resin 14 is suppressed. The hybrid integrated circuit device 10 includes: a conductive pattern 13 provided on a surface of a circuit board 11; circuit elements 15 fixed to the conductive pattern 13; thin metal wires 17 electrically connecting the circuit elements 15 to the conductive pattern; leads 16 which are connected to the conductive pattern 13 to become output or input and extended to the outside; and a sealing resin 14 which is made of a thermosetting resin and covers the circuit board 11 by transfer molding while at least a rear surface of the circuit board is exposed. Here, a thermal expansion coefficient of the sealing resin 14 is set to be smaller than a thermal expansion coefficient of the circuit board 11. Thus, warping of the circuit board 11 in an after cure step can be prevented.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 30, 2006
    Applicants: SANYO ELECTRIC CO., LTD., Kanto SANYO Semiconductors Co., Ltd.
    Inventors: Kazumasa Arai, Yutaka Kubota, Yusuke Igarashi, Hidefumi Saito, Masami Motegi, Noriaki Sakamoto
  • Publication number: 20060032049
    Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.
    Type: Application
    Filed: August 19, 2005
    Publication date: February 16, 2006
    Applicant: Sanyo Electric Co. Ltd.
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20060024862
    Abstract: To provide a method of manufacturing a highly reliable circuit device realizing a smaller, thinner and lighter configuration. In the method of manufacturing a circuit device according to the invention, a resin sealed body is separated from a supporting substrate, after the resin sealed body containing a circuit device is formed on a top surface of the supporting substrate. Therefore, manufacture of a circuit device having no substrate becomes possible and it realizes a thinner and lighter circuit device with improved heat dissipation. Moreover, since sealing with a sealing resin can be performed on the supporting substrate, warps, caused by the differences in thermal expansion coefficients between the sealing resin and conductive patterns and between the sealing resin and circuit components, can be prevented.
    Type: Application
    Filed: July 11, 2005
    Publication date: February 2, 2006
    Inventors: Sadamichi Takakusaki, Yusuke Igarashi, Motoichi Nezu, Takaya Kusabe
  • Patent number: 6989291
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a first conductive film 11 and a second conductive film 12 have been laminated via a third conductive film 13 is used. After forming a conductive pattern layer 11A by etching the first conductive film 11, anchor portions 15 are formed by overetching the third conductive film 13 by use of the conductive pattern layer 11A as a mask, and a sealing resin layer 22 is made to bite into the anchor portions 15 so as to strengthen bonding of the sealing resin layer 22 with the conductive pattern layer 11A.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: January 24, 2006
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductor Co., Ltd.
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Publication number: 20060012028
    Abstract: A device mounting board on which a device is mounted is provided with a substrate and an insulating film provided on one surface of the substrate. The substrate and the insulating film include glass fiber impregnated with epoxy resin. The epoxy resin impregnation ratio of the glass fiber included in the insulating resin film is higher than that of the glass fiber included in the substrate.
    Type: Application
    Filed: June 7, 2005
    Publication date: January 19, 2006
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Yusuke Igarashi, Takeshi Nakamura
  • Publication number: 20060001166
    Abstract: A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.
    Type: Application
    Filed: June 24, 2005
    Publication date: January 5, 2006
    Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Ryosuke Usui, Hideki Mizuhara
  • Publication number: 20050272252
    Abstract: Provided is a circuit device capable of inhibiting an insulating layer from separating from a substrate. This circuit device comprises a substrate mainly constituted of metal including a first metal layer having a first thermal expansion coefficient, a second metal layer, formed on the first metal layer, having a second thermal expansion coefficient different from the first thermal expansion coefficient of the first metal layer and a third metal layer, formed on the second metal layer, having a third thermal expansion coefficient different from the second thermal expansion coefficient of the second metal layer, an insulating layer formed on the substrate, a conductive layer formed on the insulating layer and a circuit element electrically connected to the conductive layer.
    Type: Application
    Filed: May 27, 2005
    Publication date: December 8, 2005
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue, Yusuke Igarashi, Takeshi Nakamura