Patents by Inventor Yusuke Igarashi
Yusuke Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6972477Abstract: To make thin a circuit device 10 in which are incorporated a plurality of types of circuit elements 12 that differ in thickness, first conductive patterns, onto which comparatively thin circuit elements 12A are mounted, are formed thickly, and second conductive patterns 11B, onto which comparatively thick second circuit elements 12B are mounted, are formed thinly. Also, fine wiring parts may be formed using the thinly formed second conductive patterns 12B. Thus even in the case where thick circuit elements are incorporated, by affixing such circuit elements onto the thinly formed second conductive patterns 11B, the total thickness can be made thin. Thinning of circuit device 10 as a whole can thus be accomplished.Type: GrantFiled: December 11, 2003Date of Patent: December 6, 2005Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
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Publication number: 20050263320Abstract: A circuit device which enables formation of a minute pattern while securing a current capacity and has excellent heat release properties, and a manufacturing method thereof are provided. In a circuit device of the present invention, among multiple wiring layers, a first wiring layer is formed of a thin first conductive pattern and a thick second conductive pattern. Therefore, formation of the minute patterns is realized while securing the current capacity. Moreover, a small-signal circuit element is mounted on the first conductive pattern, and a large-current circuit element is mounted on the second conductive pattern. Thus, circuit elements having different sizes of currents to be handled are mounted on the same board. Furthermore, heat release properties are improved by the second conductive pattern which is formed to be thick.Type: ApplicationFiled: May 31, 2005Publication date: December 1, 2005Inventors: Yusuke Igarashi, Sadamichi Takakusaki
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Publication number: 20050263880Abstract: A circuit device having a multilayered wiring structure and an excellent heat dissipation property, and a method of manufacturing the circuit device are provided. In a circuit device, a multilayered wiring structure including a first conductive pattern and a second conductive pattern is formed on a surface of a circuit substrate. A first insulating layer is formed entirely on the surface of the circuit substrate. The first conductive pattern and the second conductive pattern are mutually insulated by a second insulating layer. An amount and grain sizes of filler included in the second insulating layer are smaller than an amount and grain sizes of filler included in the first insulating layer. Therefore, it is easier to connect the above two conductive patterns by way of penetrating the second insulating layer.Type: ApplicationFiled: May 27, 2005Publication date: December 1, 2005Inventors: Yusuke Igarashi, Sadamichi Takakusaki, Hideki Mizuhara, Ryosuke Usui
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Publication number: 20050263905Abstract: A method for manufacturing a circuit device, which is suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, is provided. In a method for manufacturing a hybrid integrated circuit device of the present invention, a first wring layer is formed by laminating a first conductive film on a first insulating layer, and patterning the first conductive film. In the first wiring layer, a first connection part which is protruded in a thickness direction is formed. Moreover, the first wiring layer including the first connection part is covered with a second insulating layer. The second insulating layer is formed of a first resin film and a second resin film. The second resin film contains fewer inorganic fillers than the first resin film. Thus, there is an advantage that a through-hole can be easily formed.Type: ApplicationFiled: May 25, 2005Publication date: December 1, 2005Inventors: Ryosuke Usul, Hideki Mizuhara, Yusuke Igarashi, Nobuhisa Takakusaki, Hayato Abe, Takeshi Nakamura
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Publication number: 20050263911Abstract: A circuit device suitable for connecting a plurality of laminated wiring layers to each other through an insulating layer, and a manufacturing method thereof are provided. According to a hybrid integrated circuit device of the present invention and a manufacturing method thereof, a first conductive film is laminated on a first insulating layer, and a first wiring layer is formed by patterning the first conductive film. Next, a second conductive film is laminated on a second insulating layer. Thereafter, by partially removing the second insulating layer and the second conductive film in a desired spot, a connection part for connecting the wiring layers to each other is formed.Type: ApplicationFiled: May 31, 2005Publication date: December 1, 2005Inventors: Yusuke Igarashi, Takeshi Nakamura, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui
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Patent number: 6967401Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: GrantFiled: March 16, 2001Date of Patent: November 22, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Patent number: 6963126Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.Type: GrantFiled: March 16, 2001Date of Patent: November 8, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Patent number: 6953712Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, are formed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.Type: GrantFiled: December 1, 2003Date of Patent: October 11, 2005Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
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Publication number: 20050214981Abstract: A method of manufacturing a circuit device includes the steps of preparing a conductive foil, forming conductive patterns in convex shapes by forming an isolation trench on a surface of the conductive foil, covering the surface of the conductive foil with a resin film so as to form the resin film covering the isolation trench thicker than the resin film covering upper surfaces of the conductive patterns, exposing the upper surfaces of the conductive patterns out of the resin film by removing the resin film, electrically connecting the conductive pattern exposed out of the resin film to a circuit element, forming sealing resin to seal the circuit element, and removing a rear surface of the conductive foil until the conductive patterns are mutually isolated.Type: ApplicationFiled: March 21, 2005Publication date: September 29, 2005Inventors: Jun Sakano, Kouji Takahashi, Yusuke Igarashi
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Patent number: 6949470Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.Type: GrantFiled: September 17, 2003Date of Patent: September 27, 2005Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
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Publication number: 20050206014Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.Type: ApplicationFiled: April 29, 2005Publication date: September 22, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi, Takeshi Nakamura
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Patent number: 6946724Abstract: A circuit device 10 comprises conductive patterns 11, separated by separation grooves 41, circuit elements 12, affixed onto conductive patterns 11, and an insulating resin 13, covering circuit elements 12 and conductive patterns 11 and filling separation grooves 41 while exposing the rear surfaces of conductive patterns 11. Constricted parts 19 are formed at side surfaces of separation grooves 41. At constricted parts 19, the width of separation grooves 41 is made narrower than at other locations. Thus by making insulating resin 13 adhere closely to constricted parts 19, the adhesion of insulating resin 13 with conductive patterns 11 is improved.Type: GrantFiled: December 11, 2003Date of Patent: September 20, 2005Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Nobuhisa Takakusaki, Jun Sakano, Noriaki Sakamoto
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Patent number: 6936927Abstract: A circuit device and a method for fabrication the same is provided. An insulation resin sheet in which the first conductive layer 3 and the second conductive layer 4 are adhered to each other by insulation resin 2 is used. The first conductive path layer 5 is formed by the first conductive layer 3, the second conductive path layer 6 is formed by the second conductive layer 4, and both of the conductive path layers are connected by multi-layer connecting means 12. Since a semiconductor element 7 is adhered to and fixed on overcoating resin 8 that covers the first conductive path layer 5, a multi-layer connection structure can be achieved by the first conductive path layer 5 and the second conductive path layer 6. Further, the second conductive layer 4 that is made thick can prevent warping from occurring due to a difference in a thermal expansion coefficient.Type: GrantFiled: June 14, 2002Date of Patent: August 30, 2005Assignee: Sanyo Electric Co., LTD.Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
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Patent number: 6933604Abstract: The back surface of a semiconductor chip (16) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this semiconductor chip (16). The back surface of this metal plate (23) and the back surface of a first supporting member (11) are substantially within a same plane, so that it is readily affixed to a second supporting member (24). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the metal plate (23) and the second supporting member (24).Type: GrantFiled: March 16, 2001Date of Patent: August 23, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Patent number: 6909178Abstract: As conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.Type: GrantFiled: June 12, 2003Date of Patent: June 21, 2005Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi, Takeshi Nakamura
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Publication number: 20050116322Abstract: A circuit module of the present invention has leads serving as terminals for performing electrical input from, and output to exterior, a circuit device in which a first circuit element electrically connected to at least one of the leads is sealed with first sealing resin, a second circuit element fixed to an island formed in one of the leads, and second sealing resin for sealing the circuit device and the second circuit element. Here, the circuit device has a conductive pattern with an interval smaller than that between the leads.Type: ApplicationFiled: July 28, 2004Publication date: June 2, 2005Inventors: Fumio Sando, Yusuke Igarashi, Noriaki Sakamoto
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Patent number: 6894375Abstract: A heat radiation electrode (15) is exposed from the back surface of an insulating resin (13), and a metal plate (23) is affixed to this heat radiation electrode (15). The back surface of this metal plate (23) and the back surface of a flexible sheet become substantially within a same plane, so that it is readily affixed to a second supporting member (24). In addition, the top surface of the heat radiation electrode (15) is made protrusive beyond the top surfaces of the pads (14) to reduce the distance between the semiconductor chip (16) and the heat radiation electrode (15). Accordingly, the heat generated by the semiconductor chip can be efficiently dissipated via the heat radiation electrode (15), the metal plate (23) and the second supporting member (24).Type: GrantFiled: August 29, 2003Date of Patent: May 17, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi
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Patent number: 6889428Abstract: The invention is to form plated films on a conductive foil a thigh precision, and simplify a procedure of forming the plated film. A resin film composed of a thermosetting resin is formed on the surface of the conductive foil. The resin film of parts which become bonding pads and die pads is eliminated by a laser etching. A clamper presses of the periphery of the block so as to form hermetically sealed spaces on the block. The interior of the clamper is filled with a plating liquid by means of an injection means and an evacuation means, and subsequently, and Ag plated film is formed by an electroplating method.Type: GrantFiled: July 10, 2003Date of Patent: May 10, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Yusuke Igarashi, Noriaki Sakamoto, Takeshi Nakamura, Yoshiyuki Kobayashi
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Patent number: 6883231Abstract: A method for fabricating a circuit device includes preparing an insulation resin sheet for which a first conductive layer and a second conductive layer are adhered to each other by insulation resin, forming through holes in the first conductive layer and the insulation resin at appointed points of the insulation resin sheet, and selectively exposing the rear side of the second conductive layer. A multi-layer connecting means is formed in the through holes and the first conductive layer is electrically connected to the second conductive layer. The method includes etching the first conductive layer to an appointed pattern, forming a first conductive path layer, and adhering and fixing semiconductor elements by electrically insulating the same on the first conductive path layer. The first conductive path layer and the semiconductor elements are overcoated with a sealing resin layer.Type: GrantFiled: June 14, 2002Date of Patent: April 26, 2005Assignee: Sanyo Electric Co. Ltd.Inventors: Yusuke Igarashi, Noriaki Sakamoto, Yoshiyuki Kobayashi, Takeshi Nakamura
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Patent number: 6864121Abstract: A conductive pattern of a first layer isolated by an isolation trench is formed on a conductive foil, and a plurality of layers of the conductive patterns are formed thereon to create a multilayered wiring structure, and furthermore, a circuit element is mounted and molded with an insulating resin and the back surface of the conductive foil is etched. It is possible to implement a method of manufacturing a circuit device which provides very power saving and is suitable for mass production, then the circuit device having conductive patterns of a multilayered structure are provided.Type: GrantFiled: October 2, 2001Date of Patent: March 8, 2005Assignee: Sanyo Electric Co., Ltd.Inventors: Noriaki Sakamoto, Yoshiyuki Kobayashi, Junji Sakamoto, Yukio Okada, Yusuke Igarashi, Eiju Maehara, Kouji Takahashi