Three dimensional memory device having well contact pillar and method of making thereof
A monolithic three dimensional memory device includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.
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The present disclosure relates generally to the field of semiconductor devices and specifically to three dimensional memory devices, such as vertical NAND strings, and other three dimensional devices and methods of making thereof.
BACKGROUNDThree dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh, et. al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36.
SUMMARYAn embodiment relates to a monolithic three dimensional memory device that includes a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate, a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate, and a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member including an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region.
Another embodiment relates to a method of making a monolithic three dimensional memory device that includes forming a stack of alternating layers of a first material and a second material different than the first material over a major surface of a substrate, etching the stack to form a plurality of memory openings and at least one support pillar opening in the stack, forming a plurality of NAND memory strings in the plurality of memory openings, and forming a support pillar in the support pillar opening, where the support pillar includes an electrically insulating material located over a sidewall of the support pillar opening and an electrically conductive material that is surrounded by the electrically insulating material.
Embodiments of the present disclosure will be described below with reference to the accompanying drawings. It should be understood that the following description is intended to describe various embodiments of the disclosure, and not to limit the disclosure.
The embodiments of the disclosure may provide a monolithic, three dimensional array of memory devices, such as an array of vertical NAND strings. The NAND strings may be vertically oriented, such that at least one memory cell is located over another memory cell. The array may allow vertical scaling of NAND devices to provide a higher density of memory cells per unit area of silicon or other semiconductor material.
A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no intervening substrates. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, titled “Three Dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
As shown in
Each of the active memory cell areas 201 may contain a plurality of vertical NAND strings 150 according to one embodiment of the disclosure. Each NAND string may comprise a substantially pillar-shaped structure extending substantially perpendicular to the major surface 100a of the substrate 100 and may include a plurality memory device levels, as shown in
In embodiments, the peripheral regions 300 may include word line connection regions 302 containing a plurality of word line contacts 303 which contact respective stepped portions of the plurality of electrically conductive word lines 3, as shown in
In embodiments, the substrate 100 may have a doped well region 105 of a first conductivity type extending substantially parallel to the major surface 100a of the semiconductor substrate 100, as shown in
A source region 113 may be located at the bottom of each of the slit trenches 84a, 84b and may be in electrical contact with a respective source line 202a, 202b. The source regions 113 may comprise regions of the substrate 100 having an opposite conductivity type than the conductivity type of the doped well region 105 (e.g., the source region 113 may be n-type when the doped well region 105 is a p-well region). In embodiments, the source region 113 may be formed by implanting the substrate 100 through the trench 84 (e.g., via ion implantation) to provide the source region 113 of the substrate 100 having a second conductivity type opposite the first conductivity type of the doped well region 105 of the substrate 100. The source line 202 may then be formed in the trench 84 in electrical contact with the source region 113.
In embodiments, each of the source lines 202 (e.g., source side electrodes) may be electrically coupled via the source region 113 to the semiconductor channel 1 of the NAND strings 150 via a semiconductor channel portion 115 that extends substantially parallel to the major surface 100a of the substrate 100 (e.g., within the doped well region 105) and contacts the semiconductor channel 1 from below the device levels 70, as shown in
The memory device 101 may also include drain electrodes 103 which contact the semiconductor channel 1 of the NAND strings 150 via a drain region 116 from above the device levels 70, as shown in
In embodiments, it may be desirable to form electrical contacts to the doped well region 105 (e.g., p-well region) of the substrate 100 in the memory device 101. The electrical contacts may be used to selectively electrically bias the well region 105 (e.g., biased at a positive voltage, e.g., 15-25V, during an erase operation of the NAND cells) in order to increase the potential in the semiconductor channel portions 115, 1 of the memory device 101. At other times, the doped well region may be biased at zero volts. The present inventors realized that it may be challenging to form electrical contacts to the doped well region 105 without taking up an unreasonably large area of the device 101 and/or otherwise interfering with the operation of the memory device 101 (e.g., by increasing noise in the device).
Various embodiments include providing a plurality of substantially pillar-shaped support members 107 extending substantially perpendicular to the major surface 100a of the substrate 100. Each of the support members 107 may include an electrically insulating outer material 109 which surrounds an electrically conductive core material 111. The electrically insulating outer material 109 may comprise any suitable insulating material (e.g., an oxide or nitride material, such as silicon oxide, silicon nitride or silicon oxynitride). The core material 111 may comprise any suitable electrically conductive material, such as a metal material (e.g., a metal or metal alloy, including a metal nitride or metal silicide) or a doped semiconductor material. The conductive core material 111 may extend generally perpendicular to the major surface 100a of the substrate 100 and may electrically contact the doped well region 105, as shown in
As shown in
In some embodiments, at least one substantially pillar-shaped support member 107 may be located within an active memory cell area 201 of the device region 200, as shown in
In other embodiments, at least one substantially pillar-shaped support member 107 may be located within a word line connection region 302 in the peripheral region 300 of the device 101, as shown in
Referring to
As shown in
In some embodiments, the monolithic three dimensional NAND string 150 comprises a semiconductor channel 1 having at least one end portion extending substantially perpendicular to a major surface 100a of a substrate 100, as shown in
In some embodiments, the semiconductor channel 1 may be a filled feature, as shown in
A memory device 101 may comprise a plurality of NAND strings 150 formed in a stack 120 of material layers over the substrate 100. The substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon, IV-IV compounds such as silicon-germanium or silicon-germanium-carbon, III-V compounds, II-VI compounds, epitaxial layers over such substrates, or any other semiconducting or non-semiconducting material, such as silicon oxide, glass, plastic, metal or ceramic substrate. The substrate 100 may include integrated circuits fabricated thereon, such as driver circuits for a memory device.
Any suitable semiconductor materials can be used for semiconductor channel 1, for example silicon, germanium, silicon germanium, or other compound semiconductor materials, such as III-V, II-VI, or conductive or semiconductive oxides, etc. The semiconductor material may be amorphous, polycrystalline or single crystal. The semiconductor channel material may be formed by any suitable deposition methods. For example, in one embodiment, the semiconductor channel material is deposited by low pressure chemical vapor deposition (LPCVD). In some other embodiments, the semiconductor channel material may be a recrystallized polycrystalline semiconductor material formed by recrystallizing an initially deposited amorphous semiconductor material.
The insulating fill material 2 may comprise any electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating materials.
The monolithic three dimensional NAND string further comprise a plurality of control gate electrodes 3, which may be continuous with the word lines 3 shown in
A blocking dielectric 7 may be located adjacent to the control gate(s) 3. For example, a straight blocking dielectric layer 7 may be located only adjacent to an edge (i.e., minor surface) of each control gate 3, as shown in
The monolithic three dimensional NAND string may also comprise a charge storage region 9. The charge storage region 9 may comprise one or more continuous layers which extend the entire length of the memory cell portion of the NAND string, as shown in
The tunnel dielectric 11 of the monolithic three dimensional NAND string is located between charge storage region 9 and the semiconductor channel 1.
The blocking dielectric 7 and the tunnel dielectric 11 may be independently selected from any one or more same or different electrically insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials, such as metal oxide materials, for example aluminum oxide or hafnium oxide. The blocking dielectric 7 and/or the tunnel dielectric 11 may include multiple layers of silicon oxide, silicon nitride and/or silicon oxynitride (e.g., ONO layers).
Various embodiments relate to methods of making a memory device that include a support member 107 having an electrically conductive material 111 surrounded by an electrically insulating material 109, such as the device 101 described above with reference to
Referring to
In one embodiment, the first material layers 19 comprise an electrically insulating material, such as an oxide (e.g., silicon oxide, silicon oxynitride, a high-k dielectric, etc.). The second material layers 121 may comprise a sacrificial material, such as an insulating material that is different from the material of the first layers 19. For example, layers 19 may comprise silicon oxide (e.g., formed using a tetraethyl orthosilicate (TEOS) source) and layers 121 may comprise silicon nitride forming an ONON stack 120. Alternatively, layers 19 may comprise silicon oxide and layers 121 may comprise polysilicon forming an OPOP stack 120.
As shown in
The formation of layers 19, 121 may be followed by etching the stack 120 to form at least one memory opening 81 and at least one support pillar opening 501 in the stack 120. The at least one memory opening 81 and the at least one support pillar opening 501 may be formed by photolithography and etching as follows. First, a mask 503 may be formed over the stack 120 and patterned to form at least one first opening 505 corresponding to a future location of a memory opening 81 and at least one second opening 507 corresponding to the future location of a support pillar opening 501, as shown in
The memory opening 81 may include a sidewall 701 defined by the exposed surfaces of the layers 19, 121 of the stack 120 and a bottom surface 703, which in this embodiment is defined by the exposed surface of the substrate 100. The support pillar opening 501 may also include a sidewall 705 defined by the exposed surfaces of the layers 19, 121 of the stack 120 and a bottom surface 707, which may be defined by the exposed surface (e.g., doped well region 105) of the substrate 100.
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An optional implantation process to implant the same conductivity type dopants as that of the well region 105 (e.g., a p+ implantation) may be performed through the support pillar opening 501 to provide a lower contact resistance region (e.g., a heavily doped p+ region) within the doped well region 105. The memory opening 81 may be covered by a mask during this implantation step.
The etching may recess the cap layer 1701 above the memory opening 81 as shown in
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In some embodiments, a blocking dielectric 7 (see
Another embodiment method of making a memory device having a support member 107 is shown in
In
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The method may then continue as described above with reference to
Another embodiment method of making a memory device having a support member 107 is shown in
In this embodiment, the semiconductor cap layer 1701 and the channel layer 1401 may form the conductive core material 111 of the support member 107. This embodiment may be used, for example, when the semiconductor material of layers 1701 and 1401 has a low enough resistance to provide adequate electrical contact with the doped well region 105 of the substrate 100.
Although the foregoing refers to particular embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.
Claims
1. A monolithic three dimensional memory device, comprising:
- a semiconductor substrate having a major surface and a doped well region of a first conductivity type extending substantially parallel to the major surface of the semiconductor substrate;
- a plurality of NAND memory strings extending substantially perpendicular to the major surface of the semiconductor substrate; and
- a plurality of substantially pillar-shaped support members extending substantially perpendicular to the major surface of the semiconductor substrate, each support member comprising an electrically insulating outer material surrounding an electrically conductive core material that extends substantially perpendicular to the major surface of the semiconductor substrate and electrically contacting the doped well region,
- wherein each of the plurality of NAND memory strings comprises a substantially pillar-shaped structure extending substantially perpendicular to the major surface of the semiconductor substrate, and each of the plurality of substantially-pillar shaped support members has a width that is greater than a width of the substantially pillar shaped NAND strings.
2. The monolithic three dimensional memory device of claim 1, further comprising:
- a plurality of electrically conductive word lines extending substantially parallel to the major surface of the semiconductor substrate and adjacent to the support members, wherein the word lines comprise or are electrically continuous with a plurality of control gate electrodes of the NAND memory strings, the plurality of control gate electrodes comprising at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level.
3. The monolithic three dimensional memory device of claim 2, wherein each of the NAND memory strings comprises:
- a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to the major surface of the semiconductor substrate;
- at least one charge storage region located adjacent to at least the first side surfaces of each of the control gate electrodes;
- a blocking dielectric located adjacent to at least the first side surfaces of each of the control gate electrodes and located between the at least one charge storage region and each of the control gate electrodes; and
- a tunnel dielectric located between the at least one charge storage region and the semiconductor channel.
4. The monolithic three dimensional memory device of claim 3, wherein the plurality of NAND strings and at least one support member are located in an active memory cell area of the memory device, wherein the active memory cell area is located between a pair of electrically conductive source lines extending in a first direction substantially parallel the major surface of the semiconductor substrate.
5. The monolithic three dimensional memory device of claim 4, wherein:
- the doped well region comprises a p-well region; and
- each of the source lines comprises a source electrode that is electrically coupled via a source region to the semiconductor channel of at least one NAND string by a semiconductor channel portion that extends substantially parallel to the major surface of the semiconductor substrate and contacts the semiconductor channel from below the device levels.
6. The monolithic three dimensional memory device of claim 5, further comprising at least one drain electrode which contacts the semiconductor channel via a drain region from above the device levels, and at least one bit line which extends substantially perpendicular to the source electrode and which electrically contacts the at least one drain electrode.
7. The monolithic three dimensional memory device of claim 4, further comprising:
- at least one electrically conductive shunt line extending in a second direction substantially parallel to the major surface of the semiconductor substrate and to the at least one bit line, wherein the second direction is substantially perpendicular to the first direction of the source electrode, and wherein the electrically conductive core of each of the plurality of support members electrically contacts the doped well region at a first end of the core and is electrically coupled to a shunt line at a second end of the core opposite the first end.
8. The monolithic three dimensional memory device of claim 7, wherein at least one support member is located between first and second sets of one or more NAND strings within the active memory cell area and the at least one support member extends through a plurality of vertically separated word line fingers under the at least one electrically conductive shunt line.
9. The monolithic three dimensional memory device of claim 8, wherein at least one additional support member is further located in a word line connection region containing a plurality of word line contacts which contact respective stepped portions of the plurality of electrically conductive word lines.
10. The monolithic three dimensional memory device of claim 2, wherein at least one support member is located in a word line connection region containing a plurality of word line contacts which contact respective stepped portions of the plurality of electrically conductive word lines.
11. The monolithic three dimensional memory device of claim 1, wherein:
- the substrate comprises a silicon substrate;
- the plurality of NAND strings comprise a monolithic, three dimensional array of NAND strings;
- at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
- the silicon substrate contains located thereon an integrated circuit comprising a driver circuit for the array of NAND strings.
12. A method of making a monolithic three dimensional memory device, comprising:
- forming a stack of alternating layers of a first material and a second material different than the first material over a major surface of a substrate;
- etching the stack to form a plurality of memory openings and at least one support pillar opening in the stack;
- forming a plurality of NAND memory strings in the plurality of memory openings; and
- forming a support pillar in the support pillar opening, wherein the support pillar comprises an electrically insulating material located over a sidewall of the support pillar opening and an electrically conductive material that is surrounded by the electrically insulating material,
- wherein the substrate comprises a semiconductor substrate having a doped well region of a first conductivity type extending substantially parallel to the major surface of the substrate, and wherein etching the stack to form the at least one support pillar opening comprises exposing the doped well region of the substrate through the stack, and forming the support pillar comprises forming the electrically conductive material of the support pillar in electrical contact with the doped well region, and
- wherein the memory openings are formed with a first width and the at least one support pillar opening is formed with a second width that is larger than the first width.
13. The method of claim 12, wherein the doped well region comprises a p-well region.
14. The method of claim 12, wherein forming the plurality of NAND strings and forming the support pillar comprises:
- forming a first insulating material layer over a top surface of the stack, over the sidewalls and bottom surfaces of each of the memory openings and over the sidewall and bottom surface of the at least one support pillar opening;
- forming a charge storage material layer over the first insulating material over the top surface the stack, over the sidewalls and bottom surfaces of each of the memory openings and over the sidewall and bottom surface of the at least one support pillar opening;
- forming a tunnel dielectric layer over the charge storage material layer over the top surface of the stack, over the sidewalls and bottom surfaces of each of the memory openings and over the sidewall and bottom surface of the at least one support pillar opening;
- forming a mask over the tunnel dielectric layer over the top surface of the stack; and
- etching through a mask to remove the first insulating material layer, the charge storage material layer and the tunnel dielectric layer from the bottom surfaces of the memory openings and from the bottom surface of the at least one support pillar opening to expose the doped well region of the substrate at the bottom of the at least one support pillar opening.
15. The method of claim 14, further comprising:
- prior to forming the mask, forming a first semiconductor material layer over the tunnel dielectric layer over the top surface of the stack, over the sidewalls and bottom surfaces of each of the memory openings and over the sidewall and bottom surface of the at least one support pillar opening, wherein a first portion of the first semiconductor material layer over the bottom surfaces of the memory openings and the bottom surface at least one support pillar opening is removed during the etching, and a second portion of the first semiconductor material layer over the sidewalls of the memory openings and over the sidewall of the at least one support pillar opening protects the tunnel dielectric layer, the charge storage material layer and the first insulating material layer over the sidewalls of the memory openings and the sidewall of the at least one support pillar opening against etching damage during the etching.
16. The method of claim 15, further comprising:
- removing the mask from over the top surface of the stack; and
- forming a second semiconductor material layer over the first semiconductor layer over the top surface of the stack, over the sidewalls of each of the memory openings and over the sidewall of the at least one support pillar opening, and over the bottom surface of the memory openings and over the exposed doped well region of the substrate over the bottom of the at least one support pillar opening.
17. The method of claim 16, further comprising:
- forming a core insulator layer over the second semiconductor material layer over the top surface of the stack, over the sidewalls and bottom surface of each of the memory openings and over the sidewall and bottom surface of the at least one support pillar opening, wherein the core insulator layer completely fills each of the plurality of memory openings and does not completely fill the at least one support pillar opening.
18. The method of claim 17, further comprising:
- etching the stack using an isotropic etching process to substantially completely remove the core insulator layer from over the top surface of the stack, the at least one support pillar opening and an upper portion of each of the memory openings, wherein the core insulator layer is not removed from a lower portion of each of the memory openings.
19. The method of claim 18, further comprising:
- forming a third semiconductor material layer over the second semiconductor material layer over the top surface of the stack and within the memory openings and the at least one support pillar opening, wherein the third semiconductor material completely fills the upper portion of each of the memory openings and is located over at least the sidewall and the bottom surface of the support pillar opening.
20. The method of claim 19, further comprising:
- etching the stack using an isotropic etching process to substantially completely remove the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer from over the top surface of the stack and from the sidewall and bottom surface of the support pillar opening, wherein the first semiconductor material layer, the second semiconductor material layer and the third semiconductor material layer are not removed from the plurality of memory openings.
21. The method of claim 20, further comprising:
- etching the stack using an anisotropic etching process to remove the tunnel dielectric layer, the charge storage material layer and the first insulating material layer from over the top surface of the stack, wherein the tunnel dielectric layer, the charge storage material layer and the first insulating material layer are not removed from the sidewalls of the memory openings and the sidewall of the support pillar opening.
22. The method of claim 21, further comprising:
- forming an electrically conductive material over the top surface of the stack and filling the support pillar opening such that the electrically conductive material electrically contacts the doped well region of the substrate at the bottom surface of the support pillar opening and the tunnel dielectric layer, the charge storage material layer and the first insulating material layer surround the electrically conductive material along the sidewall of the support pillar opening; and
- removing the electrically conductive material from over the top surface of the stack.
23. The method of claim 22, wherein the electrically conductive material comprises doped polysilicon, metal or metal alloy.
24. The method of claim 22, further comprising:
- forming a second insulating material layer over the top surface of the stack and over the sidewall and bottom surface of the at least one support pillar opening;
- etching the stack using an anisotropic etching process to remove the second insulating material from over the top surface of the stack and from over the bottom surface of the at least one support pillar opening, wherein at least a portion of the second insulating material layer is not removed from over the sidewall of the at least one support pillar opening, and the electrically conductive material is formed within the support pillar opening such that the second insulating material surrounds the electrically conductive material along the sidewall of the support pillar opening.
25. The method of claim 19, wherein the third semiconductor material layer comprises an electrically conductive material that fills the support pillar opening such that the electrically conductive material of the third semiconductor layer electrically contacts the doped well region of the substrate at the bottom surface of the support pillar opening and the tunnel dielectric layer, the charge storage material layer and the first insulating material layer surround the electrically conductive material of the third semiconductor material along the sidewall of the support pillar opening.
26. The method of claim 12, wherein the first material in the stack comprises an insulating material and the second material in the stack comprises a sacrificial material, and the method further comprises:
- etching through the stack to form at least one back side opening in the stack;
- removing by etching at least a portion of the sacrificial material layers through the back side opening to form back side recesses between the first material layers, wherein the at least one support pillar provides mechanical support for the vertically separated first material layers of the stack; and
- forming control gates for the NAND strings in the back side recesses through the at least one back side opening.
27. The method of claim 26, further comprising forming a blocking dielectric comprising at least one layer in the back side recesses through the at least one back side opening prior to forming the control gates.
28. The method of claim 27, wherein:
- the blocking dielectric comprises a first silicon oxide layer and a second metal oxide layer;
- the at least one back side opening comprises an elongated trench extending through the stack to the substrate; and
- the first insulating material layer comprises a cover silicon oxide layer which is a different layer from the first silicon oxide layer and the second metal oxide layer of the blocking dielectric.
29. The method of claim 28, further comprising:
- forming a source region in the substrate at the bottom of the trench;
- forming an insulating material over the sidewalls of the trench; and
- forming an electrically conductive source line within the trench and electrically contacting the source region.
30. The method of claim 29, wherein forming the source region comprises implanting the substrate through the trench to provide a source region of the substrate having a second conductivity type opposite the first conductivity type of the doped well region of the substrate.
31. The method of claim 26, wherein the support pillar is located in a word line connection region containing a plurality of word line contacts which contact respective stepped portions of a plurality of electrically conductive word lines which comprise or are electrically continuous with the control gates.
32. The method of claim 12, further comprising forming a shunt line comprising an electrically conductive material located over the stack and extending substantially parallel to the major surface of the substrate, wherein:
- the shunt line is located over the support pillar;
- the shunt line is electrically coupled to the electrically conductive material in the support pillar; and
- the support pillar is located between first and second sets of one or more NAND strings within an active memory cell area.
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Type: Grant
Filed: Sep 19, 2014
Date of Patent: Jan 5, 2016
Assignee: SANDISK TECHNOLOGIES INC (Plano, TX)
Inventors: Seiji Shimabukuro (Yokkaichi), Ryoichi Honma (Yokkaichi), Hiroyuki Ogawa (Yokkaichi), Yuki Mizutani (San Jose, CA), Fumiaki Toyama (Cupertino, CA)
Primary Examiner: Ly D Pham
Application Number: 14/491,026
International Classification: G11C 16/04 (20060101); H01L 27/115 (20060101); H01L 21/768 (20060101); H01L 23/528 (20060101); H01L 29/788 (20060101); H01L 29/06 (20060101); H01L 29/66 (20060101); G11C 5/02 (20060101); H01L 29/792 (20060101);