Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/105)
  • Patent number: 8760584
    Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: June 24, 2014
    Assignee: MSTAR Semiconductor, Inc.
    Inventor: Po-Jen Yang
  • Patent number: 8758510
    Abstract: A method is used for producing an SiC volume monocrystal by sublimation growth. During growth, by sublimation of a powdery SiC source material and by transport of the sublimated gaseous components into the crystal growth region, an SiC growth gas phase is produced there. The SiC volume monocrystal grows by deposition from the SiC growth gas phase on the SiC seed crystal. The SiC seed crystal is bent during a heating phase before such that an SiC crystal structure with a non-homogeneous course of lattice planes is adjusted, the lattice planes at each point have an angle of inclination relative to the direction of the center longitudinal axis and peripheral angles of inclination at a radial edge of the SiC seed crystal differ in terms of amount by at least 0.05° and at most by 0.2° from a central angle of inclination at the site of the center longitudinal axis.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 24, 2014
    Assignee: SiCrystal Aktiengesellschaft
    Inventors: Thomas Straubinger, Michael Vogel, Andreas Wohlfart
  • Patent number: 8741413
    Abstract: A method and system of forming large-diameter SiC single crystals suitable for fabricating high crystal quality SiC substrates of 100, 125, 150 and 200 mm in diameter are described. The SiC single crystals are grown by a seeded sublimation technique in the presence of a shallow radial temperature gradient. During SiC sublimation growth, a flux of SiC bearing vapors filtered from carbon particulates is substantially restricted to a central area of the surface of the seed crystal by a separation plate disposed between the seed crystal and a source of the SiC bearing vapors. The separation plate includes a first, substantially vapor-permeable part surrounded by a second, substantially non vapor-permeable part. The grown crystals have a flat or slightly convex growth interface. Large-diameter SiC wafers fabricated from the grown crystals exhibit low lattice curvature and low densities of crystal defects, such as stacking faults, inclusions, micropipes and dislocations.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 3, 2014
    Assignee: II-VI Incorporated
    Inventors: Ilya Zwieback, Thomas E. Anderson, Andrew E. Souzis, Gary E. Ruland, Avinash K. Gupta, Varatharajan Rengarajan, Ping Wu, Xueping Xu
  • Patent number: 8728236
    Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: May 20, 2014
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo
  • Patent number: 8728237
    Abstract: A method for growing nitride semiconductor crystals contains: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, using a first carrier gas containing an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, using a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, using a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8728235
    Abstract: A manufacturing method for three-dimensional GaN epitaxial structure comprises a disposing step, in which a substrate of LiAlO2 and a source metal of Ga are disposed inside an vacuum chamber. An exposing step is importing N ions in plasma state and generated by a nitrogen source into the chamber. A heating step is heating up the source metal to generate Ga vapor. A growing step is forming a three-dimensional GaN epitaxial structure with hexagonal micropyramid or hexagonal rod having a broadened disk-like surface on the substrate by reaction between the Ga vapor and the plasma state of N ions.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: May 20, 2014
    Assignee: National Sun Yat-Sen University
    Inventors: I-Kai Lo, Chia-Ho Hsieh, Yu-Chi Hsu, Wen-Yuan Pang, Ming-Chi Chou
  • Patent number: 8715414
    Abstract: There are provided a Si(1-v-w-x)CwAlxNv substrate that achieves high crystallinity and low costs, an epitaxial wafer, and manufacturing methods thereof. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate according to the present invention includes the steps of preparing a different type of substrate 11 and growing a Si(1-v-w-x)CwAlxNv layer having a main surface on the different type of substrate 11. The component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer is 0<x+v<1. The component ratio x+v increases or decreases monotonically from the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 to the main surface of the Si(1-v-w-x)CwAlxNv layer. The component ratio x+v at the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 is closer to that of the material of the different type of substrate 11 than the component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: May 6, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, Hideaki Nakahata
  • Publication number: 20140106182
    Abstract: A sub-structure, suitable for use as a hot seed on which to form a perpendicular magnetic main write pole, is described. It is made up of a buffer layer of atomic layer deposited alumina on which there are one or more seed layers having a body-centered cubic (bcc) crystal structure. Finally, the high coercivity magnetic film lies on the seed layer(s). It is critical that the high coercivity magnetic film be deposited at a very low deposition rate (around 1 Angstrom per second).
    Type: Application
    Filed: October 14, 2012
    Publication date: April 17, 2014
    Applicant: HEADWAY TECHNOLOGIES, INC.
    Inventors: Shengyuan Wang, Kunliang Zhang, Min Li
  • Publication number: 20140090688
    Abstract: A backside illuminated multi-junction solar cell module includes a substrate, multiple multi-junction solar cells, and a cell interconnection that provides a series connection, between at least two of the multi-junction solar cells. The substrate may include a material that is substantially transparent to solar radiation. Each multi-junction solar cell includes a first active cell, grown over the substrate, for absorbing a first portion of the solar radiation for conversion into electrical energy and a second active cell, grown over the first active cell, for absorbing a second portion of the solar radiation for conversion into electrical energy. At least one of the first and second active cells includes a nitride.
    Type: Application
    Filed: December 4, 2013
    Publication date: April 3, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jizhong Li
  • Patent number: 8685165
    Abstract: Atomic layer deposition (ALD) type processes for producing titanium containing oxide thin films comprise feeding into a reaction space vapor phase pulses of titanium alkoxide as a titanium source material and at least one oxygen source material, such as ozone, capable of forming an oxide with the titanium source material. In preferred embodiments the titanium alkoxide is titanium methoxide.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: April 1, 2014
    Assignee: ASM International N.V.
    Inventors: Antti Rahtu, Raija Matero, Markku Leskela, Mikko Ritala, Timo Hatanpaa, Timo Hanninen, Marko Vehkamaki
  • Patent number: 8673074
    Abstract: A method of growing planar non-polar m-plane or semi-polar III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in an atmosphere of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: March 18, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Alexander Usikov, Alexander Syrkin, Robert G. W. Brown, Hussein S. El-Ghoroury, Philippe Spiberg, Vladimir Ivantsov, Oleg Kovalenkov, Lisa Shapovalova
  • Patent number: 8663389
    Abstract: A method and apparatus for depositing III-V material is provided. The apparatus includes a reactor partially enclosed by a selectively permeable membrane 12. A means is provided for generating source vapors, such as a vapor-phase halide of a group III element (IUPAC group 13) within the reactor volume 10, and an additional means is also provided for introducing a vapor-phase hydride of a group V element (IUPAC group 15) into the volume 10. The reaction of the group III halide and the group V hydride on a temperature-controlled substrate 18 within the reactor volume 10 produces crystalline III-V material and hydrogen gas. The hydrogen is preferentially removed from the reactor through the selectively permeable membrane 12, thus avoiding pressure buildup and reaction imbalance. Other gases within the reactor are unable to pass through the selectively permeable membrane.
    Type: Grant
    Filed: May 21, 2011
    Date of Patent: March 4, 2014
    Inventor: Andrew Peter Clarke
  • Patent number: 8652255
    Abstract: A method of: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxial grow silicon carbide on a wafer in the growth chamber; stopping or reducing the flow of the silicon source gas to interrupt the silicon carbide growth and maintaining the flow of the carrier gas while maintaining an elevated temperature in the growth chamber for a period of time; and resuming the flow of the silicon source gas to reinitiate silicon carbide growth. The wafer remains in the growth chamber throughout the method.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 18, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Robert E Stahlbush, Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, David Kurt Gaskill, Charles R. Eddy, Jr.
  • Patent number: 8647435
    Abstract: HVPE reactors and methods for growth of p-type group III nitride materials including p-GaN. A reaction product such as gallium chloride is delivered to a growth zone inside of a HVPE reactor by a carrier gas such as Argon. The gallium chloride reacts with a reactive gas such as ammonia in the growth zone in the presence of a magnesium-containing gas to grow p-type group III nitride materials. The source of magnesium is an external, non-metallic compound source such as Cp2Mg.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: February 11, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Vladimir A. Dmitriev, Oleg V. Kovalenkov, Vladimir Ivantsov, Lisa Shapovalov, Alexander L. Syrkin, Anna Volkova, Vladimir Sizov, Alexander Usikov, Vitali A. Soukhoveev
  • Patent number: 8636844
    Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
  • Patent number: 8628615
    Abstract: An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8603243
    Abstract: A method of: supplying sources of carbon and silicon into a chemical vapor deposition chamber; collecting exhaust gases from the chamber; performing mass spectrometry on the exhaust gases; and correlating a partial pressure of a carbon species in the exhaust gases to a carbon:silicon ratio in the chamber.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: December 10, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brenda L VanMil, Kok-Keong Lew, Rachael L Myers-Ward, Charles R. Eddy, Jr., David Kurt Gaskill
  • Publication number: 20130320275
    Abstract: In a crystal growth apparatus and method, polycrystalline source material and a seed crystal are introduced into a growth ambient comprised of a growth crucible disposed inside of a furnace chamber. In the presence of a first sublimation growth pressure, a single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a first gas that includes a reactive component that reacts with and removes donor and/or acceptor background impurities from the growth ambient during said sublimation growth. Then, in the presence of a second sublimation growth pressure, the single crystal is sublimation grown on the seed crystal via precipitation of sublimated source material on the seed crystal in the presence of a flow of a second gas that includes dopant vapors, but which does not include the reactive component.
    Type: Application
    Filed: May 24, 2013
    Publication date: December 5, 2013
    Inventors: Ilya Zwieback, Ping Wu, Varatharajan Rengarajan, Avinash K. Gupta, Thomas E. Anderson, Gary E. Ruland, Andrew E. Souzis, Xueping Xu
  • Patent number: 8591651
    Abstract: A method of epitaxially growing a SiC layer on a single crystal SiC substrate is described. The method includes heating a single-crystal SiC substrate to a first temperature of at least 1400° C. in a chamber, introducing a carrier gas, a silicon containing gas and carbon containing gas into the chamber; and epitaxially growing a layer of SiC on a surface of the SiC substrate. The SiC substrate is heated to the first temperature at a rate of at least 30° C./minute. The surface of the SiC substrate is inclined at an angle of from 1° to 3° with respect to a basal plane of the substrate material.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: November 26, 2013
    Assignee: Power Integrations, Inc.
    Inventor: Jie Zhang
  • Patent number: 8568531
    Abstract: A seed holder for use in a crystal growth reactor. The seed holder has a drool and a washer of outer diameter substantially the same as the drool inner diameter. A main body is disposed over the washer and drool, forming an enclosure above the washer and drool, the enclosure forming a cavity above the washer and drool.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: October 29, 2013
    Assignee: Pronomic Industry AB
    Inventors: Olof Claes Erik Kordina, Shailaja Rao, Joshua R. Christie
  • Patent number: 8568530
    Abstract: Precursors suitable for chemical vapor deposition, especially ALD, of hafnium oxide or zirconium oxide, have the general formula: (R1Cp)2MR2 wherein Cp represents a cyclopentadienyl ligand, R1 is H or a substituting alkyl group, alkoxy group or amido group of the Cp ligand, R2 is an alkyl group, an alkoxy group or an amido group and M is hafnium or zirconium.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: October 29, 2013
    Assignee: Sigma-Aldrich Co. LLC
    Inventors: Peter Nicholas Heys, Paul Williams, Fuquan Song
  • Patent number: 8568529
    Abstract: Embodiments disclosed herein generally relate to an HVPE chamber. The chamber may have two separate precursor sources coupled thereto to permit two separate layers to be deposited. For example, a gallium source and a separate aluminum source may be coupled to the processing chamber to permit gallium nitride and aluminum nitride to be separately deposited onto a substrate in the same processing chamber. The nitrogen may be introduced to the processing chamber at a separate location from the gallium and the aluminum and at a lower temperature. The different temperatures causes the gases to mix together, react and deposit on the substrate with little or no deposition on the chamber walls.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 29, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Tetsuya Ishikawa, David H. Quach, Anzhong Chang, Olga Kryliouk, Yuriy Melnik, Harsukhdeep S. Ratia, Son T. Nguyen, Lily Pang
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 8529697
    Abstract: A process for growing a crystal of a nitride semiconductor in which after the step of mounting a substrate (12) in a reaction tube (11), the step of feeding a first material gas containing a Group 3 element onto the substrate in the reaction tube and the step of feeding a second material gas containing elemental nitrogen onto the substrate in the reaction tube are carried out alternately to deposit a nitride semiconductor crystal directly on the substrate. The number of moles of the elemental nitrogen contained in the second material gas has a ratio of 200 or more to the number of moles of the Group 3 element in the first material gas.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: September 10, 2013
    Assignees: Honda Motor Co., Ltd.
    Inventors: Hideki Hashimoto, Akihiko Horiuchi, Hideo Kawanishi
  • Patent number: 8512471
    Abstract: In a physical vapor transport growth technique for silicon carbide a silicon carbide powder and a silicon carbide seed crystal are introduced into a physical vapor transport growth system and halosilane gas is introduced separately into the system. The source powder, the halosilane gas, and the seed crystal are heated in a manner that encourages physical vapor transport growth of silicon carbide on the seed crystal, as well as chemical transformations in the gas phase leading to reactions between halogen and chemical elements present in the growth system.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: August 20, 2013
    Assignee: II-VI Incorporated
    Inventors: Ilya Zwieback, Thomas E. Anderson, Avinash K. Gupta
  • Patent number: 8470090
    Abstract: Affords large-diametric-span AlN crystals, applicable to various types of semiconductor devices, with superior crystallinity, a method of growing the AlN crystals, and AlN crystal substrates. The AlN crystal growth method is a method in which an AlN crystal (4) is grown by vapor-phase epitaxy onto a seed crystal substrate (2) placed inside a crystal-growth compartment (24) within a crystal-growth vessel (12) provided within a reaction chamber, and is characterized in that during growth of the crystal, carbon-containing gas is supplied to the inside of the crystal-growth compartment (24).
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: June 25, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Michimasa Miyanaga, Tomohiro Kawase, Shinsuke Fujiwara
  • Patent number: 8465588
    Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 18, 2013
    Assignee: SORAA, Inc.
    Inventors: Christiane Poblenz, James S. Speck, Derrick S. Kamber
  • Patent number: 8455372
    Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: June 4, 2013
    Assignee: Fudan University
    Inventors: Qingqing Sun, Runchen Fang, Wen Yang, Pengfei Wang, Wei Zhang
  • Patent number: 8444765
    Abstract: A method for large-scale manufacturing of gallium nitride includes a process for reducing and/or minimizing contamination in the crystals, for solvent addition to an autoclave, for improving or optimizing the solvent atmosphere composition, for removal of the solvent from the autoclave, and for recycling of the solvent. The method is scalable up to large volumes and is cost effective.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: May 21, 2013
    Assignee: Soraa, Inc.
    Inventor: Mark P. D'Evelyn
  • Publication number: 20130095294
    Abstract: A silicon carbide ingot excellent in uniformity in characteristics and a silicon carbide substrate obtained by slicing the silicon carbide ingot, and a method of manufacturing the same are obtained. A method of manufacturing a silicon carbide ingot includes the steps of preparing a base substrate having an off angle with respect to a (0001) plane not greater than 1° and composed of single crystal silicon carbide and growing a silicon carbide layer on a surface of the base substrate. In the step of growing a silicon carbide layer, a temperature gradient in a direction of width when viewed in a direction of growth of the silicon carbide layer is set to 10° C./cm or less.
    Type: Application
    Filed: October 17, 2012
    Publication date: April 18, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: SUMITOMO ELECTRIC INDUSTRIES, LTD.
  • Patent number: 8404045
    Abstract: An underlying film 2 of a group III nitride is formed on a substrate 1 by vapor phase deposition. The substrate 1 and the underlying film 2 are subjected to heat treatment in the present of hydrogen to remove the underlying film 2 so that the surface of the substrate 1 is roughened. A seed crystal film 4 of a group III nitride single crystal is formed on a surface of a substrate 1A by vapor phase deposition. A group III nitride single crystal 5 is grown on the seed crystal film 4 by flux method.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: March 26, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshitaka Kuraoka, Shigeaki Sumiya, Makoto Miyoshi, Minoru Imaeda
  • Publication number: 20130061801
    Abstract: Provided is a method for manufacturing a silicon carbide crystal, including the steps of: placing a seed substrate and a source material for the silicon carbide crystal within a growth container; and growing the silicon carbide crystal with a diameter of more than 4 inches on a surface of the seed substrate by a sublimation method, in the step of growing, a pressure within the growth container being changed from a predetermined pressure, at a predetermined change rate.
    Type: Application
    Filed: August 3, 2012
    Publication date: March 14, 2013
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shinsuke FUJIWARA, Shin HARADA, Taro NISHIGUCHI, Hiroki INOUE, Naoki OOI
  • Patent number: 8394196
    Abstract: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 12, 2013
    Assignee: Applied Materials, Inc.
    Inventor: Yihwan Kim
  • Patent number: 8394197
    Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 12, 2013
    Assignee: Sub-One Technology, Inc.
    Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
  • Patent number: 8372199
    Abstract: Bulk GaN and AlGaN single crystal boules, preferably fabricated using a modified HVPE process, are provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth, for example to achieve n-, i-, or p-type conductivity.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: February 12, 2013
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Yuri V. Melnik, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A. Dmitriev
  • Patent number: 8349078
    Abstract: The present method of forming a nitride semiconductor epitaxial layer includes the steps of growing at least one layer of nitride semiconductor epitaxial layer on a nitride semiconductor substrate having a dislocation density lower than or equal to 1×107 cm?2 with a chemical decomposition layer interposed therebetween, the chemical decomposition layer being chemically decomposed at least with either a gas or an electrolytic solution, and decomposing the chemical decomposition layer at least with either the gas or the electrolytic solution at least either during or after the step of growing the nitride semiconductor epitaxial layer, thereby separating the nitride semiconductor epitaxial layer from the nitride semiconductor substrate. A high-quality nitride semiconductor epitaxial layer suffering less damage when separated from the nitride semiconductor substrate is thereby formed.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: January 8, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Yu Saitoh, Kazuhide Sumiyoshi, Akihiro Hachigo, Makoto Kiyama, Seiji Nakahata
  • Patent number: 8349076
    Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: January 8, 2013
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventors: In-Jae Song, Jai-yong Han
  • Patent number: 8338273
    Abstract: An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: December 25, 2012
    Assignee: University of South Carolina
    Inventors: M. Asif Khan, Vinod Adivarahan
  • Patent number: 8334015
    Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: December 18, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Sunil Shanker, Chi-I Lang
  • Patent number: 8278666
    Abstract: The disclosure relates to a high purity 2H-SiC composition and methods for making same. The embodiments represented herein apply to both thin film and bulk growth of 2H-SiC. According to one embodiment, the disclosure relates to doping an underlying substrate or support layer with one or more surfactants to nucleate and grow high purity 2H-SiC. In another embodiment, the disclosure relates to a method for preparing 2H-SiC compositions by nucleating 2H-SiC on another SiC polytype using one or more surfactants. The surfactants can include AlN, Te, Sb and similar compositions. These nucleate SiC into disc form which changes to hexagonal 2H-SiC material.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 2, 2012
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Narsingh B. Singh, Sean R. McLaughlin, Thomas J. Knight, Robert M. Young, Brian P. Wagner, David A. Kahler, Andre E. Berghmans, David J. Knuteson, Ty R. McNutt, Jerry W. Hedrick, Jr., George M. Bates, Kenneth Petrosky
  • Patent number: 8268076
    Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
  • Publication number: 20120227663
    Abstract: Lanthanum strontium manganate (La0.67Sr0.33Mn03, i.e., LSMO)/lanthanum manganate (LaMn03, i.e., LMO) perovskite oxide metal/semiconductor superlattices were investigated for potential p-type thermoelectric applications. Growth optimizations were performed using pulsed laser deposition to achieve epitaxial superlattices of LSMO (metal)/LMO (p-type semiconductor) on strontium titanate (STO) substrates. In-plane Seebeck results validated the p-type semiconducting and metallic behavior in LMO and LSMO thin films, respectively. Thermal conductivity measurements via the photo-acoustic (PA) technique showed that LSMO/LMO superlattices exhibit a room temperature cross-plane thermal conductivity (0.89 W/m·K) that is significantly lower than the thermal conductivity of individual thin films of either LSMO (1.60 W/m·K) or LMO (1.29 W/m·K).
    Type: Application
    Filed: March 8, 2012
    Publication date: September 13, 2012
    Applicant: PURDUE RESEARCH FOUNDATION
    Inventors: Pankaj Jha, Timothy D. Sands
  • Patent number: 8236103
    Abstract: A method for producing a Group III nitride semiconductor crystal includes a first step of supplying a Group III raw material and a Group V raw material at a V/III ratio of 0 to 1,000 to form and grow a Group III nitride semiconductor on a heated substrate and a second step of vapor-phase-growing a Group III nitride semiconductor crystal on the substrate using a Group III raw material and a nitrogen raw material.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: August 7, 2012
    Assignee: Showa Denko K.K.
    Inventors: Hisayuki Miki, Tetsuo Sakurai, Mineo Okuyama
  • Patent number: 8231724
    Abstract: The reactor for polycrystalline silicon is a reactor for polycrystalline silicon in which a silicon seed rod installed inside the reactor is heated by supplying electricity, a raw material gas supplied inside the reactor is allowed to react, thereby producing polycrystalline silicon on the surface of the silicon seed rod, and specifically, the reactor for polycrystalline silicon is provided with a raw material gas supply port installed on the bottom of the reactor and a raw material gas supply nozzle attached to the raw material gas supply port so as to be communicatively connected and extending upward, in which the upper end of the raw material gas supply nozzle is set to a height in a range from ?10 cm to +5 cm on the basis of the upper end of the electrode which retains the silicon seed rod.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: July 31, 2012
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshihide Endoh, Toshiyuki Ishii, Masaaki Sakaguchi, Naoki Hatakeyama
  • Patent number: 8231728
    Abstract: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam of a first group V element to form a first compound semiconductor layer; a second step of stopping the irradiation of the molecular beam of the group III element and the molecular beam of the first group V element to halt growth until an amount of the first group V element supplied is reduced to 1/10 or less of a supply of the first group V element in the first step; and a third step of irradiating a molecular beam of at least one of the group III elements and a molecular beam of a second group V element to form a second compound semiconductor layer, which is different from the first compound semiconductor, on the first compound semiconductor layer.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: July 31, 2012
    Assignee: Nippon Mining & Metals Co., Ltd.
    Inventors: Misao Takakusaki, Susumu Kanai
  • Patent number: 8226767
    Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: July 24, 2012
    Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
  • Patent number: 8216367
    Abstract: A method for producing a silicon carbide layer on a surface of a silicon substrate includes the step of irradiating the surface of the silicon substrate heated in a high vacuum at a temperature in a range of from 500° C. to 1050° C. with a hydrocarbon-based gas as well as an electron beam to form a cubic silicon carbide layer on the silicon substrate surface.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 10, 2012
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 8197596
    Abstract: A crystal growth process comprising providing a reactor having a crucible with an injector apparatus and a seed holder. The injector apparatus has an inner gas conduit and an outer gas conduit wherein an inert gas is introduced into the outer conduit. The injector apparatus has an upper injector and a lower injector and a gap therebetween. The upper injector temperature is maintained at a higher temperature than the lower injector.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: June 12, 2012
    Assignee: Pronomic Industry AB
    Inventors: Olof Claes Erik Kordina, Shailaja Rao
  • Patent number: 8187380
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: May 29, 2012
    Assignee: Apollo Diamond, Inc
    Inventors: Robert C. Linares, Patrick J. Doering
  • Patent number: 8168000
    Abstract: A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 1, 2012
    Assignee: International Rectifier Corporation
    Inventors: Mike Briere, Robert Beach