Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/105)
  • Patent number: 6780243
    Abstract: A method of growing a silicon carbide single crystal on a silicon carbide seed crystal in an inert gas environment includes the step of raising the seed crystal temperature to a growth temperature Tseed and raising the temperature of source material to a growth temperature Tsource that is lower than Tseed to define a thermal gradient therebetween. The process also requires maintaining constant seed temperature and constant source temperature throughout substantially the entire growth period of the single crystal. The growth period begins when the seed crystal and source material reach Tseed and Tsource. Another step requires changing only the pressure of the inert gas during the growth period to control the growth rate of the crystal rather than changing any temperatures to control the growth rate once growth of the single crystal has started.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: August 24, 2004
    Assignee: Dow Corning Enterprises, Inc.
    Inventors: Shaoping Wang, Aneta Kopec, Rodd Mitchell Ware, Sonia Holmes
  • Patent number: 6780241
    Abstract: The present invention provides methods of manufacturing and integrating optical devices. In one embodiment, a method of integrating an optical device may include forming a first device over a substrate, and forming a second device over the substrate and adjacent the first device with a deposition gas having an etchant selective to a deposited component of the deposition gas.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: August 24, 2004
    Assignee: TriQuint Technology Holding Co.
    Inventors: Abdallah Ougazzaden, Justin Larry Peticolas, Jr., Andrei Sirenko
  • Patent number: 6773509
    Abstract: An improved molecular beam epitaxy (MBE) system and method in which an interface and a processing component associated with the MBE system enables an operator to set up the molecular beam epitaxy system such that it will produce beam fluxes of the correct magnitude and with a high degree of precision in response to inputted growth criteria. In standard operation mode, after user input of desired growth parameters, a command file is started via interaction through the interface.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: August 10, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Stefan P. Svensson
  • Patent number: 6773508
    Abstract: To economically and easily fabricate a single crystal silicon carbide thin film. The apparatus for fabricating a single crystal silicon carbide thin film comprises a film-formation chamber 200 adapted to receive a SOI substrate 100 for film-formation, a gas supply means 300 for supplying various gases G1 to G4 necessary to fabricate a single crystal silicon carbide thin film to the film-formation chamber 200, a gas treatment means 500 for treating argon gas as an inert gas G1, propane gas as a hydrocarbon-based gas G2, hydrogen gas as a carrier gas, and oxygen gas G4 supplied to the film-formation chamber 200, and a temperature control means 400 for controlling the temperature of the film-formation chamber 200.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: August 10, 2004
    Assignees: Osaka Prefecture, Hosiden Corporation
    Inventors: Katsutoshi Izumi, Motoi Nakao, Yoshiaki Ohbayashi, Keiji Mine, Fumihiko Jobe
  • Patent number: 6770137
    Abstract: A crucible has first member and second cylindrical body, and is disposed in a lower chamber. The fist member is disposed in the second cylindrical body so as to define a gas flow path formed therebetween as a gap. A pedestal is disposed inside the first member. A seed crystal is fixed to the pedestal. SiC single crystals are formed on the pedestal by introducing a mixture gas through an inlet conduit. During growth of the SiC single crystals, conductance in introduction of the mixture gas into the crucible is larger than that in exhaust of the mixture gas, so that pressure of the mixture gas in the crucible is larger than that of the mixture gas after exhausted from the crucible.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: August 3, 2004
    Assignee: Denso Corporation
    Inventors: Kazukuni Hara, Masao Nagakubo, Shoichi Onda
  • Patent number: 6749685
    Abstract: Methods of growing silicon carbide are provided in which an electric arc is used to sublime a silicon carbide source material. In these embodiments, a silicon carbide seed crystal is introduced into a sublimation system, along with first and second electrodes that are separated by a gap. A power supply is coupled to at least one of the electrodes and used to create an electric arc across the gap between the two electrodes. This electric arc is used to sublime at least a portion of a silicon carbide source material. The vaporized silicon carbide material may then be encouraged to condense onto a seed material to produce monocrystalline or polycrystalline silicon carbide. In embodiments of the present invention, at least one of the electrodes is comprised of silicon carbide and serves as the silicon carbide source material.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: June 15, 2004
    Assignee: Cree, Inc.
    Inventor: Thomas G. Coleman
  • Patent number: 6749957
    Abstract: An acicular structure is formed of AlN on the main surface of a base made of single crystal. Then, a desired Al-including III nitride film is formed on the main surface of the base via the acicular structure.
    Type: Grant
    Filed: December 18, 2002
    Date of Patent: June 15, 2004
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Shigeaki Sumiya, Mitsuhiro Tanaka
  • Patent number: 6730163
    Abstract: An aluminum-containing material deposition method includes depositing a first precursor on a substrate in the substantial absence of a second precursor. The first precursor can contain a chelate of Al(NR1R2)x(NR3(CH2)zNR4R5)y or Al(NR1R2)x(NR3(CH2)zOR4)y; where x is 0, 1, or 2; y is 3−x; z is an integer 2 to 8; and R1 to R5 are independently selected from among hydrocarbyl groups containing 1 to 10 carbon atoms with silicon optionally substituted for one or more carbon atoms. The method includes depositing the second precursor on the first deposited precursor, the second precursor containing a nitrogen source or an oxidant. A deposition product of the first and second precursors includes at least one of an aluminum nitride or an aluminum oxide. The deposition method can be atomic layer deposition where the first and second precursors are chemisorbed or reacted as monolayers. The first precursor can further be non-pyrophoric.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: May 4, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 6716284
    Abstract: An apparatus and process for atomic layer deposition that minimizes mixing of the chemicals and reactive gases is disclosed. The first precursor and second precursor are only mixed with other chemicals and reactive gases when and where desired by installing and monitoring a dispensing fore-line. Also, independent and dedicated chamber outlets, isolation valves, exhaust fore-lines, and exhaust pumps are provided that are activated for the specific gas when needed.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: April 6, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Philip H. Campbell, David J. Kubista
  • Patent number: 6709989
    Abstract: A method of fabricating a semiconductor structure including the steps of: providing a silicon substrate having a surface; forming by atomic layer deposition a monocrystalline seed layer on the surface of the silicon substrate; and forming by atomic layer deposition one or more layers of a monocrystalline high dielectric constant oxide on the seed layer, where providing a substrate includes providing a substrate having formed thereon a silicon oxide, and wherein forming by atomic layer deposition a seed layer further includes depositing a layer of a metal oxide onto a surface of the silicon oxide, flushing the layer of metal oxide with an inert gas, and reacting the metal oxide and the silicon oxide to form a monocrystalline silicate.
    Type: Grant
    Filed: June 21, 2001
    Date of Patent: March 23, 2004
    Assignee: Motorola, Inc.
    Inventors: Jamal Ramdani, Ravindranath Droopad, Zhiyi Yu
  • Patent number: 6709512
    Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: March 23, 2004
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6689212
    Abstract: An &agr;-SiC bulk single crystal is formed from an SiC gas phase by deposition of SiC on an SiC seed crystal. To enable an SiC bulk single crystal of the 15R type to be grown reproducibly and without restricting the seed crystal, the deposition takes place under a uniaxial tensile strength which includes a predetermined angle with the [0001] axis of the bulk single crystal, so that a rhombohedral crystal is formed.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: February 10, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Harald Kuhn, Rene Stein, Johannes Völkl
  • Patent number: 6656269
    Abstract: Provided is a method of manufacturing a nitride system III-V compound layer which improves the quality and facilitates the manufacturing process and a method of manufacturing a substrate employing the method of manufacturing a nitride system III-V compound layer. A first growth layer is grown on a growth base at a growth rate, in a vertical direction to the growth surface, higher than 10 &mgr;m/h. Subsequently, a second growth layer is grown at a growth rate, in a vertical direction to the growth surface, lower than 10 &mgr;m/h. The first growth layer grown at the higher growth rate has a rough surface. However, the second growth layer is grown at the lower growth rate than that used for growing the first growth layer, so that depressions of the surface of the first growth layer are filled and thus the surface of the second growth layer is flattened. Further, growth takes place laterally so as to fill the depressions of the surface of the first growth layer.
    Type: Grant
    Filed: December 5, 2000
    Date of Patent: December 2, 2003
    Assignee: Sony Corporation
    Inventor: Satoshi Tomioka
  • Patent number: 6656573
    Abstract: Self-assembled nanowires are provided, comprising nanowires of a first crystalline composition formed on a substrate of a second crystalline composition. The two crystalline materials are characterized by an asymmetric lattice mismatch, in which in the interfacial plane between the two materials, the first material has a close lattice match (in any direction) with the second material and has a large lattice mismatch in all other major crystallographic directions with the second material. This allows the unrestricted growth of the epitaxial crystal in the first direction, but limits the width in the other.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: December 2, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yong Chen, R. Stanley Williams, Douglas A. A. Ohlberg
  • Patent number: 6648966
    Abstract: A method for making a free-standing, single crystal, gallium nitride (GaN) wafer includes forming a single crystal GaN layer directly on a single crystal LiAlO2 substrate using a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal GaN layer to make the free-standing, single crystal GaN wafer. Forming the single crystal GaN layer may comprise depositing GaN by vapor phase epitaxy (VPE) using the gallium halide reactant gas and a nitrogen-containing reactant gas. Because gallium halide is used as a reactant gas rather than a metal organic reactant such as trimethygallium (TMG), the growth of the GaN layer can be performed using VPE which provides commercially acceptable rapid growth rates. In addition, the GaN layer is also devoid of carbon throughout. Because the GaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm−2.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: November 18, 2003
    Assignee: Crystal Photonics, Incorporated
    Inventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou
  • Publication number: 20030200917
    Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 30, 2003
    Inventor: Brian A. Vaartstra
  • Patent number: 6638838
    Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: October 28, 2003
    Assignee: Motorola, Inc.
    Inventors: Kurt Eisenbeiser, Barbara M. Foley, Jeffrey M. Finder, Danny L. Thompson
  • Publication number: 20030188682
    Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporisable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporised, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2, with sufficiently short reaction times.
    Type: Application
    Filed: August 27, 2002
    Publication date: October 9, 2003
    Applicant: ASM Microchemistry OY
    Inventors: Eva Tois , Suvi Haukka , Marko Tuominen
  • Patent number: 6623559
    Abstract: A method for producing compound semiconductor quantum particles from at least a metallic element selected from Groups IIA, IIB, IIIA, IVA, and VA of the Periodic Table and at least a non-oxygen reactant element selected from the group consisting of P, As, S, Se, and Te. The method includes: (a) operating a heating and atomizing means to provide a stream of super-heated fine-sized fluid droplets of a selected metallic element into a reaction chamber; (b) directing a stream of a reactant element-containing fluid medium into the chamber to impinge upon and react with the super-heated metal fluid droplets to form substantially nanometer-sized phosphide, arsenide, sulfide, selenide, and/or telluride compound particles; and (c) cooling and/or passivating the compound particles to form the desired compound semiconductor quantum particles. These quantum particles are particularly useful for photo luminescence and biological labeling applications.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: September 23, 2003
    Assignee: Nanotek Instruments, Inc.
    Inventor: Wen-Chiang Huang
  • Patent number: 6616757
    Abstract: A method for growing bulk GaN and AlGaN single crystal boules, preferably using a modified HVPE process, is provided. The single crystal boules typically have a volume in excess of 4 cubic centimeters with a minimum dimension of approximately 1 centimeter. If desired, the bulk material can be doped during growth to achieve n-, i-, or p-type conductivity. In order to have growth cycles of sufficient duration, preferably an extended Ga source is used in which a portion of the Ga source is maintained at a relatively high temperature while most of the Ga source is maintained at a temperature close to, and just above, the melting temperature of Ga. To grow large boules of AlGaN, preferably multiple Al sources are used, the Al sources being sequentially activated to avoid Al source depletion and excessive degradation.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: September 9, 2003
    Assignee: Technologies and Devices International, Inc.
    Inventors: Yuri V. Melnik, Vitali Soukhoveev, Vladimir Ivantsov, Katie Tsvetkov, Vladimir A. Dmitriev
  • Patent number: 6610144
    Abstract: The present invention discloses a semiconductor film having a reduced dislocation density. The film comprises at least one interlayer structure, including a group III-nitride layer, a passivation interlayer disposed on the group III-nitride layer, interrupting the group III-nitride layer, and an island growth interlayer disposed on the passivation interlayer, and interrupting the group III-nitride layer. A method of making a semiconductor film of the present invention comprises producing a semiconductor film including at least one interlayer structure, each interlayer structure produced by the substeps of growing a group III-nitride layer, depositing a passivation interlayer on the group III-nitride layer, depositing an island growth interlayer on the passivation interlayer and continuing growing the group III-nitride layer.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: August 26, 2003
    Assignee: The Regents of the University of California
    Inventors: Umesh Kumar Mishra, Stacia Keller
  • Patent number: 6599361
    Abstract: A method is described for selectively depositing a GaN epitaxial layer on a substrate. The substrate is first patterned with a seed layer, preferably of AlN, and then the GaN epitxial layer is grown on the resulting patterned substrate by molecular beam epitaxy (MBE) such that growth occurs selectively over the seed layer.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: July 29, 2003
    Assignee: National Research Council of Canada
    Inventors: Haipeng Tang, James B. Webb, Jennifer A. Bardwell
  • Patent number: 6592661
    Abstract: A method of manufacturing semiconductor wafers in a processing chamber having at least one radiant heat source is provided. The method includes the steps of applying a predetermined amount of power to the radiant heat source and positioning a wafer within the processing chamber. The predetermined amount of power applied to the at least one radiant heat source is set such that the wafer reaches a predetermined temperature in a predetermined amount of time for carrying out a desired process in the processing chamber. The processing chamber is particularly suited for very low pressure environments and may be used to form HSG in a clustered or non-clustered system. A reflective plate may be used so that the radiated properties of the wafer are substantially independent of the emissivity of the wafer thereby minimizing emissivity variation from one wafer to another. Another plate may be used to form an isothermal cavity between the plate and the wafer to minimize emissivity variation from one wafer to another.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: July 15, 2003
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Ronald A. Weimer
  • Patent number: 6592942
    Abstract: Method for chemical vapor deposition of a film onto a substrate. Before bulk chemical vapor deposition the substrate is subjected to a nucleation treatment. The nucleation treatment comprises atomic layer deposition wherein the substrate is alternatingly and sequentially exposed to pulses of at least two mutually reactive gaseous reactants wherein the nucleation temperature is chosen to prevent condensation of either of the used reactants and to prevent substantial thermal decomposition of each of the reactants individually.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: July 15, 2003
    Assignee: ASM International N.V.
    Inventor: Margreet Albertine Anne-Marie Van Wijck
  • Patent number: 6592664
    Abstract: A method for epitaxial deposition of atoms or molecules from a reactive gas on a deposition surface of a substrate is described. The method includes the following steps: a first amount of energy is supplied by heating at least the deposition surface; and an ionized inert gas is conducted, at least from time to time, onto the deposition surface in order to supply, at least from time to time, a second amount of energy through the effect of ions of the ionized inert gas on the deposition surface. The first amount of energy is less than the energy amount necessary for the epitaxial deposition of atoms or molecules of the reactive gas on the deposition surface. A sum of the first energy amount and the second energy equaling, at least from time to time, a total amount of energy that is sufficient for the epitaxial deposition of atoms or molecules of the reactive gas onto the deposition surface.
    Type: Grant
    Filed: September 6, 2000
    Date of Patent: July 15, 2003
    Assignee: Robert Bosch GmbH
    Inventors: Wilhelm Frey, Franz Laermer, Klaus Heyers
  • Patent number: 6589336
    Abstract: Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation oxidation and allows ion implantation using only a photoresist film as a mask in a method for producing an epitaxial wafer having buried ion-implanted layers. Since an intentional formation of an oxide film, including such pre-implantation oxidation, on an epitaxial layer is omitted, the number of repetition of the thermal history exerted to the buried ion-implanted layers can be reduced, which effectively suppresses lateral diffusion of implanted ions. Since the formation and removal of the oxide film is thus no more necessary, the number of process steps in the production of the epitaxial wafer can dramatically be reduced.
    Type: Grant
    Filed: July 10, 2001
    Date of Patent: July 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koji Ebara, Hiroki Ose, Yasuo Kasahara
  • Patent number: 6589335
    Abstract: A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C. with a subsequent process for planarization of the InGaAs alloy.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: July 8, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Eugene A. Fitzgerald
  • Publication number: 20030121469
    Abstract: A method and apparatus for growing a thin film onto a substrate is disclosed. According to one embodiment, a plurality of substrates, each having a width and a length, are placed in a reaction space and the substrates are subjected to surface reactions of vapor-phase reactants according to the ALD method to form a thin film on the surfaces of the substrates. The reaction space comprises an elongated gas channel having a cross-section with a width greater that the height and which has a length which is at least 2 times greater than the length of one substrate in the direction of the gas flow in the channel, the channel having a folded configuration with at least one approximately 180 degree turn in the direction of the gas flow.
    Type: Application
    Filed: October 11, 2002
    Publication date: July 3, 2003
    Inventors: Sven Lindfors, Ivo Raaijmakers
  • Patent number: 6585823
    Abstract: Atomic layer deposition is used to provide a solid film on a plurality of disc shaped substrates. The substrates are entered spaced apart in a boat, in a furnace and heated to deposition temperature. In the furnace the substrate is exposed to alternating and sequential pulses of at least two mutually reactive reactants, in such way that the deposition temperature is high enough to prevent condensation of the at least two reactants on the surface but not high enough to result in significant thermal decomposition of each of the at least two reactants individually.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: July 1, 2003
    Assignee: ASM International, N.V.
    Inventor: Margreet Albertine Anne-Marie Van Wijck
  • Patent number: 6569534
    Abstract: An optical material including a crystalline silicon and FexSi2 in the form of dots, islands, or a film is provided. The FexSi2 has a symmetrical monoclinic crystalline structure belonging to the P21/c space group and is synthesized at the surface or in the interior of the crystalline silicon. The monoclinic structure corresponds to a deformed structure of &bgr;-FeSi2 generated by heteroepitaxial stress between the {110} plane of the FexSi2 and the {111} plane of the crystalline silicon. The value of x is 0.85≦x≦1.1. An optical element using the optical material is also provided.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: May 27, 2003
    Assignee: Mitsubishi Materials Corporation
    Inventors: Kenji Yamaguchi, Kazuki Mizushima
  • Patent number: 6562129
    Abstract: After a Group III-V compound semiconductor layer, to which a p-type dopant has been introduced, has been formed over a substrate, the compound semiconductor layer is annealed. In the stage of heating the compound semiconductor layer, atoms, deactivating the p-type dopant, are eliminated from the compound semiconductor layer by creating a temperature gradient in the compound semiconductor layer.
    Type: Grant
    Filed: April 19, 2001
    Date of Patent: May 13, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiaki Hasegawa, Ayumu Tsujimura, Isao Kidoguchi, Yuzaburo Ban
  • Publication number: 20030079676
    Abstract: The purpose of the invention is to provide a high resistivity silicon carbide substrate with electrical properties and structural quality suitable for subsequent device manufacturing, such as for example high frequency devices, so that the devices can exhibit stable and linear characteristics and to provide a high resistivity silicon carbide substrate having a low density of structural defects and a substantially controlled uniform radial distribution of its resistivity. (FIG. 2).
    Type: Application
    Filed: October 28, 2002
    Publication date: May 1, 2003
    Inventors: Alexandre Ellison, Nguyen Tien Son, Bjorn Magnusson, Erik Janzen
  • Patent number: 6551399
    Abstract: A method and apparatus for fabricating a metal-insulator-metal capacitor by performing atomic layer deposition (ALD). A fully integrated process flow prevents electrode-dielectric contamination during an essential ex situ bottom electrode patterning step.
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: April 22, 2003
    Assignee: Genus Inc.
    Inventors: Ofer Sneh, Thomas E. Seidel
  • Patent number: 6547877
    Abstract: A method and apparatus for axially growing single crystal silicon carbide is provided. Utilizing the system, silicon carbide can be grown with a dislocation density of less than 104 per square centimeter, a micropipe density of less than 10 per square centimeter, and a secondary phase inclusion density of less than 10 per cubic centimeter. As disclosed, a SiC source and a SiC seed crystal of the desired polytype are co-located within a crucible, the growth zone being defined by the substantially parallel surfaces of the source and the seed in combination with the sidewalls of the crucible. Prior to reaching the growth temperature, the crucible is evacuated and sealed, either directly or through the use of a secondary container housing the crucible. The crucible is comprised of tantalum or niobium that has been specially treated.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: April 15, 2003
    Assignee: The Fox Group, Inc.
    Inventors: Yury Alexandrovich Vodakov, Evgeny Nikolaevich Mokhov, Mark Grigorievich Ramm, Alexandr Dmitrievich Roenkov, Yury Nikolaevich Makarov, Sergei Yurievich Karpov, Mark Spiridonovich Ramm, Leonid Iosifovich Temkin
  • Publication number: 20030064570
    Abstract: The invention relates to a structure composed of a substrate wherein a surface supports juxtaposed islands, characterized in that the islands rest on a periodic network of terraces composed of the intersection of two step networks, each terrace having a first dimension corresponding to the step width of one of the step networks and a second dimension corresponding to the step width of the other step network, each terrace supporting at least two islands formed of a different superimposition of monolayers wherein the composition is chosen between at least one first composition and one second composition.
    Type: Application
    Filed: June 4, 2002
    Publication date: April 3, 2003
    Inventors: David Martrou, Noel Magnea
  • Patent number: 6537371
    Abstract: A method and apparatus for axially growing single crystal silicon carbide is provided. Utilizing the system, silicon carbide can be grown with a dislocation density of less than 104 per square centimeter, a micropipe density of less than 10 per square centimeter, and a secondary phase inclusion density of less than 10 per cubic centimeter. As disclosed, a SiC source and a SiC seed crystal of the desired polytype are co-located within a crucible, the growth zone being defined by the substantially parallel surfaces of the source and the seed in combination with the sidewalls of the crucible. Prior to reaching the growth temperature, the crucible is evacuated and sealed, either directly or through the use of a secondary container housing the crucible. The crucible is comprised of tantalum or niobium that has been specially treated.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: March 25, 2003
    Assignee: The Fox Group, Inc.
    Inventors: Yury Alexandrovich Vodakov, Evgeny Nikolaevich Mokhov, Mark Grigorievich Ramm, Alexandr Dmitrievich Roenkov, Yury Nikolaevich Makarov, Sergei Yurievich Karpov, Mark Spiridonovich Ramm, Leonid Iosifovich Temkin
  • Patent number: 6537370
    Abstract: The invention concerns a method which consists in: (a) stabilization of the monocrystalline silicon substrate temperature at a first predetermined temperature T1 of 400 to 500° C.; (b) chemical vapour deposition (CVD) of germanium at said first predetermined temperature T1 until a base germanium layer is formed on the substrate, with a predetermined thickness less than the desired final thickness; (c) increasing the CVD temperature from said first predetermined temperature T1 up to a second predetermined temperature T2 of 750 to 850° C.; and (d) carrying on with CVD of germanium at said second predetermined temperature T2 until the desired final thickness for the monocrystalline germanium final layer is obtained. The invention is useful for making semiconductor devices.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: March 25, 2003
    Assignee: France Télécom
    Inventors: Caroline Hernandez, Yves Campidelli, Daniel Bensahel
  • Patent number: 6528430
    Abstract: An atomic layer deposition (ALD) method employing Si2Cl6 and NH3, or Si2Cl6 and activated NH3 as reactants. In one embodiment, the invention includes the steps of (a) placing a substrate into a chamber, (b) injecting a first reactant containing Si2Cl6 into the chamber, (c) chemisorbing a first portion of the first reactant onto the substrate and physisorbing a second portion of the first reactant onto the substrate, d) removing the non-chemically absorbed portion of the first reactant from the chamber, (e) injecting a second reactant including NH3 into the chamber, (f) chemically reacting a first portion of the second reactant with the chemisorbed first portion of the first reactant to form a silicon-containing solid on the substrate, and (g) removing the unreacted portion of the second reactant from the chamber. In other embodiments, the first reactant can contain two or more compounds containing Si and Cl, such as Si2Cl6 and SiCl4.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: March 4, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kim Yeong Kwan, Park Young Wook, Lee Joo Won, Kim Dong Chan
  • Patent number: 6527855
    Abstract: Cobalt thin films were prepared by atomic layer deposition (ALD). The precursor cobalt(II) acetylacetonate [Co(C5H7O2)2] was used to selectively deposit films onto iridium substrates using hydrogen reduction. Cobalt growth was observed on SiO2, silicon, fluorinated silica glass (FSG), and tantalum when silane was used as a reducing agent.
    Type: Grant
    Filed: October 10, 2001
    Date of Patent: March 4, 2003
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Mark J. DelaRosa, Toh-Ming Lu, Atul Kumar
  • Patent number: 6527856
    Abstract: A method for changing the surface termination of a perovskite substrate surface, an example of which is the conversion of B-site terminations of a single-crystal STO substrate to A-site terminations. The method generally comprises the steps of etching the substrate surface by applying a reactive plasma thereto in the presence of fluorine or another halogen, and then annealing the substrate at a temperature sufficient to regenerate a long range order of the surface, i.e., the surface termination contributes to a better long range order in a film epitaxially grown on the surface. More particularly, the resulting substrate surfaces predominantly contains A-site surface terminations, i.e., SrO for STO (100) substrates. As a result, disadvantages associated with B-site terminated perovskite substrate surfaces are avoided. A suitable etching treatment is a low power oxygen ashing in the presence of low halogen levels.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Matthew Copel, James Misewich, Alejandro G. Schrott, Ying Zhang
  • Publication number: 20030037723
    Abstract: A method and apparatus for the high throughput epitaxial growth of a layer on the surface of a substrate by chemical vapor deposition is provided. In one embodiment, the method of the present invention comprises placing the substrate within a reactor vessel and passing a horizontal flow of reactant gas comprising a precursor chemical through the reactor vessel. The flow of the reactant gas is defined as having a Reynolds number of at least about 5000. The substrate is heated to a temperature sufficient to thermally decompose the precursor chemical and deposit an epitaxial layer on the substrate. In accordance with a preferred embodiment of the present invention, the substrate is placed within the reactor vessel at a position such that the flow of the reactant gas is characterized as a fully developed turbulent flow.
    Type: Application
    Filed: November 15, 2001
    Publication date: February 27, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Srikanth Kommu, Gregory M. Wilson
  • Publication number: 20030029376
    Abstract: Disclosed is a method for reproducibly producing large size, single crystals in a crystal growth chamber. The method includes the steps of: (a) forming a plurality of smaller size tiles of single crystals of substantially the same crystal orientation as the desired large size, single crystal; (b) assembling the plurality of smaller tiles into a structure having a larger size while minimizing gapping between adjacent tiles; (c) placing the assembly of smaller tiles formed in step (b) into a growth chamber; and (d) through a growth reaction carried out in the growth chamber, forming a large size single crystal using the assembly of smaller tiles formed in step (b) as a seed crystal for the growth reaction.
    Type: Application
    Filed: September 11, 2002
    Publication date: February 13, 2003
    Inventors: David W Snyder, William J. Everson
  • Patent number: 6503610
    Abstract: Provided is a method of producing a group III-V compound semiconductor having a low dislocation density without increasing the thickness of a re-grown layer, the method includes a re-growing process using a mask pattern, and threading dislocations in the re-grown layer are terminated by the voids formed on the pattern.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: January 7, 2003
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6500258
    Abstract: This invention relates to a method of growing a nitride semiconductor layer by molecular beam epitaxy comprising the steps of: a) heating a GaN substrate (S) disposed in a growth chamber (10) to a substrate temperature of at least 850° C.; and b) growing a nitride semiconductor layer on the GaN substrate by molecular beam epitaxy at a substrate temperature of at least 850° C., ammonia gas being supplied to the growth chamber (10) during the growth of the nitride semiconductor layer; wherein the method comprises the further step of commencing the supply ammonia gas to the growth chamber during step (a), before the substrate temperature has reached 800° C.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: December 31, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jonathan Heffernan, Jennifer Mary Barnes, Alistair Henderson Kean
  • Patent number: 6500256
    Abstract: In case of epitaxially growing a single crystal silicon layer by catalytic CVD on a material layer in lattice alignment with single crystal silicon, i.e. a substrate of single crystal silicon, sapphire, spinel, or the like, the total pressure of the growth atmosphere is maintained in the range from 1.33×10−3 Pa to 4 Pa at least in the initial period of the epitaxial growth, or alternatively, partial pressure of oxygen and moisture in the growth atmosphere is maintained in the range from 6.65×10−10 to 2×10−6 Pa at least in the initial period of the epitaxial growth. Thus, the maximum oxygen concentration of the epitaxially grown single crystal silicon layer becomes not higher than 3×1018 atoms/cm−3 at least in a portion with the thickness of 10 nm from the boundary with the substrate 4. It is thus ensured to epitaxially grow a high-quality single crystal silicon layer at a lower temperature than that of existing CVD.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: December 31, 2002
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6497764
    Abstract: A method is described for growing at least one silicon carbide (SiC) single crystal by sublimation of a SiC source material. Silicon, carbon and a SiC seed crystal are introduced into a growing chamber. Then, the SiC source material is produced from the silicon and the carbon in a synthesis step that takes place before the actual growing. The growing of the SiC single crystal is then carried out immediately after the synthesis step. The carbon used is a C powder with a mean grain diameter of greater than 10 &mgr;m.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: December 24, 2002
    Assignee: Siemens Aktiengesellschaft
    Inventors: Harald Kuhn, Rene Stein, Johannes Völkl
  • Publication number: 20020189535
    Abstract: Source gases and atomic hydrogen are alternately supplied onto a substrate on which a crystal is to be grown. By exposing a surface of the substrate to the atomic hydrogen, the ratio of Ge atoms attached to H atoms to all Ge atoms present on the outermost surface where growth is proceeding is increased compared with that prior to the exposure to the atomic hydrogen. If H atoms are attached to Ge atoms on the outermost surface, the phenomenon occurs in which the Ge atoms are interchanged with Si atoms present in the underlying layer. As a result, a higher proportion of Ge atoms are interchanged with Si atoms than in a conventional manufacturing method which does not involve the exposure to the atomic hydrogen. This reduces the ratio of Ge atoms to all atoms on the outermost surface where growth is proceeding and renders C atoms having low affinity with Ge atoms more likely to occupy lattice positions in the crystal.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 19, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshihiko Kanzawa, Katsuya Nozawa, Tohru Saitoh, Minoru Kubo
  • Publication number: 20020189534
    Abstract: A method is described for selectively depositing a GaN epitaxial layer on a substrate. The substrate is first patterned with a seed layer, preferably of AlN, and then the GaN epitxial layer is grown on the resulting patterned substrate by molecular beam epitaxy (MBE) such that growth occurs selectively over the seed layer.
    Type: Application
    Filed: June 18, 2001
    Publication date: December 19, 2002
    Inventors: Haipeng Tang, James B. Webb, Jennifer A. Bardwell
  • Patent number: 6485564
    Abstract: In a thin film forming method of the invention, an atmosphere for a base as a thin film forming target is set to a high vacuum of, e.g., 0.01 Torr or less, and a gas of an organometallic compound and an oxidizing gas are introduced onto a base surface heated to about 450° C., to form a plurality of crystal nuclei, made of an oxide of a metal constituting the organometallic compound, on the base surface. The atmosphere for the base is then set to a lower vacuum than the first vacuum degree, and the gas of the organometallic compound and the oxidizing gas are subsequently introduced onto the base surface heated to about 45° C., to form a film made of the oxide of the metal there.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: November 26, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Yijun Liu, Hiroshi Shinriki, Takashi Magara
  • Publication number: 20020166502
    Abstract: A low defect density (Ga,Al,In)N material. The (Ga, Al, In)N material may be of large area, crack-free character, having a defect density as low as 3×106 defects/cm2 or lower. Such (Ga,Al,In)N material is useful as a substrate for epitaxial growth of Group III-V nitride device structures thereon.
    Type: Application
    Filed: March 21, 2002
    Publication date: November 14, 2002
    Inventors: Robert P. Vaudo, Vivek M. Phanse, Michael A. Tischler