Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/105)
  • Patent number: 8143147
    Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: March 27, 2012
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
  • Patent number: 8137459
    Abstract: The inventive method for producing nanoparticles for ferrofluids by electron-beam evaporation and condensation in vacuum, consists in evaporating an initial solid material and in fixing nanoparticles to a cooled substrate by means of a solidifiable carrier during vapour condensation, wherein a solid inorganic material, which is selected from a group containing metals, alloys or oxides thereof, is used as an initial material and a solid liquid-soluble material is used as a magnetic carrier material for fixing nanoparticles. The method also consists in simultaneously evaporating the initial material and the carrier composition by electron-beam heating. The vapour is deposited on the substrate, the temperature which is lower than the melting point of the carrier material, and the condensate of the magnetic material nanoparticles, which have a size and are fixed in the carrier, is produced. The particle size is adjusted by setting the specified temperature of the substrate during vapour deposition.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: March 20, 2012
    Assignee: State Enterprise “International Center For Electron Beam Technologies of E.O. Paton Electric Welding Institute of National Academy of Sciences of Ukraine”
    Inventors: Boris Paton, Boris Movchan, Iurii Kurapov
  • Patent number: 8123859
    Abstract: A method and apparatus for producing bulk single crystals of AlN having low dislocation densities of about 10,000 cm?2 or less includes a crystal growth enclosure with Al and N2 source material therein, capable of forming bulk crystals. The apparatus maintains the N2 partial pressure at greater than stoichiometric pressure relative to the Al within the crystal growth enclosure, while maintaining the total vapor pressure in the crystal growth enclosure at super-atmospheric pressure. At least one nucleation site is provided in the crystal growth enclosure, and provision is made for cooling the nucleation site relative to other locations in the crystal growth enclosure. The Al and N2 vapor is then deposited to grow single crystalline low dislocation density AlN at the nucleation site. High efficiency ultraviolet light emitting diodes and ultraviolet laser diodes are fabricated on low defect density AlN substrates, which are cut from the low dislocation density AlN crystals.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: February 28, 2012
    Assignee: Crystal IS, Inc.
    Inventors: Leo J. Schowalter, Glen A. Slack, J. Carlos Rojo
  • Publication number: 20120015814
    Abstract: A high temperature superconductor (=HTS) coated conductor (1), comprising an HTS layer (11) deposited epitaxially on a substrate (2), wherein the HTS layer (11) exhibits a lattice with a specific crystal axis being oriented perpendicular to the substrate plane (SP), in particular wherein the HTS layer material is of ReBCO type and the c-axis (c) is oriented perpendicular to the substrate plane (SP), wherein the HIS layer (11) comprises particle inclusions (4),in particular wherein the particle inclusions (4) may be used to introduce pinning of magnetic flux, is characterized in that at least a part (4a) of the particle inclusions (4) are formed of the same material as the HTS layer (11), and/or of chemical fractions of the material of the HTS layer (11), such that the average stoichiometry of said part (4a) of the particle inclusions (4) corresponds to the stoichiometry of the HTS layer (11), and that the particle inclusions of said part (4a) are discontinuities of the lattice of the HTS layer (11).
    Type: Application
    Filed: July 18, 2011
    Publication date: January 19, 2012
    Applicant: Bruker HTS GmbH
    Inventors: Alexander Usoskin, Klaus Schlenga
  • Patent number: 8071466
    Abstract: Zinc sulfide (ZnS) single crystals and multi-grain ZnS crystals are suitable for many applications. The disclosed method produces ZnS single crystals or multi-grain ZnS crystals. More specifically, ZnS single crystals or multi-grain ZnS crystals of pure or substantially pure hexagonal wurtzite structure with sufficiently high purity and crystalline perfection to be used to fabricate components and devices including but not limited to optical components (useful in the infrared (IR) & visible spectrum range of 0.34-14 ?m), photoluminescence devices, cathode luminescence devices, electroluminescence devices, semiconductor devices, and IR laser gain mediums (in the wave length range of 1-5 ?m).
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: December 6, 2011
    Assignee: Fairfield Crystal Technology, LLC
    Inventor: Shaoping Wang
  • Patent number: 8062422
    Abstract: Embodiments described herein are directed to an apparatus for generating a precursor for a semiconductor processing system. In one embodiment, an apparatus for generating a precursor gas during a vapor deposition process is described. The apparatus includes a canister containing an interior volume between a lid and a bottom, a gaseous inlet and a gaseous outlet disposed on the lid, a plurality of silos coupled to the bottom and extending from a lower region to an upper region of the interior volume, and a tantalum precursor having a chlorine concentration of about 5 ppm or less contained within the lower region of the canister.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: November 22, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Ling Chen, Vincent W. Ku, Hua Chung, Christophe Marcadal, Seshadri Ganguli, Jenny Lin, Dien-Yeh Wu, Alan Ouye, Mei Chang
  • Patent number: 8048225
    Abstract: The present invention includes a high-quality, large-area bulk GaN seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal is of ultra-low defect density, has flat surfaces free of bowing, and is free of foreign substrate material. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: November 1, 2011
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, Mathew C. Schmidt, Derrick S. Kamber
  • Patent number: 8048223
    Abstract: The present invention provides in one example embodiment a synthetic diamond and a method of growing such a diamond on a plurality of seed diamonds, implanting the grown diamond with ions, and separating the grown diamond from the plurality of seed diamonds.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: November 1, 2011
    Assignee: Apollo Diamond, Inc.
    Inventors: Alfred Genis, Robert C. Linares, Patrick J. Doering
  • Patent number: 8043687
    Abstract: A method for forming a graphene layer is disclosed herein. The method includes establishing an insulating layer on a substrate such that at least one seed region, which exposes a surface of the substrate, is formed. A seed material in the seed region is exposed to a carbon-containing precursor gas, thereby initiating nucleation of the graphene layer on the seed material and enabling lateral growth of the graphene layer along at least a portion of a surface of the insulating layer.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: October 25, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Theodore I. Kamins, R. Stanley Williams, Nathaniel Quitoriano
  • Patent number: 8021482
    Abstract: A method for eliminating precipitates contained in an II-VI solid semiconductor material, in which the solid semiconductor material is a congruent sublimation solid semiconductor material, the method including: providing an inert gas flow; heating the solid semiconductor material under the inert gas flow up to a temperature T, between a first temperature T1, corresponding to compound II-VI/element VI eutectic, and a second temperature T2, corresponding to maximum congruent sublimation temperature; maintaining the solid semiconductor material at this temperature T under a neutral gas flow for a time period sufficient to eliminate the precipitates; cooling the solid semiconductor material under the inert gas flow from temperature T to ambient temperature, at a rate such that, during the cooling, the solid semiconductor material merges with its congruent sublimation line; and recovering a precipitate-free solid semiconductor material.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: September 20, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Bernard Pelliciari
  • Patent number: 8007588
    Abstract: A vapor phase epitaxial growth method using a vapor phase epitaxy apparatus having a chamber, a support structure holding thereon a substrate in the chamber, a first flow path supplying a reactant gas for film formation on the substrate and a second flow path for exhaust of the gas, said method includes rotating the substrate, supplying the reactant gas and a carrier gas to thereby perform vapor-phase epitaxial growth of a semiconductor film on the substrate, and during the vapor-phase epitaxial growth of the semiconductor film on the substrate, controlling process parameters to make said semiconductor film uniform in thickness, said process parameters including flow rates and concentrations of the reactant gas and the carrier gas, a degree of vacuum within said chamber, a temperature of the substrate, and a rotation speed of said substrate.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: August 30, 2011
    Assignee: NuFlare Technology, Inc.
    Inventors: Hideki Ito, Satoshi Inada, Yoshikazu Moriyama
  • Patent number: 7976630
    Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: July 12, 2011
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, James S. Speck, Derrick S. Kamber
  • Patent number: 7955435
    Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: June 7, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Patent number: 7947128
    Abstract: In one embodiment the present invention provides for a method for depositing a thin film layer onto a composite tape 16, that comprises depositing at least one thin film layer of physically enhancing material 30 onto at least one portion of the composite tape. The depositing is accomplished by atomic layer epitaxy and the thin film layer is approximately 1-10 molecules thick.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: May 24, 2011
    Assignee: Siemens Energy, Inc.
    Inventor: Douglas J. Conley
  • Patent number: 7942966
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: May 17, 2011
    Assignee: Apollo Diamond, Inc.
    Inventors: Robert C. Linares, Patrick J. Doering
  • Publication number: 20110042684
    Abstract: Affords an AlN crystal growth method, and an AlN laminate, wherein AlN of favorable crystalline quality is grown. The AlN crystal growth method is provided with the following steps. To begin with, a source material (17) containing AlN is prepared. A heterosubstrate (11), having a major surface (11a), is prepared. The source material (17) is sublimed to grow AlN crystal so as to cover the major surface (11a) of the heterosubstrate (11), whereby a first layer (12) with a flat face (12a) is formed. The source material (17) is sublimed to form onto the face (12a) of the first layer (12) a second layer (13) made of AlN. The second layer (13) is formed at a higher temperature than is the first layer (12).
    Type: Application
    Filed: April 14, 2009
    Publication date: February 24, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keisuke Tanizaki, Naho Mizuhara, Michimasa Miyanaga, Issei Satoh, Hideaki Nakahata, Yoshiyuki Yamamoto
  • Patent number: 7887634
    Abstract: In a method of producing a semiconductor element in a substrate, a plurality of carbide precipitates is formed in the substrate, doping atoms are implanted into the substrate, thereby forming crystal defects in the substrate, the substrate is heated, such that at least a part of the crystal defects is eliminated using the carbide precipitates, and the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: February 15, 2011
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7867335
    Abstract: GaN is grown by creating a Ga vapor from a powder, and using an inert purge gas from a source to transport the vapor to a growth site where the GaN growth takes place. In one embodiment, the inert gas is N2, and the powder source is GaN powder that is loaded into source chambers. The GaN powder is congruently evaporated into Ga and N2 vapors at temperatures between approximately 1000 and 1200° C. The formation of Ga liquid in the powder is suppressed by the purging of an inert gas through the powder. The poser may also be isolated from a nitride containing gas provided at the growth cite. In one embodiment, the inert gas is flowed through the powder.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: January 11, 2011
    Assignee: Cornell Research Foundation, Inc.
    Inventors: Michael G. Spencer, Phani Konkapaka, Huaqiang Wu, Yuri Makarov
  • Patent number: 7858536
    Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
  • Patent number: 7857907
    Abstract: The present invention relates to a method for forming a layered structure with silicon nanocrystals. In one embodiment, the method comprises the steps of: (i) forming a first conductive layer on a substrate, (ii) forming a silicon-rich dielectric layer on the first conductive layer, and (iii) laser-annealing at least the silicon-rich dielectric layer to induce silicon-rich aggregation to form a plurality of silicon nanocrystals in the silicon-rich dielectric layer. The silicon-rich dielectric layer is one of a silicon-rich oxide film having a refractive index in the range of about 1.4 to 2.3, or a silicon-rich nitride film having a refractive index in the range of about 1.7 to 2.3. The layered structure with silicon nanocrystals in a silicon-rich dielectric layer is usable in a solar cell, a photodetector, a touch panel, a non-volatile memory device as storage node, and a liquid crystal display.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: December 28, 2010
    Assignee: AU Optronics Corporation
    Inventors: An-Thung Cho, Chih-Wei Chao, Chia-Tien Peng, Wan-Yi Liu, Ming-Wei Sun
  • Patent number: 7837790
    Abstract: Methods and apparatus for formation and treatment of epitaxial layers containing silicon and carbon are disclosed. Treatment of the epitaxial layer converts interstitial carbon to substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices. In specific embodiments, the treatment of the epitaxial layer involves annealing for short periods of time, for example, by laser annealing, millisecond annealing, rapid thermal annealing, and spike annealing in a environment containing nitrogen.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Yihwan Kim, Arkadii V. Samoilov
  • Patent number: 7830027
    Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: November 9, 2010
    Assignees: Commissariat a l'Energie Atomique, Freescale Semiconductor, Inc.
    Inventors: Bernard Diem, Eugene Blanchet, Bishnu Gogoi
  • Patent number: 7820244
    Abstract: In a method of forming a layer, a titanium layer and a titanium nitride layer may be successively formed on a first wafer. By-products adhered to the inside of a chamber during the formation of the titanium nitride layer may be removed from the chamber. Processes of forming the titanium layer, forming the titanium nitride layer, and removing the by-products may be repeated relative to a second wafer.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: October 26, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hun Seo, Jin-Gi Hong, Yun-Ho Choi, Hyun-Chul Kwun, Eun-Taeck Lee, Jin-Ho Kim
  • Patent number: 7815735
    Abstract: The invention refers to a method and apparatus for CVD coating and to a coated body. To improve the mechanical properties of the structure and surface of the body and to make the method and apparatus as simple and cost-effective as possible, it is suggested in the method, in which a layer is deposited on a substrate in a carbon-containing gas atmosphere: that the process parameters be varied during the coating period in such a way that during the coating period a first operating mode and a second operating mode are repeatedly alternated, wherein in the first operating mode a higher carbon over-saturation of the gas atmosphere occurs near the substrate, and in the second operating mode a lower carbon over-saturation of the gas atmosphere occurs near the substrate. In this way, a body can be produced with a substrate and at least one layer deposited on the surface of the substrate, wherein the layer consists of nano-crystalline diamond.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: October 19, 2010
    Assignee: Cemecon AG
    Inventors: Dirk Breidt, Oliver Lemmer, Martin Frank
  • Publication number: 20100251958
    Abstract: The invention provides an epitaxial growth method which is a single wafer processing epitaxial growth method by which at least a single crystal substrate is placed in a reaction chamber with an upper wall having a downward convexity and an epitaxial layer is deposited on the single crystal substrate by introducing raw material gas and carrier gas into the reaction chamber through a gas feed port, in which, after any one of the radius of curvature of the upper wall of the reaction chamber and a difference between an upper end of the gas feed port and a lower end of the upper wall of the reaction chamber in the height direction or both are adjusted in accordance with the flow rate of the carrier gas which is introduced into the reaction chamber through the gas feed port, an epitaxial layer is deposited on the single crystal substrate.
    Type: Application
    Filed: November 18, 2008
    Publication date: October 7, 2010
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Masato Ohnishi
  • Patent number: 7807126
    Abstract: A method for manufacturing a diamond single crystal substrate, in which a single crystal is grown from a diamond single crystal serving as a seed substrate by vapor phase synthesis, said method comprising: preparing a diamond single crystal seed substrate which has a main surface whose planar orientation falls within an inclination range of not more than 8 degrees relative to a {100} plane or a {111} plane, as a seed substrate; forming a plurality of planes of different orientation which are inclined in the outer peripheral direction of the main surface relative to the main surface on one side of this seed substrate, by machining; and then growing a diamond single crystal by vapor phase synthesis.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: October 5, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
  • Patent number: 7799132
    Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: September 21, 2010
    Assignee: Zyvex Labs, LLC
    Inventors: John N. Randall, Jingping Peng, Jun-Fu Liu, George D. Skidmore, Christof Baur, Richard E. Stallcup, Robert J. Folaron
  • Patent number: 7794540
    Abstract: Method of manufacturing a semiconductor device, in which on a region of silicon oxide (5) situated next to a region of monocrystalline silicon (4) at the surface (3) of a semiconductor body (1), a non-monocrystalline auxiliary layer (8) is formed. The auxiliary layer is formed in two steps. In the first step, the silicon body is heated in an atmosphere comprising a gaseous arsenic compound; in the second step it is heated in an atmosphere comprising a gaseous silicon compound instead of said arsenic compound. Thus, the regions of silicon oxide are provided with an amorphous or polycrystalline silicon seed layer in a self-aligned manner.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: September 14, 2010
    Assignee: NXP B.V.
    Inventors: Petrus Hubertus Cornelis Magnee, Johannes Josephus Theodorus Marinus Donkers, Xiaoping Shi
  • Patent number: 7790584
    Abstract: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal thin film on the semi-polar nitride single crystal base layer having the dielectric pattern layer in a lateral direction. The growing of the semi-polar nitride single crystal thin film in a lateral direction includes primarily growing the semi-polar nitride single crystal thin film in the lateral direction such that part of a growth plane on the semi-polar nitride single crystal base layer has an a-plane, and secondarily growing the semi-polar nitride single crystal thin film in the lateral direction such that sidewalls of the primarily grown semi-polar nitride single crystal thin film are combined to have a (11 22) plane.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: September 7, 2010
    Assignee: Samsung Led Co., Ltd.
    Inventors: Ho Sun Paek, Jeong Wook Lee, Youn Joon Sung
  • Patent number: 7785415
    Abstract: Systems and methods for local synthesis of silicon nanowires and carbon nanotubes, as well as electric field assisted self-assembly of silicon nanowires and carbon nanotubes, are described. By employing localized heating in the growth of the nanowires or nanotubes, the structures can be synthesized on a device in a room temperature chamber without the device being subjected to overall heating. The method is localized and selective, and provides for a suspended microstructure to achieve the thermal requirement for vapor deposition synthesis, while the remainder of the chip or substrate remains at room temperature. Furthermore, by employing electric field assisted self-assembly techniques according to the present invention, it is not necessary to grow the nanotubes and nanowires and separately connect them to a device. Instead, the present invention provides for self-assembly of the nanotubes and nanowires on the devices themselves, thus providing for nano- to micro-integration.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: August 31, 2010
    Assignee: The Regents of the University of California
    Inventors: Liwei Lin, Ongi Englander, Dane Christensen
  • Patent number: 7767021
    Abstract: A growing method of a SiC single crystal includes the steps of thermal treatment of a high purity SiC source for decreasing a specific surface area and increasing a ratio of ?-phase and making a mole fraction of C greater than that of Si in the source, providing the SiC source into a crucible, arranging a SiC seed in the crucible, and growing the SiC single crystal by heating the SiC source.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: August 3, 2010
    Assignee: NeosemiTech Corporation
    Inventors: Soo-Hyung Seo, Joon-Suk Song, Myung-Hwan Oh
  • Patent number: 7767022
    Abstract: A crystal is sublimation grown in a crucible by way of a temperature gradient in the presence of between 1 and 200 Torr of inert gas. The pressure of the inert gas is then increased to between 300 and 600 Torr, while the temperature gradient is maintained substantially constant. The temperature gradient is then reduced and the temperature in the crucible is increased sufficiently to anneal the crystal. Following cooling and removal from the crucible, the crystal is heated in the presence of oxygen in an enclosure to a temperature sufficient to remove unwanted material from the crystal. Following cooling and removal from the enclosure, the crystal surrounded by another instance of the source material is heated in a crucible in the presence 200 and 600 Torr of inert gas to a temperature sufficient to anneal the crystal.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: August 3, 2010
    Assignee: II-VI Incorporated
    Inventors: Avinash K. Gupta, Ilya Zwieback, Jihong Chen, Marcus Getkin, Walter R. M. Stepko, Edward Semenas
  • Publication number: 20100180814
    Abstract: A method of fabricating an SiC single crystal includes (a) physical vapor transport (PVT) growing a SiC single crystal on a seed crystal in the presence of a temperature gradient, wherein an early-to-grow portion of the SiC single crystal is at a lower temperature than a later-to-grow portion of the SiC single crystal. Once grown, the SiC single crystal is annealed in the presence of a reverse temperature gradient, wherein the later-to-grow portion of the SiC single crystal is at a lower temperature than the early-to-grow portion of the SiC single crystal.
    Type: Application
    Filed: June 26, 2008
    Publication date: July 22, 2010
    Applicant: II-VI INCORPORATED
    Inventors: Ping Wu, Ilya Zwieback, Avinesh K. Gupta, Edward Semenas
  • Patent number: 7758697
    Abstract: Methods for depositing a silicon-containing film are described. The methods may include delivering a silicon compound to a surface or a substrate, and reacting the silicon compound to grow the silicon-containing film. The silicon compound may be one or more compounds having a formula selected from the group Si4X8, Si4X10, Si5X10, and Si5X12, where X is independently a hydrogen or halogen.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: July 20, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Paul B. Comita, Lance A. Scudder, David K. Carlson
  • Patent number: 7754013
    Abstract: A deposition station allows atomic layer deposition (ALD) of films onto a substrate. The station comprises an upper and a lower substantially flat part between which a substrate is accommodated. The parts are positioned opposite each other and parallel to the substrate during processing. At least one of the parts is provided with a plurality of gas channels that allow at least two mutually reactive reactants to be discharged out of that part to the substrate. The discharge is configured to occur in a sequence of alternating, separated pulses for ALD. In addition, each part is preferably configured to be about 1 mm or less from the substrate to minimize the volume of the reaction chamber to increase the efficiency with which gases are purged from the chamber. Also, for each reactant, the upper and lower parts are preferably kept at a temperature outside of the window in which optimal ALD of that reactant occurs, thereby minimizing deposition of that reactant on deposition station surfaces.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 13, 2010
    Assignee: ASM International N.V.
    Inventor: Ernst H. A. Granneman
  • Patent number: 7749828
    Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: July 6, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
  • Patent number: 7736435
    Abstract: A method for producing a single crystals by preferential epitaxial growth of {100} face, comprising the steps of (1) growing the crystal on a single crystal {100} substrate; (2) forming on the side of the grown crystal a surface parallel to a {100} face different from the {100}face in the growth direction, and (3) growing the crystal on the formed {100} surface; and the steps (2) and (3) being performed once or more than once. A method for producing a single-crystal diamond using a metallic holder for the single-crystal diamond having a crystal holding portion which is raised above an outer peripheral portion of the holder, is part from the outer peripheral portion of the holder, and has a recessed shape. The methods enable the production of a large single-crystal diamond in a comparatively short time at low cost.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: June 15, 2010
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Yoshiaki Mokuno, Akiyoshi Chayahara, Yuji Horino, Naoji Fujimori
  • Publication number: 20100142577
    Abstract: A nitride semiconductor laser device includes an n-type AlGaN clad layer, a GaN layer, a first InGaN light guide layer, a light-emitting layer, a second InGaN light guide layer, a nitride semiconductor intermediate layer, a p-type AlGaN layer, and a p-type AlGaN clad layer stacked in this order on a nitride semiconductor substrate, wherein the n-type AlGaN clad layer has an Al composition ratio of 3-5% and a thickness of 1.8-2.5 ?m; the first and second InGaN light guide layers have an In composition ratio of 3-6%; the first light guide layer has a thickness of 120-160 nm and greater than that of the second light guide layer; and the p-type AlGaN layer is in contact with the p-type clad layer and has an Al composition ratio of 10-35% and greater than that of the p-type clad layer.
    Type: Application
    Filed: November 12, 2009
    Publication date: June 10, 2010
    Inventors: Yuhzoh Tsuda, Masataka Ohta, Yoshie Fujishiro
  • Patent number: 7682450
    Abstract: A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun-Seung Kang, Eun-Kuk Chung, Joon Kim, Jin-Hong Kim, Suk-Chul Bang
  • Patent number: 7678194
    Abstract: A method and apparatus for generating gas for a processing system is provided. In one embodiment, an apparatus for generating gas for a processing system includes a canister having at least one baffle disposed between two ports and containing a precursor material. The precursor material is adapted to produce a gas vapor when heated to a defined temperature at a defined pressure. The baffle forces a carrier gas to travel an extended mean path between the inlet and outlet ports. In another embodiment, an apparatus for generating gas includes a canister having a tube that directs a carrier gas flowing into the canister away from a precursor material disposed within the canister.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: March 16, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Seshadri Ganguli, Ling Chen, Vincent W. Ku
  • Patent number: 7674335
    Abstract: A method for minimizing particle generation during deposition of a graded Si1?xGex layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si1?xGex layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm2 on the substrate.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 9, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eugene A. Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
  • Publication number: 20100031877
    Abstract: In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.
    Type: Application
    Filed: September 27, 2007
    Publication date: February 11, 2010
    Applicant: II-VI INCORPORATED
    Inventors: Avinash Gupta, Utpal K. Chakrabarti, Jihong Chen, Edward Semenas, Ping Wu
  • Patent number: 7655090
    Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: February 2, 2010
    Assignee: The Regents of the University of California
    Inventors: Hugues Marchand, Brendan Jude Moran
  • Patent number: 7648577
    Abstract: A method of growing a p-type nitride semiconductor material by molecular beam epitaxy (MBE) uses bis(cyclopentadienyl)magnesium (Cp2Mg) as the source of magnesium dopant atoms. Ammonia gas is used as the nitrogen precursor for the MBE growth process. To grow p-type GaN, for example, by the method of the invention, gallium, ammonia and Cp2Mg are supplied to an MBE growth chamber; to grow p-type AlGaN, aluminum is additionally supplied to the growth chamber. The growth process of the invention produces a p-type carrier concentration, as measured by room temperature Hall effect measurements, of up to 2 1017 cm?3, without the need for any post-growth step of activating the dopant atoms.
    Type: Grant
    Filed: November 27, 2003
    Date of Patent: January 19, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart E. Hooper, Katherine L. Johnson, Valerie Bousquet, Jonathan Heffernan
  • Patent number: 7628855
    Abstract: Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: December 8, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Neal R. Rueger
  • Patent number: 7625448
    Abstract: The invention relates to a device for depositing especially crystalline layers on at least one especially crystalline substrate in a process chamber comprising a top and a vertically opposing heated bottom for receiving the substrates. A gas-admittance body forming vertically superimposed gas-admittance regions is used to separately introduce at least one first and one second gaseous starting material, said starting materials flowing through the process chamber with a carrier gas in the horizontal direction. The gas flow homogenises in an admittance region directly adjacent to the gas-admittance body, and the starting materials are at least partially decomposed, forming decomposition products which are deposited on the substrates in a growth region adjacent to the admittance region, under continuous depletion of the gas flow. An additional gas-admittance region of the gas-admittance body is essential for one of the two starting materials, in order to reduce the horizontal extension of the admittance region.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: December 1, 2009
    Assignee: Aixtron AG
    Inventors: Martin Dauelsberg, Martin Conor, Gerhard Karl Strauch, Johannes Kaeppeler
  • Patent number: 7625447
    Abstract: SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10?6 to 10?8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once.
    Type: Grant
    Filed: March 18, 2004
    Date of Patent: December 1, 2009
    Assignee: Japan Science and Technology Agency
    Inventors: Jun Suda, Hiroyuki Matsunami, Norio Onojima
  • Patent number: 7615203
    Abstract: A single crystal diamond grown by vapor phase synthesis, wherein when one main surface is irradiated with a linearly polarized light considered to be the synthesis of two mutually perpendicular linearly polarized light beams, the phase difference between the two mutually perpendicular linearly polarized light beams exiting another main surface on the opposite side is, at a maximum, not more than 50 nm per 100 ?m of crystal thickness over the entire crystal. This single crystal diamond is of a large size and high quality unattainable up to now, and has characteristics that are extremely desirable in semiconductor device substrates and are applied to optical components of which low strain is required.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: November 10, 2009
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Yamamoto, Kiichi Meguro, Takahiro Imai
  • Patent number: 7611579
    Abstract: A system for synthesizing nanostructures using chemical vapor deposition (CVD) is provided. The system includes a housing, a porous substrate within the housing, and on a downstream surface of the substrate, a plurality of catalyst particles from which nanostructures can be synthesized upon interaction with a reaction gas moving through the porous substrate. Electrodes may be provided to generate an electric field to support the nanostructures during growth. A method for synthesizing extended length nanostructures is also provided. The nanostructures are useful as heat conductors, heat sinks, windings for electric motors, solenoid, transformers, for making fabric, protective armor, as well as other applications.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: November 3, 2009
    Assignee: Nanocomp Technologies, Inc.
    Inventors: David Lashmore, Joseph J. Brown, Robert C. Dean, Jr., Peter L. Antoinette
  • Patent number: 7608539
    Abstract: A method and an apparatus for executing efficient and cost-effective Atomic Layer Deposition (ALD) at low temperatures are presented. ALD films such as oxides and nitrides are produced at low temperatures under controllable and mild oxidizing conditions over substrates and devices that are moisture- and oxygen-sensitive. ALD films, such as oxides, nitrides, semiconductors and metals, are efficiently and cost-effectively deposited from conventional metal precursors and activated nonmetal sources. Additionally, substrate preparation methods for optimized ALD are disclosed.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 27, 2009
    Assignee: Sundew Technologies, LLC
    Inventor: Ofer Sneh