With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/94)
-
Patent number: 7438759Abstract: An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.Type: GrantFiled: November 1, 2005Date of Patent: October 21, 2008Assignee: Sharp Laboratories of America, Inc.Inventors: Fengyan Zhang, Robert A. Barrowcliff, Jong-Jan Lee, Sheng Teng Hsu
-
Publication number: 20080223287Abstract: A method of forming a copper alloy seed layer comprises providing a substrate in a reactor, performing a first ALD process to fabricate an alloy metal layer on the substrate, wherein the first ALD process uses an alloy metal precursor selected from a group of specific alloy metal precursors, performing a second ALD process to fabricate a copper metal layer on the alloy metal layer, wherein the second ALD process uses a copper metal precursor selected from a group of specific copper metal precursors, and annealing the alloy metal layer and the copper metal layer to form a graded Cu-alloy layer.Type: ApplicationFiled: March 15, 2007Publication date: September 18, 2008Inventors: Adrien R. Lavoie, Juan E. Dominguez
-
Patent number: 7425237Abstract: The deposition of material (3) on a growth area (4) may be highly temperature-sensitive. In order to reduce temperature inhomogeneities on the growth area (4) of a substrate wafer (1), a thermal radiation absorption layer (2) is applied on a rear side (5) of the substrate wafer (1) lying opposite to the growth area (4). The thermal radiation absorption layer (2) exhibits good radiation absorption in the spectral range of a heating source. Since the deposition of semiconductor materials, in particular AllnGaN, may lead to (depending on the deposition temperature) different emission wavelengths of the deposited material, the use of a thermal radiation absorption layer (2) may produce a narrower emission wavelength distribution of the deposited material (3).Type: GrantFiled: October 30, 2003Date of Patent: September 16, 2008Assignee: Osram Opto Semiconductor GmbHInventors: Stefan Bader, Hans-Jurgen Lugauer, Volker Haerle, Berthold Hahn
-
Patent number: 7410539Abstract: The template type substrate is used for opto-electric or electrical devices and comprises A) a layer of bulk mono-crystal nitride containing at least one element of alkali metals (Group I, IUPAC 1989) and B) a layer of nitride grown by means of vapor phase epitaxy growth wherein the layer A) and the layer B) are combined at non N-polar face of the layer A) and N-polar face of the layer B). Therefore, the template type substrate has a good dislocation density and a good value of FWHM of the X-ray rocking curve from (0002) plane less than 80, so that the resulting template type substrate is very useful for the epitaxy substrate from gaseous phase such as MOCVD, MBE and HVPE, resulting in possibility of making good opto-electric devices such as Laser Diode and large-output LED and good electric devices such as MOSFET.Type: GrantFiled: December 11, 2003Date of Patent: August 12, 2008Assignees: Ammono Sp. z o.o., Nichia CorporationInventors: Robert Dwilinski, Roman Doradzinski, Jerzy Garczynski, Leszek Sierzputowski, Yasuo Kanbara
-
Patent number: 7407548Abstract: The present invention relates to a method of manufacturing a wafer comprising a single crystalline bulk substrate of a first material and at least one epitaxial layer of a second material which has a lattice different from the lattice of the first material. The present invention provides a method for manufacturing a wafer in which a layer which is lattice-mismatched with the substrate can be grown on the substrate with a high effectiveness and high quality at a low cost. A roughening step is included for roughening the surface of the bulk substrate and a growing step is included for growing the second material on the rough surface with a reduced number of threading dislocations and an enhanced strain relaxation compared to a second material that is epitaxially grown on a polished surface.Type: GrantFiled: August 11, 2004Date of Patent: August 5, 2008Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Konstantin Bourdelle, Ian Cayrefourcq, Mark Kennard
-
Patent number: 7396409Abstract: By uniformly forming an indefinite number of microscopic acicular crystals on a surface of a silicon substrate so as to be perpendicular to the surface of the substrate by plasma CVD method using a catalyst, it is possible to reliably, homogeneously and massively form an ultramicroscopic acicular silicon crystal having a substantial cone shape tapered so as to have a radius of curvature of not less than 1 nm to no more than 20 nm at its tip end and having a diameter of bottom surface of not less than 10 nm, and a height equivalent to or more than the diameter of bottom surface, at a desired location.Type: GrantFiled: September 4, 2003Date of Patent: July 8, 2008Assignees: Covalent Materials Corporation, Techno Network Shikoku Co., Ltd.Inventors: Akitmitsu Hatta, Hiroaki Yoshimura, Keiichi Ishimoto, Hiroaki Kanakusa, Shinichi Kawagoe
-
Patent number: 7387678Abstract: A GaN substrate comprises a GaN single crystal substrate, an AlxGa1-xN intermediate layer (0<x?1) epitaxially grown on the substrate, and an GaN epitaxial layer grown on the intermediate layer. The intermediate layer is made of AlGaN and this AlGaN grows over the entire surface of the substrate with contaminants thereon and high dislocation regions therein. Thus, the intermediate layer is normally grown on the substrate, and a growth surface of the intermediate layer can be made flat. Since the growth surface is flat, a growth surface of the GaN epitaxial layer epitaxially grown on the intermediate layer is also flat.Type: GrantFiled: June 25, 2004Date of Patent: June 17, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Eiryo Takasuka, Masahiro Nakayama, Masaki Ueno, Kouhei Miura, Takashi Kyono
-
Patent number: 7384479Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layer with a thickness of about 2 molecular layers or less.Type: GrantFiled: March 16, 2005Date of Patent: June 10, 2008Assignee: Ricoh Company, Ltd.Inventors: Naoto Jikutani, Shunichi Sato, Takashi Takahashi
-
Patent number: 7377978Abstract: It is to provide a method for producing a silicon epitaxial wafer, which can prevent fine unevenness from occurring on a rear main surface of a silicon epitaxial wafer and which suppresses the haze level of the whole rear main surface to 50 ppm or less. A method for producing a silicon epitaxial wafer, includes: a hydrogen heat treatment step of arranging within a reactor a susceptor capable of mounting a silicon single crystal substrate and subjecting the silicon single crystal substrate mounted on the susceptor to heat treatment in a hydrogen atmosphere, and a vapor phase epitaxy step of epitaxially growing a silicon epitaxial layer after the hydrogen heat treatment step, wherein the silicon single crystal substrate is separated from the susceptor during the hydrogen heat treatment step, and the silicon single crystal substrate is mounted on the susceptor during the vapor phase epitaxy step.Type: GrantFiled: June 21, 2004Date of Patent: May 27, 2008Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Tsuyoshi Nishizawa
-
Patent number: 7368014Abstract: A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer thick over the substrate. At a second temperature different from the first temperature, the first layer may be contacted with a second precursor, chemisorbing a second layer at least one monolayer thick on the first layer. Temperature may be altered by adding or removing heat with a thermoelectric heat pump. The altering the substrate temperature may occur from the first to the second temperature. The second layer may be reacted with the first layer by heating to a third temperature higher than the second temperature. A deposition method may also include atomic layer depositing a first specie of a substrate approximately at an optimum temperature for the first specie deposition.Type: GrantFiled: August 9, 2001Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventor: Trung Tri Doan
-
Patent number: 7361222Abstract: A method and a device to grow from the vapor phase, a single crystal of either SiC, a group III-nitride, or alloys thereof, at a growth rate and for a period of time sufficient to produce a crystal of preferably several centimeters length. The diameter of the growing crystal may be controlled. To prevent the formation of undesirable polycrystalline deposits on surfaces in the downstream vicinity of the single crystal growth area, the local supersaturation of at least one component of the material grown is lowered by introducing a separate gas flow comprising at least one halogen element or a combination of said halogen and hydrogen species.Type: GrantFiled: April 23, 2004Date of Patent: April 22, 2008Assignee: Norstel ABInventors: Erik Janzén, Peter Råback, Alexandre Ellison
-
Patent number: 7357837Abstract: The method of making a GaN single crystal substrate comprises a mask layer forming step of forming on a GaAs substrate 2 a mask layer 8 having a plurality of opening windows 10 disposed separate from each other; and an epitaxial layer growing step of growing on the mask layer 8 an epitaxial layer 12 made of GaN.Type: GrantFiled: October 24, 2003Date of Patent: April 15, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Naoki Matsumoto
-
Patent number: 7354477Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: September 9, 2004Date of Patent: April 8, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
-
Patent number: 7351286Abstract: A method of producing a high quality bulk single crystal of silicon carbide in a seeded growth system is disclosed. The method includes positioning the seed crystal in a crucible while exerting minimal torsional forces on the seed crystal to thereby prevent torsional forces from warping or bowing the seed crystal in a manner that that would otherwise encourage sublimation from the rear of the seed crystal or undesired thermal differences across the seed crystal.Type: GrantFiled: October 12, 2005Date of Patent: April 1, 2008Assignee: Cree, Inc.Inventors: Robert Tyler Leonard, Adrian Powell, Stephan Georg Mueller, Valeri F. Tsvetkov
-
Patent number: 7341628Abstract: Gallium Nitride layers grown as single crystals by epitaxy such as Hydride Vapor Phase Epitaxy (HVPE) contain large numbers of crystal defects such as hexagonal pits, which limit the yield and performance of opto- and electronic devices. In this method, the Gallium Nitride layer is first coated with an Aluminum layer of approximate thickness of 0.1 microns. Next, Nitrogen is ion implanted through the Aluminum layer so as to occupy mostly the top 0.1 to 0.5 microns of the Gallium Nitride layer. Finally, through a pulsed directed energy beam such as electron or photons, with a fluence of approximately 1 Joule/cm2 the top approximately 0.5 microns are converted to a single crystal with reduced defect density.Type: GrantFiled: December 16, 2004Date of Patent: March 11, 2008Inventor: Andreas A. Melas
-
Patent number: 7338554Abstract: The invention relates to a process for synthesizing nanorods of a carbide of one metal M1 on a substrate, which comprises: a) the deposition, on the substrate, of a layer of nanocrystals of oxide of the metal M1 and nanocrystals of oxide of at least one metal M2 different from metal M1, the M1 metal oxide nanocrystals being dispersed within this layer; b) the reduction of the M1 and M2 metal oxide nanocrystals into corresponding metal nanocrystals; and c) the selective growth of the M1 metal nanocrystals. The invention also relates to a process for growing nanorods of a carbide of one metal M1 on a substrate from nanocrystals of this metal, to the substrates thus obtained and to their applications: fabrication of Microsystems provided with chemical or biological functionalities, in particular the fabrication of biosensors; electron emission sources, for example for flat television or computer screens; etc.Type: GrantFiled: December 4, 2003Date of Patent: March 4, 2008Assignee: Commissariat a L'Energie AtomiqueInventors: Marc Delaunay, Francoise Vinet
-
Patent number: 7335255Abstract: The present invention provides a method for removing a metal element effectively from a crystalline semiconductor film obtained with the use of the metal element, without increasing the number of processes. In the present invention, an amorphous semiconductor film is formed on an insulating surface, a metal element for promoting crystallization is added to the amorphous semiconductor film, the amorphous semiconductor film is heated to form a crystallized semiconductor film, a continuous wave laser beam is irradiated to the crystallized semiconductor film, and an upper portion of the crystallized semiconductor film is removed.Type: GrantFiled: November 26, 2003Date of Patent: February 26, 2008Assignee: Semiconductor Energy Laboratory, Co., Ltd.Inventors: Shinji Maekawa, Hidekazu Miyairi
-
Patent number: 7332030Abstract: Process for the treatment of a component, at least one zone to be treated of which located in the depth of this component at a certain distance from the surface thereof, has at least one property that can be modified when this zone is subjected to a thermal energy density above a specified treatment level, comprises: placing the component to be treated at a thermal energy level below the specified level; and subjecting, through its aforementioned surface, for a specified time and in the form of at least one pulse, the component to a power flux generated by a particle emission unit, this emission unit being regulated so as to produce a thermal energy density that is concentrated on or has a localized maximum in the zone to be treated and reaching, in at least part of this zone, a level above the specified treatment level.Type: GrantFiled: January 15, 2003Date of Patent: February 19, 2008Inventor: Michel Bruel
-
Patent number: 7329317Abstract: The present invention is to produce a silicon crystal wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so that the boron concentration in the silicon crystal is no less than 1×1018 atoms/cm3 and the growth condition V/G falls within the epitaxial defect-free region ?2 whose lower limit line LN1 is the line indicating that the growth rate V gradually drops as the boron concentration increases. A silicon wafer is also produced wherein the boron concentration in the silicon crystal and the growth condition V/G are controlled so as to include at least the epitaxial defect region ?1, and both the heat treatment condition and the oxygen concentration of the silicon crystal are controlled so that no OSF nuclei grow to OSFs.Type: GrantFiled: October 31, 2003Date of Patent: February 12, 2008Assignee: Komatsu Denshi Kinzoku Kabushiki KaishaInventors: Susumu Maeda, Hiroshi Inagaki, Shigeki Kawashima, Shoei Kurosaka, Kozo Nakamura
-
Patent number: 7326293Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.Type: GrantFiled: March 25, 2005Date of Patent: February 5, 2008Assignee: Zyvex Labs, LLCInventors: John N. Randall, Jingping Peng, Jun-Fu Liu, George D. Skidmore, Christof Baur, Richard E. Stallcup, II, Robert J. Folaron
-
Patent number: 7311777Abstract: A process for manufacturing a quartz crystal element consists of the steps of producing plural quartz layers on a surface of a crystalline substrate having a lattice constant differing from that of quartz crystal, in which each of the quartz layers consists of a crystalline phase and an amorphous phase, and percentage of the crystalline phase in the quartz layer farther from the substrate is larger than percentage of the crystalline phase in the quartz layer adjacent to the substrate; and producing an epitaxially grown quartz crystal film on the surface of the quartz layer farther from the substrate by a reaction between silicon alkoxide and oxygen.Type: GrantFiled: August 26, 2004Date of Patent: December 25, 2007Assignee: Humo Laboratory, LtdInventors: Naoyuki Takahashi, Takato Nakamura, Satoshi Nonaka, Yoshinori Kubo, Yoichi Shinriki, Katsumi Tamanuki
-
Patent number: 7309394Abstract: An object is to provide an ultraviolet light-emitting device in which a p-type semiconductor which has high conductivity and an emission peak in ultraviolet region, and emits light efficiently is used. The p-type semiconductor is prepared by supplying a p-type impurity raw material at the same time or after starting supply of predetermined types of crystal raw materials, besides before starting supply of other types of crystal raw materials than the predetermined types of crystal raw materials in one cycle wherein all the types of crystal raw materials of the plural types of crystal raw materials are supplied in one time each in case of making crystal growth by supplying alternately the plural types of crystal raw materials in a pulsed manner.Type: GrantFiled: July 25, 2003Date of Patent: December 18, 2007Assignee: RikenInventors: Hideki Hirayama, Sohachi Iwai, Yoshinobu Aoyagi
-
Patent number: 7303631Abstract: Patterned zinc-oxide nanostructures are grown without using a metal catalyst by forming a seed layer of polycrystalline zinc oxide on a surface of a substrate. The seed layer can be formed by an atomic layer deposition technique. The seed layer is patterned, such as by etching, and growth of at least one zinc-oxide nanostructure is induced substantially over the patterned seed layer by, for example, exposing the patterned seed layer to zinc vapor in the presence of a trace amount of oxygen. The seed layer can alternatively be formed by using a spin-on technique, such as a metal organic deposition technique, a spray pyrolisis technique, an RF sputtering technique or by oxidation of a zinc thin film layer formed on the substrate.Type: GrantFiled: October 29, 2004Date of Patent: December 4, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: John F. Conley, Jr., Lisa H. Stecker
-
Patent number: 7303628Abstract: Disclosed herein are nanostructures comprising distinct dots and rods coupled through potential barriers of tuneable height and width, and arranged in three dimensional space at well defined angles and distances. Such control allows investigation of potential applications ranging from quantum information processing to artificial photosynthesis.Type: GrantFiled: July 7, 2004Date of Patent: December 4, 2007Assignee: The Regents of the University of CaliforniaInventors: A. Paul Alivisatos, Delia Milliron, Liberato Manna, Steven M. Hughes
-
Patent number: 7303630Abstract: Dotted seeds are implanted in a regular pattern upon an undersubstrate. A GaN crystal is grown on the seed implanted undersubstrate by a facet growth method. The facet growth makes facet pits above the seeds. The facets assemble dislocations from neighboring regions, accumulate the dislocations into pit bottoms, and make closed defect accumulating regions (H) on the seeds. The polycrystalline or slanting orientation single crystal closed defect accumulating regions (H) induce microcracks due to thermal expansion anisotropy. The best one is orientation-inversion single crystal closed defect accumulating regions (H). At an early stage, orientation-inverse protrusions are induced on tall facets and unified with each other above the seeds. Orientation-inverse crystals growing on the unified protrusions become the orientation-inverse single crystal closed defect accumulating regions (H).Type: GrantFiled: September 3, 2004Date of Patent: December 4, 2007Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Takuji Okahisa, Ryu Hirota, Seiji Nakahata, Koji Uematsu
-
Patent number: 7294202Abstract: Process for fabricating self-assembled nanoparticles on buffer layers without mask making and allowing for any degree of lattice mismatch; that is, binary, ternary or quaternary nanoparticles comprising Groups III-V, II-VI or IV-VI. The process includes a first step of applying a buffer layer, a second step of turning on the purge gas to modulate the first reactant to the lower first flow rate, then the second reactant is supplied to the buffer layer to form a metal-rich island on the buffer layer, and a third step of turning on purge gas again to modulate the first reactant to the higher second flow rate onto the buffer layer. On the metal-rich island is formed the nanoparticles of the binary, ternary or quaternary III-V, II-VI and IV-IV semiconductor material. This is then recrystallized under the first reactant flow at high temperature forming high quality nanoparticles.Type: GrantFiled: December 6, 2004Date of Patent: November 13, 2007Assignee: National Chiao Tung UniversityInventors: Wei-Kuo Chen, Ming-Chih Lee, Wu-Ching Chou, Wen-Hsiung Chen, Wen-Cheng Ke
-
Patent number: 7294201Abstract: A crystal substrate and a crystal film of a III-V compound of the nitride system which are manufactured easily and have few dislocations as well as a method of manufacturing a crystal and a method of manufacturing a device with the use thereof are disclosed. On a basal body, formed in order are a base crystal layer of, for example, gallium nitride (GaN), a first mask pattern of, for example, silicon dioxide (SiO2), an intermediate crystal layer of, for example, gallium nitride, a second mask pattern of, for example, silicon dioxide, and a top crystal layer of, for example, gallium nitride. The first and second mask patterns have stripes arranged at least in one direction at unequally spaced intervals. The stripes are different in pitch from pattern to pattern. Thus, the mask patterns at least partly overlie one another in the direction of the thickness of the crystal layers.Type: GrantFiled: November 30, 2000Date of Patent: November 13, 2007Assignee: Sony CorporationInventor: Etsuo Morita
-
Patent number: 7273525Abstract: A method of forming a phosphorus- and/or boron-containing silica layer, such as a PSG, BSG, or BPSG layer, on a substrate, such as a semiconductor substrate or substrate assembly.Type: GrantFiled: May 13, 2003Date of Patent: September 25, 2007Assignee: Micron Technology, Inc.Inventor: Brian A Vaartstra
-
Publication number: 20070209578Abstract: There is disclosed a method for producing a substrate for single crystal diamond growth, comprising at least a step of preliminarily subjecting a substrate before single crystal diamond growth to a bias treatment for forming a diamond nucleus thereon by a direct-current discharge in which an electrode in a substrate side is a cathode, and wherein in the treatment, at least, a temperature of the substrate from 40 sec after an initiation of the bias treatment to an end of the bias treatment is held in a range of 800° C.±60° C. There can be provided a method for producing a substrate for single crystal diamond growth, by which a single crystal diamond can be grown more certainly.Type: ApplicationFiled: March 2, 2007Publication date: September 13, 2007Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Hitoshi Noguchi
-
Patent number: 7261777Abstract: A method for fabricating an epitaxial substrate. The technique includes providing a crystalline or mono-crystalline base substrate, implanting atomic species into a front face of the base substrate to a controlled mean implantation depth to form a zone of weakness within the base substrate that defines a sub-layer, and growing a stiffening layer on a front face of the base substrate by using a thermal treatment in a first temperature range. The stiffening layer has a thickness sufficient to form an epitaxial substrate. In addition, the method includes detaching the stiffening layer and the sub-layer from the base substrate by using a thermal treatment in a second temperature range higher than the first temperature range. An epitaxial substrate and a remainder of the base substrate are obtained. The epitaxial substrate is suitable for use in growing high quality homoepitaxial or heteroepitaxial films thereon.Type: GrantFiled: June 1, 2004Date of Patent: August 28, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Bruce Faure
-
Patent number: 7258742Abstract: A method of manufacturing KNbO3 single crystal thin film having single-phase high quality and excellent morphology on each of single crystal substrates. A surface acoustic wave element, frequency filter, frequency oscillator, electronics circuit, and electronic device employ the thin film manufactured by the method, and have high k2, and are wideband, reduced in size and economical in power consumption. A plasma plume containing K, Nb, and O in the range 0.5?x?xE is supplied to a substrate, where x is a mole ratio of niobium (Nb) to potassium (K) in KxNb1?xOy, and xE is a mole composition ratio at the eutectic point for KNbO3 and 3K2O.Nb2O5 under a predetermined oxygen partial pressure. Maintaining the temperature Ts of the substrate in the range TE?Ts?Tm where TE represents the temperature at the eutectic point and Tm represents a complete melting temperature, the KNbO3 single crystal is precipitated from the KxNb1?xOy deposited on the substrate.Type: GrantFiled: August 11, 2004Date of Patent: August 21, 2007Assignee: Seiko Epson CorporationInventors: Takamitsu Higuchi, Setsuya Iwashita, Hiromu Miyazawa
-
Patent number: 7255745Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 ?, a length in the range of 1000 ? to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 ?.Type: GrantFiled: October 21, 2004Date of Patent: August 14, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Fengyan Zhang, Robert A. Barrowcliff, Sheng Teng Hsu
-
Patent number: 7235129Abstract: A method for forming an array of zinc oxide nanowires on a substrate is disclosed, which includes forming a crystal phase adjusting buffer on the surface of the substrate and growing 1D zinc oxide nanowires on the buffer by zinc vapor deposition, which are normal to the surface of the substrate. The crystal phase adjusting buffer includes, for example, nitride and oxide layers on a silicon substrate, or a gallium nitride epitaxial layer on a sapphire substrate, and is used as a growth buffer layer for the zinc oxide nanowires. The zinc vapor phase deposition includes forming a zinc oxide layer on the crystal phase adjusting buffer and forming vertical zinc oxide nanowires on the zinc oxide layer.Type: GrantFiled: April 13, 2004Date of Patent: June 26, 2007Assignee: Industrial Technology Research InstituteInventors: I-Cherng Chen, Yung-Kuan Tseng, Chor-Jye Huang
-
Patent number: 7232488Abstract: The present invention relates to a method of fabrication of a substrate for an epitaxial growth. A relaxed epitaxial base layer is obtained on an auxiliary substrate. The invention allows the fabrication of substrates with a more efficient epitaxial growth of a material with a desired lattice parameter on another material with a different lattice parameter. The material can be grown with a high thermodynamic and crystallographic stability. At least a part of the epitaxial base layer is transferred onto a carrier substrate, forming a base substrate, and growing the material of the epitaxial base layer is further grown on the carrier substrate.Type: GrantFiled: April 20, 2004Date of Patent: June 19, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Takeshi Akatsu, Cecile Aulnette, Bruno Ghyselen
-
Patent number: 7226509Abstract: A method for fabricating a carrier substrate. The technique includes providing a crystalline or mono-crystalline base substrate, growing a stiffening layer on a front face of the base substrate at a thickness sufficient to form a carrier substrate for subsequent processing, and detaching the stiffening layer from the base substrate to obtain the carrier substrate and a remainder of the base substrate. The carrier substrate is suitable for use in growing high quality homo-epitaxial or hetero-epitaxial films thereon.Type: GrantFiled: November 18, 2003Date of Patent: June 5, 2007Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Bruce Faure
-
Patent number: 7227066Abstract: Methods for passivating crystalline grains in an active layer for an optoelectronic device and optoelectronic devices having active layers with passivated crystalline grains are disclosed. Crystalline grains of an active layer material and/or window layer material are formed within the nanotubes of an insulating nanotube template. The dimensions of the nanotubes correspond to the dimensions of a crystalline grain formed by the deposition technique used to form the grains. A majority of the surface area of these grains is in contact with the wall of the nanotube template rather than with other grains.Type: GrantFiled: April 21, 2004Date of Patent: June 5, 2007Assignee: Nanosolar, Inc.Inventors: Martin R. Roscheisen, Brian M. Sager
-
Patent number: 7217323Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: setting a substrate as a seed crystal in a reactive chamber; introducing a raw material gas into the reactive chamber; growing a silicon carbide single crystal from the substrate; heating the gas at an upstream side from the substrate in a gas flow path; keeping a temperature of the substrate at a predetermined temperature lower than the gas so that the single crystal is grown from the substrate; heating a part of the gas, which is a non-reacted raw material gas and does not contribute to crystal growth, after passing through the substrate; and absorbing a non-reacted raw material gas component in the non-reacted raw material gas with an absorber.Type: GrantFiled: April 1, 2004Date of Patent: May 15, 2007Assignee: Denso CorporationInventors: Naohiro Sugiyama, Yasuo Kitou, Emi Makino, Kazukuni Hara, Kouki Futatsuyama, Atsuto Okamoto
-
Patent number: 7208044Abstract: This invention disclosure describes methods for the fabrication metal oxide films on surfaces by topotactic anion exchange, and laminate structures enabled by the method. A precursor metal-nonmetal film is deposited on the surface, and is subsequently oxidized via topotactic anion exchange to yield a topotactic metal-oxide product film. The structures include a metal-oxide layer(s) and/or a metal-nonmetal layer(s).Type: GrantFiled: November 24, 2004Date of Patent: April 24, 2007Inventor: Mark A. Zurbuchen
-
Patent number: 7192483Abstract: The present invention relates to a method for diamond coating of substrates in which the substrate is exposed in a vacuum atmosphere to a reactive gas mixture excited by means of a plasma discharge, the plasma discharge comprising a plasma beam (14) in an evacuated receiver (16) that is formed between a cathode chamber (1) and an anode (2), and the reactive gas mixture comprising a reactive gas and a working gas, the reactive gas in (9) and the working gas in (8) and/or (9) introduced into the receiver, and the receiver (16) is evacuated by a pump arrangement (15), and the hydrogen concentration of the reactive gas mixture being 0–45 vol. %.Type: GrantFiled: October 7, 2002Date of Patent: March 20, 2007Assignee: Unaxis Balzers AktiengesellschaftInventors: David Franz, Johann Karner
-
Patent number: 7189287Abstract: Formation of a layer of material on a surface by atomic layer deposition methods and systems includes using electron bombardment of the chemisorbed precursor.Type: GrantFiled: June 29, 2004Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventor: Neal R. Rueger
-
Patent number: 7175709Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.Type: GrantFiled: May 17, 2004Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pang-Yen Tsai, Liang-Gi Yao, Chun-Chieh Lin, Wen-Chin Lee, Shih-Chang Chen
-
Patent number: 7172655Abstract: A method of producing a single crystal CVD diamond of a desired color which includes the steps of providing single crystal CVD diamond which is colored and heat treating the diamond under conditions suitable to produce the desired color. Colors which may be produced are, for example, in the pink-green range.Type: GrantFiled: September 5, 2003Date of Patent: February 6, 2007Inventors: Daniel James Twitchen, Philip Maurice Martineau, Geoffrey Alan Scarsbrook
-
Patent number: 7169227Abstract: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN layer to make the free-standing, single crystal AlGaN wafer. Forming the single crystal AlGaN layer may comprise depositing AlGaN by vapor phase epitaxy (VPE) using aluminum and gallium halide reactant gases and a nitrogen-containing reactant gas. The growth of the AlGaN layer using VPE provides commercially acceptable rapid growth rates. In addition, the AlGaN layer can be devoid of carbon throughout. Because the AlGaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm?2.Type: GrantFiled: March 25, 2003Date of Patent: January 30, 2007Assignee: Crystal Photonics, IncorporatedInventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou, David W. Hill
-
Patent number: 7160529Abstract: Novel uses of diamondoid-containing materials in the field of microelectronics are disclosed. Embodiments include, but are not limited to, thermally conductive films in integrated circuit packaging, low-k dielectric layers in integrated circuit multilevel interconnects, thermally conductive adhesive films, thermally conductive films in thermoelectric cooling devices, passivation films for integrated circuit devices (ICs), and field emission cathodes. The diamondoids employed in the present invention may be selected from lower diamondoids, as well as the newly provided higher diamondoids, including substituted and unsubstituted diamondoids. The higher diamondoids include tetramantane, pentamantane, hexamantane, heptamantane, octamantane, nonamantane, decamantane, and undecamantane.Type: GrantFiled: February 24, 2004Date of Patent: January 9, 2007Assignee: Chevron U.S.A. Inc.Inventors: Jeremy E. Dahl, Robert M. Carlson, Shenggao Liu
-
Patent number: 7161148Abstract: New designs of electron devices such as scanning probes and field emitters based on tip structures are proposed. The tips are prepared from whiskers that are grown from the vapor phase by the vapor-liquid-solid technology. Some new designs for preparation of field-emitters and of probes for magnetic, electrostatic, morphological, etc, investigations based on the specific technology are proposed. New designs for preparation of multilever probes are proposed, too.Type: GrantFiled: May 31, 2000Date of Patent: January 9, 2007Assignee: Crystals and Technologies, Ltd.Inventors: Evgeny Invievich Givargizov, Michail Evgenievich Givargizov
-
Patent number: 7150788Abstract: A method of adjusting the in-plane lattice constant of a substrate and an in-plane lattice constant adjusted substrate are provided. A crystalline substrate (1) made of SrTiO3 is formed at a first preestablished temperature thereon with a first epitaxial thin film (2) made of a first material, e. g., BaTiO3, and then on the first epitaxial thin film (2) with a second epitaxial thin film (6) made of a second material, e. g., BaxSr1?xTiO3 (where 0<x<1), that contains a substance of the first material and another substance which together therewith is capable of forming a solid solution in a preestablished component ratio. Thereafter, the substrate is heat-treated at a second preselected temperature. Heat treated at the second preestablished temperature, the substrate has dislocations (4) introduced therein and the second epitaxial thin film (6) has its lattice constant relaxed to a value close to the lattice constant of bulk crystal of the second material.Type: GrantFiled: August 21, 2002Date of Patent: December 19, 2006Assignee: Japan Science and Technology AgencyInventors: Hideomi Koinuma, Masashi Kawasaki, Tomoteru Fukumura, Kota Terai
-
Patent number: 7141116Abstract: Provided are improved methods for forming silicon films, particularly single-crystal silicon films from amorphous silicon films in which a single-crystal silicon substrate is prepared by removing any native oxide, typically using an aqueous HF solution, and placed in a reaction chamber. The substrate is then heated from about 350° C. to a first deposition temperature under a first ambient to induce single-crystal epitaxial silicon deposition primarily on exposed silicon surfaces. The substrate is then heated to a second deposition temperature under a second ambient that will maintain the single-crystal epitaxial silicon deposition on exposed single-crystal silicon while inducing amorphous epitaxial silicon deposition on insulating surfaces. The amorphous epitaxial silicon can then be converted to single-crystal silicon using a solid phase epitaxy process to form a thin, high quality silicon layer.Type: GrantFiled: April 1, 2005Date of Patent: November 28, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Yong Hoon Son, Jae Young Park, Cha Dong Yeo, Jong Wook Lee, Yu Gyun Shin
-
Patent number: 7135072Abstract: Methods for producing silicon carbide crystals, seed crystal holders and seed crystal for use in producing silicon carbide crystals and silicon carbide crystals are provided. Silicon carbide crystals are produced by forcing nucleation sites of a silicon carbide seed crystal to a predefined pattern and growing silicon carbide utilizing physical vapor transport (PVT) so as to provide selective preferential growth of silicon carbide corresponding to the predefined pattern. Seed holders and seed crystals are provided for such methods. Silicon carbide crystals having regions of higher and lower defect density are also provided.Type: GrantFiled: January 13, 2004Date of Patent: November 14, 2006Assignee: Cree, Inc.Inventor: Stephan Mueller
-
Patent number: 7135074Abstract: A method for manufacturing a silicon carbide single crystal includes the steps of: preparing a seed crystal with a screw dislocation generation region; and growing the single crystal on a growth surface of the seed crystal. The generation region occupies equal to or smaller than 50% of the growth surface, which has an offset angle equal to or smaller than 60 degrees. The screw dislocation density in the single crystal generated from the generation region is higher than that in the other region. The single crystal includes a flat C-surface facet disposed on a growing surface of the single crystal. The C-surface facet overlaps at least one of parts of the growing surface provided by projecting the generation region in a direction perpendicular to the growth surface and in a direction parallel to a <0001> axis, respectively.Type: GrantFiled: August 5, 2004Date of Patent: November 14, 2006Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Denso CorporationInventors: Itaru Gunjishima, Daisuke Nakamura, Naohiro Sugiyama, Fusao Hirose
-
Patent number: 7128786Abstract: This invention relates to a method for depositing III-V semiconductor layers on a non III-V substrate especially a sapphire, silicon or silicon oxide substrate, or another substrate containing silicon. According to said method, a III-V layer, especially a buffer layer, is deposited on the substrate or on a III-V germination layer, in a process chamber of a reactor containing gaseous starting materials. In order to reduce the defect density of the overgrowth, a masking layer consisting of essentially amorphous material is deposited directly on the III-V germination layer or directly on the substrate, said masking layer partially covering of approximately partially covering the germination layer. The masking layer can be a quasi-monolayer and can consist of various materials.Type: GrantFiled: June 21, 2004Date of Patent: October 31, 2006Assignee: Aixtron AGInventors: Holger Jurgensen, Alois Krost, Armin Dadgar