With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/94)
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Patent number: 6743291Abstract: A process of fabricating a CMOS device comprised with super-steep retrograde (SSR), twin well regions, has been developed. The process features the use of two, selective epitaxial growth (SEG), procedures, with the first SEG procedure resulting in the growth of bottom silicon shapes in the PMOS, as well as in the NMOS region of the CMOS device. After implantation of the ions needed for the twin well regions, into the bottom silicon shapes, a second SEG procedure is employed resulting in growth of top silicon shapes on the underlying, implanted bottom silicon shapes. An anneal procedure then distributes the implanted ions resulting in an SSR N well region in the composite silicon shape located in the PMOS region, and resulting in an SSR P well region in the composite silicon shape located in the NMOS region of the CMOS device.Type: GrantFiled: July 9, 2002Date of Patent: June 1, 2004Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Chew Hoe Ang, Wenhe Lin, Jia Zhen Zheng
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Patent number: 6737339Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. The semiconductor device may include a doped buried layer located over a doped substrate and a doped epitaxial layer located over the doped buried layer. The semiconductor device may further include a first doped lattice matching layer located between the substrate and the buried layer and a second doped lattice matching layer located between the doped buried layer and the doped epitaxial layer.Type: GrantFiled: October 24, 2001Date of Patent: May 18, 2004Assignee: Agere Systems Inc.Inventors: Wen Lin, Charles W. Pearce
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Patent number: 6736894Abstract: To provide a method of manufacturing compound semiconductor single crystals such as silicon carbide and gallium nitride by epitaxial growth methods, that is capable of yielding compound single crystals of comparatively low planar defect density. The method of manufacturing compound single crystals in which two or more compound single crystalline layers identical to or differing from a single crystalline substrate are sequentially epitaxially grown on the surface of said substrate. At least a portion of said substrate surface has plural undulations extending in a single direction and second and subsequent epitaxial growth is conducted after the formation of plural undulations extending in a single direction in at least a portion of the surface of the compound single crystalline layer formed proximately.Type: GrantFiled: August 26, 2002Date of Patent: May 18, 2004Assignee: Hoya CorporationInventors: Takamitsu Kawahara, Hiroyuki Nagasawa, Kuniaki Yagi
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Patent number: 6709513Abstract: In a process for producing a substrate for use in a semiconductor element: a porous anodic alumina film having a great number of minute pores is formed on a surface of a base substrate; the surface of the base substrate is etched by using the porous anodic alumina film as a mask so as to form a great number of pits on the surface of the base substrate; the porous anodic alumina film is removed; and a GaN layer is formed on the surface of the base substrate by crystal growth.Type: GrantFiled: July 3, 2002Date of Patent: March 23, 2004Assignee: Fuji Photo Film Co., Ltd.Inventors: Toshiaki Fukunaga, Toshiaki Kuniyasu, Mitsugu Wada, Yoshinori Hotta
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Patent number: 6709512Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.Type: GrantFiled: August 29, 2001Date of Patent: March 23, 2004Assignee: Sony CorporationInventors: Hisayoshi Yamoto, Hideo Yamanaka
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Patent number: 6706114Abstract: Methods for producing silicon carbide crystals, seed crystal holders and seed crystal for use in producing silicon carbide crystals and silicon carbide crystals are provided. Silicon carbide crystals are produced by forcing nucleation sites of a silicon carbide seed crystal to a predefined pattern and growing silicon carbide utilizing physical vapor transport (PVT) so as to provide selective preferential growth of silicon carbide corresponding to the predefined pattern. Seed holders and seed crystals are provided for such methods. Silicon carbide crystals having regions of higher and lower defect density are also provided.Type: GrantFiled: May 21, 2001Date of Patent: March 16, 2004Assignee: Cree, Inc.Inventor: Stephan Mueller
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Patent number: 6695913Abstract: A light-emitting diode or laser diode comprises a sapphire substrate and, grown on the substrate, a GaN buffer layer, an n-doped GaN contact layer, an n-doped (AlGa)N cladding layer, a Zn-doped (InGa)N active layer, a p-doped (AlGa)N cladding layer and a p-doped GaN contact layer. Graded layers are introduced at the interfaces between the cladding layers and both the contact layers and the active layer. The constituency of each graded layer is graded from one side to the other of the layer such that the layer is lattice matched with the adjacent layer on each side with the result that the strain at the interfaces between the layers is reduced and the possibility of deleterious dislocations being introduced at the interfaces is minimised. By removing or reducing such dislocations, the efficiency of the operation of the device is increased.Type: GrantFiled: February 8, 2000Date of Patent: February 24, 2004Assignee: Sharp Kabushiki KaishaInventor: Geoffrey Duggan
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Patent number: 6689211Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium.Type: GrantFiled: June 22, 2000Date of Patent: February 10, 2004Assignee: Massachusetts Institute of TechnologyInventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein, Gianna Taraschi
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Publication number: 20040011281Abstract: This invention provides a method for manufacturing a semiconductor using a wafer carrier: the temperature of a wafer can be uniformed and the uniformity within the surface excels with few differences of the composition distribution; a crystal is grown by forming a plurality of grooves to uniform the temperature of the wafer surface by diffusing heat, at the bottom of a wafer pocket to mount a wafer on a wafer carrier inside a crystal growth apparatus chamber; and the groove depth is deeper at the peripheral part of the wafer than at the central part thereof while the groove density is higher at the peripheral part of the wafer than at the central part thereof.Type: ApplicationFiled: June 2, 2003Publication date: January 22, 2004Inventor: Koji Nakamura
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Patent number: 6673149Abstract: A method for the production of a crack-free epitiaxial film having a thickness greater than that which can be achieved by continuous epitaxial crystal growth. This epitaxial film can be used as is in a device, used as a substrate platform for further epitaxy, or separated from the initial substrate material and used as a free-standing substrate platform. The method utilizes a defect-rich initial layer that absorbs epitaxially derived stresses and another layer, which is not defect-rich, which planarizes the crystal growth front, if necessary and provides high quality epitaxial region near the surface.Type: GrantFiled: September 6, 2000Date of Patent: January 6, 2004Assignees: Matsushita Electric Industrial Co., LTD, CBL Technologies, Inc.Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
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Publication number: 20040000268Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1-xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1-xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium.Type: ApplicationFiled: June 25, 2003Publication date: January 1, 2004Applicant: Massachusetts Institute of TechnologyInventors: Kenneth C. Wu, Eugene A. Fitzgerald, Gianni Taraschi, Jeffrey T. Borenstein
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Patent number: 6666916Abstract: A mandrel for use in a diamond deposition process has surfaces with different diamond adhesion properties. According to one embodiment, a mandrel is provided and has first and second surfaces on which a diamond film is deposited, with the second surface forming a perimeter around the first surface. The first surface of the mandrel has a first diamond bonding strength which is less than a second diamond bonding strength of the second surface. In an embodiment for forming a cup-shaped diamond film, the mandrel is a titanium nitride (TiN) coated molybdenum (Mo) substrate having a stepped solid cylindrical shape with a central mesa having a side wall or flank. The side wall is etched near the top surface of the mesa to expose a molybdenum band and to form a second surface which bounds the TiN first surface.Type: GrantFiled: October 18, 2002Date of Patent: December 23, 2003Assignee: Saint-Gobain/Norton Industrial Ceramics CorporationInventors: Randy D. Fellbaum, Volker R. Ulbrich
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Patent number: 6656271Abstract: A process for manufacturing a semiconductor wafer which has superior suitability for mass production and reproducibility. The process comprises the steps of preparing a first member which has a monocrystalline semiconductor layer on a semiconductor substrate with a separation layer arranged therebetween with a semiconductor wafer as the raw material, transferring the monocrystalline semiconductor layer onto a second member which comprises a semiconductor wafer after separating the monocrystalline semiconductor layer through the separation layer, and smoothing the surface of the semiconductor substrate after the transferring step so as to be used as a semiconductor wafer for purposes other than forming the first and second members.Type: GrantFiled: December 3, 1999Date of Patent: December 2, 2003Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Kunio Watanabe, Tetsuya Shimada, Kazuaki Ohmi, Kiyofumi Sakaguchi
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Patent number: 6648966Abstract: A method for making a free-standing, single crystal, gallium nitride (GaN) wafer includes forming a single crystal GaN layer directly on a single crystal LiAlO2 substrate using a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal GaN layer to make the free-standing, single crystal GaN wafer. Forming the single crystal GaN layer may comprise depositing GaN by vapor phase epitaxy (VPE) using the gallium halide reactant gas and a nitrogen-containing reactant gas. Because gallium halide is used as a reactant gas rather than a metal organic reactant such as trimethygallium (TMG), the growth of the GaN layer can be performed using VPE which provides commercially acceptable rapid growth rates. In addition, the GaN layer is also devoid of carbon throughout. Because the GaN layer produced is high quality single crystal, it may have a defect density of less than about 107 cm−2.Type: GrantFiled: August 1, 2001Date of Patent: November 18, 2003Assignee: Crystal Photonics, IncorporatedInventors: Herbert Paul Maruska, John Joseph Gallagher, Mitch M. C. Chou
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Patent number: 6645295Abstract: A buffer layer 2 made of aluminum nitride (AlN) is formed on a substrate 1 and is formed into an island pattern such as a dot pattern, a striped pattern, or a grid pattern such that substrate-exposed portions are formed in a scattered manner. A group III nitride compound semiconductor 3 grows epitaxially on the buffer layer 2 in a longitudinal direction, and grows epitaxially on the substrate-exposed portions in a lateral direction. As a result, a group III nitride compound semiconductor 3 which has little or no feedthrough dislocations 4 is obtained. Because the region where the group III nitride compound semiconductor 3 grows epitaxially in a lateral direction, on region 32, has excellent crystallinity, forming a group III nitride compound semiconductor device on the upper surface of the region results in improved device characteristics.Type: GrantFiled: May 9, 2000Date of Patent: November 11, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Masayoshi Koike, Seiji Nagai
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Patent number: 6630023Abstract: A film (carbon and/or diamond) for a field emitter device, which may be utilized within a computer display, is produced by a process utilizing treatment of a substrate and then depositing the film. The treatment step creates nucleation and growth sites on the substrate for the film deposition process and promotes election emission of the deposited film. With this process, a patterned emission can be achieved without post-deposition processing of the film. A field emitter device can be manufactured with such a film.Type: GrantFiled: January 4, 2001Date of Patent: October 7, 2003Assignee: SI Diamond Technology, Inc.Inventors: Zhidan Li Tolt, Zvi Yaniv, Richard Lee Fink
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Patent number: 6630024Abstract: A method for the production of a semiconductor wafer having a front and a back and an epitaxial layer of semiconductor material deposited on the front, includes the following process steps: (a) preparing a substrate wafer having a polished front and a specific thickness; (b) pretreating the front of the substrate wafer in the presence of HCl gas and a silane source at a temperature of from 950 to 1250 degrees Celsius in an epitaxy reactor, the thickness of the substrate wafer remaining substantially unchanged; and (c) depositing the epitaxial layer on the front of the pretreated substrate wafer.Type: GrantFiled: May 24, 2001Date of Patent: October 7, 2003Assignee: Wacker Siltronic Gesellschaft für Halbleitermaterialien AGInventors: Rüdiger Schmolke, Reinhard Schauer, Günther Obermeier, Dieter Gräf, Peter Storck, Klaus Messmann, Wolfgang Siebert
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Patent number: 6620710Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.Type: GrantFiled: September 18, 2000Date of Patent: September 16, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: Theodore I. Kamins
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Patent number: 6617235Abstract: The present invention provides for a method of manufacturing a Group III-V compound semiconductor, which grows a nitrogen-contained Group III-V compound semiconductor of the p-type conductivity, without performing any particular post-processing after growing the compound semiconductor, and which prevents a deterioration in the yield of manufacturing light emitting elements due to post-processing. A first embodiment is directed to a method of manufacturing a Group III-V compound semiconductor which contains p-type impurities and which is expressed by a general formula InxGayAlzN (0≧x≧1,0≧z≧1, x+y+z=1), by thermal decomposition vapor phase method using metalorganics, the method being characterized in that carrier gas is inert gas in which the concentration of hydrogen is 0.5 % or smaller by volume.Type: GrantFiled: March 29, 1996Date of Patent: September 9, 2003Assignee: Sumitomo Chemical Company, LimitedInventors: Yasushi Iyechika, Yoshinobu Ono, Tomoyuki Takada
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Patent number: 6610144Abstract: The present invention discloses a semiconductor film having a reduced dislocation density. The film comprises at least one interlayer structure, including a group III-nitride layer, a passivation interlayer disposed on the group III-nitride layer, interrupting the group III-nitride layer, and an island growth interlayer disposed on the passivation interlayer, and interrupting the group III-nitride layer. A method of making a semiconductor film of the present invention comprises producing a semiconductor film including at least one interlayer structure, each interlayer structure produced by the substeps of growing a group III-nitride layer, depositing a passivation interlayer on the group III-nitride layer, depositing an island growth interlayer on the passivation interlayer and continuing growing the group III-nitride layer.Type: GrantFiled: July 19, 2001Date of Patent: August 26, 2003Assignee: The Regents of the University of CaliforniaInventors: Umesh Kumar Mishra, Stacia Keller
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Patent number: 6610143Abstract: A method of manufacturing a semiconductor component includes forming an electrically insulative layer (220) over a semiconductor substrate where a first portion of the electrically insulative layer is located over a first region (560) of the semiconductor substrate and where a second portion of the first layer is located over a second region (550) of the semiconductor substrate. An isolation region (610) is formed in the semiconductor substrate between the first and second regions of the semiconductor substrate. After forming the isolation region, the second portion of the first layer is removed, and, after removing the second potion of the first layer, an epitaxial layer (630) is grown over the second region of the semiconductor substrate.Type: GrantFiled: January 16, 2001Date of Patent: August 26, 2003Assignee: Semiconductor Components Industries LLCInventors: Peter J. Zdebel, Julio Carlos Costa
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Patent number: 6599362Abstract: A process of growing a material on a substrate, particularly growing a Group II-VI or Group III-V material, by a vapor-phase growth technique where the growth process eliminates the need for utilization of a mask or removal of the substrate from the reactor at any time during the processing. A nucleation layer is first grown upon which a middle layer is grown to provide surfaces for subsequent lateral cantilever growth. The lateral growth rate is controlled by altering the reactor temperature, pressure, reactant concentrations or reactant flow rates. Semiconductor materials, such as GaN, can be produced with dislocation densities less than 107/cm2.Type: GrantFiled: January 3, 2001Date of Patent: July 29, 2003Assignee: Sandia CorporationInventors: Carol I. Ashby, David M. Follstaedt, Christine C. Mitchell, Jung Han
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Patent number: 6596095Abstract: A single crystal silicon wafer with a back surface free of an oxide seal and substantially free of a chemical vapor deposition process induced halo and an epitaxial silicon layer on the front surface, the epitaxial layer is characterized by an axially symmetric region extending radially outwardly from the central axis of the wafer toward the circumferential edge of the wafer having a substantially uniform resistivity, the radius of the axially symmetric region being at least about 80% of the length of the radius of the wafer.Type: GrantFiled: December 29, 2000Date of Patent: July 22, 2003Assignee: MEMC Electronic Materials, Inc.Inventors: Michael J. Ries, Charles Chiun-Chieh Yang, Robert W. Standley
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Patent number: 6592664Abstract: A method for epitaxial deposition of atoms or molecules from a reactive gas on a deposition surface of a substrate is described. The method includes the following steps: a first amount of energy is supplied by heating at least the deposition surface; and an ionized inert gas is conducted, at least from time to time, onto the deposition surface in order to supply, at least from time to time, a second amount of energy through the effect of ions of the ionized inert gas on the deposition surface. The first amount of energy is less than the energy amount necessary for the epitaxial deposition of atoms or molecules of the reactive gas on the deposition surface. A sum of the first energy amount and the second energy equaling, at least from time to time, a total amount of energy that is sufficient for the epitaxial deposition of atoms or molecules of the reactive gas onto the deposition surface.Type: GrantFiled: September 6, 2000Date of Patent: July 15, 2003Assignee: Robert Bosch GmbHInventors: Wilhelm Frey, Franz Laermer, Klaus Heyers
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Patent number: 6589336Abstract: Performing the post-implantation annealing for recovering crystallinity in a hydrogen atmosphere can successfully suppress the surface roughening on the ion-implanted layers without pre-implantation oxidation. This allows omission of the pre-implantation oxidation and allows ion implantation using only a photoresist film as a mask in a method for producing an epitaxial wafer having buried ion-implanted layers. Since an intentional formation of an oxide film, including such pre-implantation oxidation, on an epitaxial layer is omitted, the number of repetition of the thermal history exerted to the buried ion-implanted layers can be reduced, which effectively suppresses lateral diffusion of implanted ions. Since the formation and removal of the oxide film is thus no more necessary, the number of process steps in the production of the epitaxial wafer can dramatically be reduced.Type: GrantFiled: July 10, 2001Date of Patent: July 8, 2003Assignee: Shin-Etsu Handotai Co., Ltd.Inventors: Koji Ebara, Hiroki Ose, Yasuo Kasahara
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Patent number: 6589333Abstract: A method is described for the production of a suitable substrate for the subsequent growth of a mono-crystalline diamond layer. This method includes the following steps: Selection of a substrate of a mono-crystalline material having a fixed lattice constant (aSi) or with a layer consisting of such a material. Manufacture of a strained silicon layer with foreign material atoms incorporated at substitutional lattice sites on the mono-crystalline material of the substrate. Transfer of the strained layer into an at least partly relaxed state in which it adopts by relaxation and through the selected foreign material concentration a lattice constant (aSi(C) which satisfies the condition n.aSi(C)=m.aD, wherein n and m are integers and aD is the lattice constant of diamond, with the relaxed layer forming the substrate or substrate surface for the epitaxial growth.Type: GrantFiled: September 18, 2000Date of Patent: July 8, 2003Assignee: Max-Planck-Gesellschaft zur Foerderung der Wissenschaften e.V.Inventors: Ulrich Gösele, Andreas Plössl
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Patent number: 6579359Abstract: A method is disclosed for fabricating monocrystal material with the bandgap width exceeding 1.8 eV. The method comprises the steps of processing a monocrystal semiconductor wafer to develop a porous layer through electrolytic treatment of the wafer at direct current under UV-illumination, and epitaxially growing a monocrystal layer on said porous layer. Growth on porous layer produces semiconductor material with reduced stress and better characteristics than with the same material grown on non-porous layers and substrates. Also, semiconductor device structure comprising at least one layer of porous group III material is included.Type: GrantFiled: June 2, 2000Date of Patent: June 17, 2003Assignee: Technologies and Devices International, Inc.Inventors: Marina Mynbaeva, Denis Tsvetkov, Vladimir Dmitriev, Alexander Lebedev, Nataliya Savkina, Alexander Syrkin, Stephen Saddow, Karim Mynbaev
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Patent number: 6562127Abstract: A method for making an array of thin single-crystal substrates on a handle substrate comprising the steps: attaching a plurality of single-crystal substrates to a face of a support wafer; polishing said plurality of attached single-crystal substrates so that said single-crystal substrates surfaces are coplanar on said support surface and to a selected surface roughness; implanting a hydrogen to a selected depth into said attached single-crystal substrates; bonding said polished and hydrogen implanted attached single-crystal substrates to a first handle substrate; and splitting said polished and hydrogen implanted attached single-crystal substrates at said selected depth thereby forming an array of thin single-crystal substrates on said first handle substrate and a support wafer having a remaining portion of said attached single-crystal substrates.Type: GrantFiled: January 16, 2002Date of Patent: May 13, 2003Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis Kud, Karl Hobart, Mike Spencer
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Publication number: 20030079677Abstract: A method of fabricating a semiconductor epitaxial wafer having doped carbon includes the steps of mixing a quantity of carbon with a quantity of silicon and then melting together the quantities of carbon and silicon, growing an ingot with carbon from the melted silicon containing carbon, grinding the ingot having carbon so as to produce a flat surface and a notch, slicing the ingot having carbon into a piece of silicon wafer, polishing the silicon wafer having carbon, and growing an epitaxial silicon layer on a surface of the polished silicon wafer having carbon.Type: ApplicationFiled: December 28, 2001Publication date: May 1, 2003Inventor: Seung Ho Pyi
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Patent number: 6537368Abstract: A process for preparing a silicon epitaxial wafer. The wafer has a front surface having an epitaxial layer deposited thereon, a back surface, and a bulk region between the front and back surfaces, wherein the bulk region contains a concentration of oxygen precipitates. In the process, the wafer is first subjected to an ideal oxygen precipitating heat treatment to causes the formation of a non-uniform distribution of crystal lattice vacancies with the concentration of vacancies in the bulk region being greater than the distribution of vacancies in the front surface. The ideal precipitating wafer is then subjected to an oxygen precipitation heat treatment to cause the nucleation and growth of oxygen precipitates to a size sufficient to stabilize the oxygen precipitates, with the oxygen precipitates being formed primarily according to the vacancy profile. An epitaxial layer is then deposited on the surface of the oxygen precipitate stabilized wafer.Type: GrantFiled: August 13, 2001Date of Patent: March 25, 2003Assignee: MEMC Electronic Materials SpAInventors: Robert J. Falster, Marco Cornara, Daniela Gambaro, Massimiliano Olmo
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Patent number: 6530991Abstract: A method for the formation of a semiconductor layer by which a defect density of structural defects, particularly a dislocation density of threading dislocations in the resulting semiconductor layer can be remarkably reduced, so that hours of work can be shortened as well as a manufacturing cost can be reduced without requiring any complicated process comprises supplying a structural defect suppressing material for suppressing structural defects in the semiconductor layer onto a surface of the layer of a material from which the semiconductor layer is to be formed.Type: GrantFiled: December 13, 2000Date of Patent: March 11, 2003Assignees: RikenInventors: Satoru Tanaka, Misaichi Takeuchi, Yoshinobu Aoyagi
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Patent number: 6521041Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.Type: GrantFiled: April 9, 1999Date of Patent: February 18, 2003Assignee: Massachusetts Institute of TechnologyInventors: Kenneth C. Wu, Eugene A. Fitzgerald, Jeffrey T. Borenstein
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Patent number: 6503321Abstract: A method is provided for detaching a single-crystal film from an epilayer/substrate or bulk crystal structure. The method includes the steps of implanting ions into the crystal structure to form a damage layer within the crystal structure at an implantation depth below a top surface of the crystal structure, and chemically etching the damage layer to effect detachment the single-crystal film from the crystal structure. The thin film may be detached by subjecting the crystal structure with the ion implanted damage layer to a rapid temperature increase without chemical etching. The method of the present invention is especially useful for detaching single-crystal metal oxide films from metal oxide crystal structures. Methods for enhancing the crystal slicing etch-rate are also disclosed.Type: GrantFiled: April 9, 1999Date of Patent: January 7, 2003Assignee: The Trustees of Columbia University in the City of New YorkInventors: Miguel Levy, Richard M. Osgood, Jr., Antonije M. Radojevic
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Patent number: 6500258Abstract: This invention relates to a method of growing a nitride semiconductor layer by molecular beam epitaxy comprising the steps of: a) heating a GaN substrate (S) disposed in a growth chamber (10) to a substrate temperature of at least 850° C.; and b) growing a nitride semiconductor layer on the GaN substrate by molecular beam epitaxy at a substrate temperature of at least 850° C., ammonia gas being supplied to the growth chamber (10) during the growth of the nitride semiconductor layer; wherein the method comprises the further step of commencing the supply ammonia gas to the growth chamber during step (a), before the substrate temperature has reached 800° C.Type: GrantFiled: June 18, 2001Date of Patent: December 31, 2002Assignee: Sharp Kabushiki KaishaInventors: Stewart Edward Hooper, Jonathan Heffernan, Jennifer Mary Barnes, Alistair Henderson Kean
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Patent number: 6497763Abstract: A method for making a multilayered electronic device with at least one epitaxial layer grown on a single-crystal film bonded to a composite wherein at least one layer is polycrystalline, the method includes the step of bonding a single-crystal film at least one of the epitaxial layers on the single-crystal film wherein thermal coefficients of expansion for the substrate and the epitaxial layer are closely matched.Type: GrantFiled: January 19, 2001Date of Patent: December 24, 2002Assignee: The United States of America as represented by the Secretary of the NavyInventors: Francis J. Kub, Karl D. Hobart
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Publication number: 20020185057Abstract: The invention provides a process for growing UV region <200 nm transmitting calcium fluoride monocrystals, which includes crystallization from the melt, the annealing of the crystals and subsequent cooling, in a vacuum furnace, and which is effected by the continuous transfer of the crucible containing the melt from the crystallization zone into the annealing zone, each of these two zones having its own independent control system for the process parameters, characterized in that there is a temperature drop of 250-450° C. from the crystallization zone to the annealing zone, with a gradient of 8-12° C./cm, the crucible containing the material to be crystallized is moved from the crystallization zone to the annealing zone at a speed of 1-3 mm/hour, it is first kept in the annealing zone at a holding temperature of 1100-1300° C. for 20-40 hours and is then cooled first to 950-900° C. at a rate of 2-40 C./hour and then to 300° C. at a rage of 5-8° C.Type: ApplicationFiled: April 16, 2002Publication date: December 12, 2002Inventors: Evgeny A. Garibin, Aleksey A. Demidenko, Boris I. Kvashnin, Igor A. Mironov, Gury T. Petrovsky, Vladimir M. Reyterov, Aleksandr N. Sinev
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Patent number: 6478871Abstract: An epitaxial deposition process produces epitaxial lateral overgrowth (ELO) of nitride based materials directly a patterned substrate (10). The substrate (10) is preferably formed from SiC or sapphire, and is patterned with a mask (12), preferably formed of silicon nitride, having a plurality of openings (13) formed therein. A nucleation layer (14), preferably formed of AlGaN, is grown at a high reactor temperature of 700-1100 degrees C., which wets the exposed substrate surface, without significant nucleation on the mask (12). This eliminates the need for regrowth while producing smooth growth surfaces in the window openings (13) as well as over the mask (12). Subsequent deposition of a nitride based material layer (16), preferably GaN, results in a relatively defect free planar surfaced material grown laterally over the mask (12).Type: GrantFiled: October 2, 2000Date of Patent: November 12, 2002Assignee: Cornell Research Foundation, Inc.Inventors: James R. Shealy, Joseph A. Smart
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Patent number: 6475456Abstract: There is disclosed a method for manufacturing a silicon carbide film in which a crystal orientation is continued on a single crystal substrate surface and silicon carbide is allowed to epitaxially grow, the method comprising the steps of: entirely or partially providing the substrate surface with a plurality of undulations extended parallel in one direction; and allowing silicon carbide to grow on the substrate surface.Type: GrantFiled: December 3, 2001Date of Patent: November 5, 2002Assignee: Hoya CorporationInventors: Yukitaka Nakano, Hiroyuki Nagasawa, Kuniaki Yagi, Takamitsu Kawahara
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Publication number: 20020157601Abstract: A polycrystalline thin film of MgO is formed on a substrate by an ion sputtering process wherein the thin film is obtained by irradiating a target with an ion beam to dislodge particles from the target and deposit the particles on the substrate. The film is preferably formed in an atmosphere at a reduced pressure of 3.0×10−2 Pa or lower while keeping the substrate temperature at 300° C. or lower.Type: ApplicationFiled: October 6, 2001Publication date: October 31, 2002Inventors: Yasuhiro Iijima, Mariko Kimura, Takashi Saito
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Patent number: 6468348Abstract: An open form is produced with a plurality of in each case two-dimensionally structured layers. The form is made of silicon which is etchable in dependence on its doping. A first silicon layer is first produced, and a portion of the first layer which belongs to the form to be produced, is marked by doping at least one zone of the first layer. Subsequently, at least one further silicon layer is applied, and a portion belonging to the form is also marked therein. Finally, every unmarked portion of the layers is removed by etching depending on the respective doping of each layer. The open form is, in particular, a photonic crystal.Type: GrantFiled: March 30, 2000Date of Patent: October 22, 2002Assignee: Infineon Technologies AGInventors: Ulrike Grüning, Hermann Wendt, Volker Lehmann, Reinhard Stengl, Hans Reisinger
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Patent number: 6464780Abstract: The invention relates to a method for the production of a monocrystalline layer on a substrate with a non-adapted lattice. To this end, a monocrystalline substrate with a buried amply defective layer and a monocrystalline layer produce thereon are used. The buried amply defective layer can be produced by hydrogen implantation.Type: GrantFiled: August 29, 2000Date of Patent: October 15, 2002Assignee: Forschungszentrum Julich GmbHInventors: Siegfried Mantl, Bernhard Holländer, Ralf Liedtke
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Patent number: 6458206Abstract: AFM/STM probes are based on whiskers grown by the vapor-liquid-solid (VLS) mechanism. Silicon cantilevers oriented along the crystallographic plane (111) are prepared from silicon-on-insulator structures that contain a thin layer (111) on a (100) substrate with SiO2 interposed layer. At removal of solidified alloy globules inherent in the growth mechanism sharpening of the whiskers takes place and, in such a way, the probes are formed. Cross-sections of the wiskers grown by the mechanism on the cantilevers can be controllably changed during the growth process so that step-shaped whiskers optimal for fabrication of the probes can be prepared. Also, whiskers with expansions/contractions can be formed that are important for fabrication of probes suitable for investigations in coarse surfaces, complicated cavitites, grooves typical for semiconductor microelectronics, etc.Type: GrantFiled: March 9, 2001Date of Patent: October 1, 2002Assignee: Crystals and Technologies, Ltd.Inventors: Evgeny Invievich Givargizov, Lidiya Nikolaevna Obolenskaya, Ala Nikolaevna Stepanova, Evgeniya Sergeevna Mashkova, Michail Evgenievich Givargizov
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Patent number: 6458205Abstract: By forming a silicon single-crystal thin film direct on a chemically etched substrate, a time required for all the process can be effectively shortened, which largely contributes to reduction in production cost of a silicon epitaxial wafer and improvement on production efficiency thereof, with the result that a reduced wafer price at a user's end and a short delivery time are ensured. In a technical aspect, an etching removal in a chemical etching treatment is set to be 60 &mgr;m or more and thereby, a glossiness of a front main surface of a chemically etched substrate can be ensured to be 95% or higher. With such a glossiness of the front main surface of the substrate employed, a surface glossiness of a silicon single-crystal thin film formed on the front main surface of the chemically etched substrate can be increased to 95% or higher, thereby, enabling an auto-alignment treatment in a lithographic step coming later with no trouble.Type: GrantFiled: December 19, 2000Date of Patent: October 1, 2002Assignees: Shin-Etsu Handotai Co., Ltd., Naoetsudenshikogyo-KabushikigaishaInventors: Koichi Hasegawa, Yuji Okubo
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Publication number: 20020134301Abstract: Disclosed are compositions comprising one or more pentamantanes. Specifically disclosed are compositions comprising 10 to 100 weight percent of one or more pentamantanes. Also disclosed are novel processes for the separation and isolation of pentamantane components into recoverable fractions from a feedstock containing at least a higher diamondoid component which contains one or more pentamantane components.Type: ApplicationFiled: December 12, 2001Publication date: September 26, 2002Inventors: Jeremy E. Dahl, Robert M. Carlson
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Patent number: 6447604Abstract: A III-V nitride homoepitaxial microelectronic device structure comprising a III-V nitride homoepitaxial epi layer on a III-V nitride material substrate, e.g., of freestanding character. Various processing techniques are described, including a method of forming a III-V nitride homoepitaxial layer on a corresponding III-V nitride material substrate, by depositing the III-V nitride homoepitaxial layer by a VPE process using Group III source material and nitrogen source material under process conditions including V/III ratio in a range of from about 1 to about 105, nitrogen source material partial pressure in a range of from about 1 to about 103 torr, growth temperature in a range of from about 500 to about 1250 degrees Celsius, and growth rate in a range of from about 0.1 to about 500 microns per hour. The III-V nitride homoepitaxial microelectronic device structures are usefully employed in device applications such as UV LEDs, high electron mobility transistors, and the like.Type: GrantFiled: June 28, 2000Date of Patent: September 10, 2002Assignee: Advanced Technology Materials, Inc.Inventors: Jeffrey S. Flynn, George R. Brandes, Robert P. Vaudo, David M. Keogh, Xueping Xu, Barbara E. Landini
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Patent number: 6440214Abstract: A method of growing a nitride semiconductor layer, such as a GaN layer, by molecular beam epitaxy comprises the step of growing a GaAlN nucleation layer on a substrate by molecular beam epitaxy. The nucleation layer is annealed, and a nitride semiconductor layer is then grown over the nucleation layer by molecular beam epitaxy. The nitride semiconductor layer is grown at a V/III molar ratio of 100 or greater, and this enables a high substrate temperature to be used so that a good quality semiconductor layer is obtained. Ammonia gas is supplied during the growth process, to provide the nitrogen required for the MBE growth process.Type: GrantFiled: June 9, 2000Date of Patent: August 27, 2002Assignee: Sharp Kabushiki KaishaInventors: Stewart Edward Hooper, Jennifer Mary Barnes, Jonathan Heffernan, Alistair Henderson Kean
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Publication number: 20020104477Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.Type: ApplicationFiled: August 29, 2001Publication date: August 8, 2002Inventors: Hisayoshi Yamoto, Hideo Yamanaka
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Publication number: 20020100413Abstract: Disclosed is a method for depositing a thin dielectric on a portion in which a decreased growth speed of epitaxy is needed in a bridge fashion, and adjusting the width of bridges made of dielectric material and the distance of the bridges deposited, thereby controlling a growth speed and growth thickness of an epitaxial growth layer, which comprising the processes of growing a bridge-shape thin dielectric on a semiconductor substrate for fabricating a semiconductor integrated circuit device, and growing an epitaxial layer with different epitaxial growth rates on selective areas on top of the semiconductor substrate. Thus, the method controls a distance between bridges and a width of the bridge, thereby adjusting a growth speed and growth thickness of an epitaxial layer to be grown in future.Type: ApplicationFiled: December 27, 2001Publication date: August 1, 2002Inventors: Jeong Soo Kim, Ho Sung Cho, Kyu-Seok Lee
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Publication number: 20020096107Abstract: A cylinder array of diamond having a dent in its cylinder top face is manufactured by subjecting a cylinder array of diamond to a plasma etching.Type: ApplicationFiled: August 17, 2001Publication date: July 25, 2002Inventors: Akira Fujishima, Hideki Masuda
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Publication number: 20020096106Abstract: A method for making a multilayered electronic device with at least one epitaxial layer grown on a single-crystal film bonded to a composite wherein at least one layer is polycrystalline, the method includes the step of bonding a single-crystal film at least one of the epitaxial layers on the single-crystal film wherein thermal coefficients of expansion for the substrate and the epitaxial layer are closely matched.Type: ApplicationFiled: January 19, 2001Publication date: July 25, 2002Inventors: Francis J. Kub, Karl D. Hobart