With Pretreatment Or Preparation Of A Base (e.g., Annealing) Patents (Class 117/94)
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Patent number: 5861337Abstract: A method for manufacturing a semiconductor device including preparing a multi-chamber system having at least first and second chambers, the first chamber for forming a film and the second chamber for processing an object with a laser light; processing a substrate in one of the first and second chambers; transferring the substrate to the other one of the first and second chambers; and processing the substrate in the other one of the chambers, wherein the first and second chambers can be isolated from one another by using a gate valve.Type: GrantFiled: June 2, 1995Date of Patent: January 19, 1999Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Naoto Kusumoto
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Patent number: 5861058Abstract: A composite structure for electronic components, having a base substrate with a flat side provided with a depression, and having a cover layer which is disposed on the flat side structured by the depression, and the depression being covered to form a hollow structure. The depression in the base substrate is created prior to the deposition of the cover layer and has a clear width measured parallel to the flat side that is less than one-half of its clear depth measured before the cover layer is applied. The vapor phase deposited cover layer is formed from a material which has a sufficiently high surface tension to promote three-dimensional growth of the vapor phase deposited layer.Type: GrantFiled: April 22, 1996Date of Patent: January 19, 1999Assignee: Daimler-Benz AktiengesellschaftInventors: Hans-Juergen Fuesser, Reinhard Zachai, Wolfram Muench, Tim Gutheit, Mona Ferguson, Reiner Schaub, Karl-Heinrich Greeb
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Patent number: 5843224Abstract: The invention relates to a composite structure including a semiconductor layer arranged on a diamond layer and/or a diamond-like layer, for subsequent processing to produce electronic components and/or groups of components and to a process for producing such a composite structure. In order to improve the quality of the subsequent components, the diamond layer is deposited underneath the component source zones from which the components are subsequently produced, and the diamond or diamond-like layer is provided at the margins of the component source zones and/or outside of the component source zones with edges where the thickness of the layer changes abruptly such that the edges have an edge height amounting to at least 1O%, preferably at least 50%, of the layer thickness of the diamond layer.Type: GrantFiled: August 7, 1995Date of Patent: December 1, 1998Assignee: Daimler-Benz AktiengesellschaftInventors: Reinhard Zachai, Tim Gutheit, Kenneth Goodson
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Patent number: 5843227Abstract: A crystal growth method for growing on a gallium arsenide (GaAs) substrate a gallium nitride (GaN) film which is good in surface flatness and superior in crystallinity. According to the method, a GaAs substrate having a surface which is inclined with respect to the GaAs(100) face is used. The inclination angle of the substrate surface is larger than 0 degree but smaller than 35 degrees with respect to the GaAs(100) face. The inclination direction of the substrate surface is within a range of an angular range from the ?0,0,1! direction of GaAs to the ?0,-1,0! direction past the ?0,-1,1! direction and angles less than 5 degrees on opposite sides of the angular range around an ?1,0,0! direction of gallium arsenide taken as an axis, or within another range crystallographically equivalent to the range. The GaN layer is formed on the surface of the GaAs substrate preferably by hydride vapor deposition method.Type: GrantFiled: January 13, 1997Date of Patent: December 1, 1998Assignee: NEC CorporationInventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido, Atsushi Yamaguchi
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Patent number: 5827365Abstract: A vapor phase growth process for the fabrication of a thin film form of compound semiconductor of elements of Groups III-V, using a halogen element-free hydride and a halogen element-free organic metal as the source materials for growth, is characterized in that a halide gas and/or a halogen gas that are free from the mother elements of the compound to be grown are added to the reaction atmosphere while the compound is growing. A trace amount(s) of the halide and/or halogen gas(es) that are free from the mother elements of the compound to be grown, such as HCl, is added to the reaction atmosphere while the compound is growing, thereby making it possible to flatten the heterojunction interface or effect the growth of high-quality crystals without deposition of polycrystals on a mask over a wide range.Type: GrantFiled: January 23, 1995Date of Patent: October 27, 1998Assignee: Mitsubishi Kasei CorporationInventors: Kenji Shimoyama, Hideki Gotoh
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Patent number: 5817174Abstract: A method of treating a semiconductor substrate, which comprises the steps of subjecting a surface of the semiconductor substrate to an annealing treatment, performing an etching treatment of the surface of the semiconductor substrate under a condition where the semiconductor substrate is substantially prevented from being etched and a precipitate exposed from the surface of the semiconductor substrate is selectively etched away, and forming a monocrystalline film of a semiconductor material constituting the semiconductor substrate on the surface of the semiconductor substrate.Type: GrantFiled: December 13, 1996Date of Patent: October 6, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Tomita, Mami Takahashi
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Patent number: 5810923Abstract: The invention provides an oxide thin film in the form of an epitaxial film of the composition: Zr.sub.1-x R.sub.x O.sub.2-.delta. wherein R is a rare earth metal inclusive of Y, x=0 to 0.75, preferably x=0.20 to 0.50, formed on a surface of a single crystal silicon substrate. A rocking curve of the film has a half-value width of up to 1.50.degree.. The film has a ten point mean roughness Rz of up to 0.60 nm across a reference length of 500 nm. An epitaxial film of the composition ZrO.sub.2 is constructed by unidirectionally oriented crystals. When a functional film is to be formed on the oxide thin film serving as a buffer film, an adequately epitaxially grown functional film of quality is available.Particularly when the single crystal substrate is rotated within its plane, an oxide thin film of uniform high quality having an area as large as 10 cm.sup.2 or more is obtained.Type: GrantFiled: May 10, 1996Date of Patent: September 22, 1998Assignee: TDK CorporationInventors: Yoshihiko Yano, Takao Noguchi, Katsuto Nagano
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Patent number: 5810925Abstract: A GaN single crystal having a full width at half-maximum of the double-crystal X-ray rocking curve of 5-250 sec and a thickness of not less than 80 .mu.m, a method for producing the GaN single crystal having superior quality and sufficient thickness permitting its use as a substrate and a semiconductor light emitting element having high luminance and high reliability, comprising, as a substrate, the GaN single crystal having superior quality and/or sufficient thickness permitting its use as a substrate.Type: GrantFiled: May 17, 1996Date of Patent: September 22, 1998Assignee: Mitsubishi Cable Industries, Ltd.Inventors: Kazuyuki Tadatomo, Shinichi Watabe, Hiroaki Okagawa, Kazumasa Hiramatsu
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Patent number: 5811375Abstract: A superconducting multilayer interconnection comprises a substrate having a principal surface, a first superconducting current path of a c-axis orientated oxide superconductor thin film formed on the principal surface of the substrate, an insulating layer on the first superconducting current path, and a second superconducting current path of a c-axis orientated oxide superconductor thin film formed on the insulating layer so that the first and second superconducting current paths are insulated by the insulating layer. The superconducting multilayer interconnection further comprises a superconducting interconnect current path of an a-axis orientated oxide superconductor thin film, through which the first and second superconducting current paths are electrically connected each other.Type: GrantFiled: June 30, 1995Date of Patent: September 22, 1998Assignee: Sumitomo Electric Industries Ltd.Inventors: Takao Nakamura, Hiroshi Inada, Michitomo Iiyama
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Patent number: 5795795Abstract: A method of fabricating a semiconductor device by the use of laser crystallization steps is provided. During these crystallization steps, an amorphous or polycrystalline semiconductor is crystallized by laser irradiation in such a way that generation of ridges is suppressed. Two separate laser crystallization steps are carried out. First, a laser irradiation step is performed in a vacuum, using somewhat weak laser light. Then, another laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient with intenser laser light. The first laser irradiation conducted in a vacuum does not result in satisfactory crystallization. However, this irradiation can suppress generation of ridges. The second laser irradiation step is performed in a vacuum, in the atmosphere, or in an oxygen ambient to achieve sufficient crystallization, but no ridges are produced.Type: GrantFiled: June 5, 1995Date of Patent: August 18, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takamasa Kousai, Hongyong Zhang, Akiharu Miyanaga
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Patent number: 5788766Abstract: A window material, which has a high thermal conductivity material layer having a thermal conductivity of at least 10 W/cm.multidot.K and which has a cooling medium flow path on or in the high thermal conductivity material layer, has a high heat-dissipating property and a high transmittance.Type: GrantFiled: November 30, 1995Date of Patent: August 4, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yoshiyuki Yamamoto, Keiichiro Tanabe, Katsuko Harano, Takashi Tsuno, Nobuhiro Ota, Naoji Fujimori
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Patent number: 5785754Abstract: A substrate, which has a high thermal conductivity material layer having a thermal conductivity of at least 10 W/cm.multidot.K and which has a cooling medium flow path on or in the high thermal conductivity material layer, has a high heat-dissipating property.Type: GrantFiled: November 30, 1995Date of Patent: July 28, 1998Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yoshiyuki Yamamoto, Keiichiro Tanabe, Katsuko Harano, Nobuhiro Ota, Naoji Fujimori
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Patent number: 5759265Abstract: A buffer layer having crystal orientation In a (111) face is formed on a semiconductor single-crystal (100) substrate and a ferroelectric thin film having crystal orientation in a (111) or (0001) face is then formed over the buffer layer. The buffer layer is preferably formed of MgO at a temperature ranging from 20.degree. to 600.degree. C. and at a rate ranging from 0.5 to 50 .ANG./sec. The thus formed ferroelectric thin film has its axes of polarization aligned in one direction. Using the oriented ferroelectric thin-film device, highly functional nonvolatile memories, capacitors or optical modulators can be fabricated on semiconductor substrates.Type: GrantFiled: May 3, 1995Date of Patent: June 2, 1998Assignee: Fuji Xerox Co., Ltd.Inventors: Keiichi Nashimoto, Atsushi Masuda
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Patent number: 5755879Abstract: A method is presented to manufacture substrates for growing monocrystalline diamond films by chemical vapor deposition (CVD) on large area at low cost. The substrate materials are either Pt or its alloys, which have been subject to a single or multiple cycle of cleaning, roller press, and high temperature annealing processes to make the thickness of the substrate materials to 0.5 mm or less, or most preferably to 0.2 mm or less, so that either (111) crystal surfaces or inclined crystal surfaces with angular deviations within .+-.10 degrees from (111), or both, appear on the entire surfaces or at least part of the surfaces of the substrates. The annealing is carried out at a temperature above 800.degree. C. The present invention will make it possible to markedly improve various characteristics of diamond films, and hence put them into practical use.Type: GrantFiled: November 17, 1995Date of Patent: May 26, 1998Assignee: Kabushiki Kaisha Kobe Seiko ShoInventors: Yoshihiro Shintani, Takeshi Tachibana, Kozo Nishimura, Koichi Miyata, Yoshihiro Yokota, Koji Kobashi
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Patent number: 5753038Abstract: A method is disclosed for producing large single crystals. According to the initial steps of this method, a plurality of single crystal wafers are crystallographically oriented to form a seed plate which is patterned. The patterned seed plate is selectively etched to expose the bare surface of the seed plate. The exposed, patterned bare surface of the seed plate is etched to form a plurality of nucleation structures. Each of the nucleation structures protrude outwardly from the underlying surface of the seed plate and provide ideal structures for the growth of large, single crystals. The resulting large, single crystals can be separated from the seed crystals by etching, physical or chemical means.Type: GrantFiled: March 21, 1997Date of Patent: May 19, 1998Assignee: Air Products and Chemicals, Inc.Inventors: Miroslav Vichr, David Samuel Hoover
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Patent number: 5746826Abstract: Utilizing rugged pattern of atomic size present on a crystalline substrate of a semiconductor such as silicon or selenium or the like, a microstructure body is produced on the substrate by forming a layer of a first element of one monolayer or less by arranging at the position of the substrate most stable in energy formed by ruggedness the atoms of the first element such as gold, silver, copper, nickel, palladium, platinum or an element of group IV and then depositing successively atoms of at least one second element of group III, group IV and group V on only at a part of the surface of the substrate on which said layer of one monolayer or less by vapor deposition, sputtering or the like.Type: GrantFiled: December 2, 1994Date of Patent: May 5, 1998Assignee: Hitachi, Ltd.Inventors: Tsuyoshi Hasegawa, Shigeyuki Hosoki, Makiko Kohno, Masakazu Ichikawa, Hitoshi Nakahara, Toshiyuki Usagawa
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Patent number: 5741360Abstract: In a method of selectively growing a crystal of a compound semiconductor layer which is composed of gallium and arsenic, a selective growth is selectively carried out on a substrate by using a combination of metallic gallium and a reactive gas, such as trisdimethylminoarsine, which includes a metallic compound of arsenic specified by at least one amine. The combination may includes organometallic gallium, such as trimethylgallium, triethylgallium instead of the metallic gallium. Such a combination serves to selectively deposit the compound semiconductor layer only on an exposed portion uncovered with a mask. Any other compound semiconductor layer may be selectively deposited on the exposed portion. The exposed portion may be composed of GaAs, AlGaAs, or InGaAs.Type: GrantFiled: August 11, 1995Date of Patent: April 21, 1998Assignee: Optoelectronics Technology Research CorporationInventors: Shigeo Goto, Yasuhiko Nomura, Yoshitaka Morishita, Seikoh Yoshida, Masahiro Sasaki
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Patent number: 5739086Abstract: A biaxially textured article includes a rolled and annealed, biaxially textured substrate of a metal having a face-centered cubic, body-centered cubic, or hexagonal close-packed crystalline structure; and an epitaxial superconductor or other device epitaxially deposited thereon.Type: GrantFiled: May 22, 1996Date of Patent: April 14, 1998Assignee: Lockheed Martin Energy Systems, Inc.Inventors: Amit Goyal, John D. Budai, Donald M. Kroeger, David P. Norton, Eliot D. Specht, David K. Christen
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Patent number: 5738720Abstract: The present invention aims to provide a method of manufacturing a microstructure pattern of a high orientation aggregate of organic molecular material by forming a fine pattern made by single crystal growing ionic material of another property on an ionic substrate by lithography and epitaxial growth, and forming a pattern made by organic molecular material having functionability to light on the fine pattern by utilizing dependence of substrate material of crystal growth rate in epitaxial growth, and is applied to the formation of a microstructure pattern of organic molecular material which can be utilized for optical waveguide, optical integrated circuit, non-linear optical element and laser resonator.Type: GrantFiled: February 12, 1996Date of Patent: April 14, 1998Assignee: The University of TokyoInventors: Toshihiro Shimada, Atsushi Koma
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Patent number: 5728214Abstract: When a cuprate oxide LnBa.sub.2 Cu.sub.3 O.sub.7-x (Ln=Y, Pr or Sm; 0.30.ltoreq.x.ltoreq.1) single crystal is heated for growing a film epitaxially on the crystal or for smoothing a damaged surface of the single crystal, many large protrusions occur on the surface of the oxide single crystal substrate or the film. The smooth surface of the oxides becomes rugged by the protrusions. According to the present invention, however, the oxide substrate or the oxide superconductor film can be heated in an atmosphere including oxygen of a partial pressure between 50 mTorr and 200 mTorr to prevent the protrusions from originating on the surface of the heated oxides.Type: GrantFiled: September 6, 1995Date of Patent: March 17, 1998Assignees: Sumitomo Electric Industries, Ltd., Kabushiki Kaisha Toshiba, International Superconductivity Technology CenterInventors: Masaya Konishi, Hiroyuki Fuke, Youichi Enomoto, Yuh Shiohara, Shoji Tanaka
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Patent number: 5718761Abstract: A method of forming a crystalline compound semiconductor film comprises introducing into a crystal forming space housing a substrate on which a non-nucleation surface (S.sub.NDS) having a smaller nucleation density and a nucleation surface (S.sub.NDL) having a fine surface area sufficient for crystal growth only from a single nucleus and having a larger nucleation density (ND.sub.L) than the nucleation density (NDs) of the non-nucleation surface (S.sub.NDS) are arranged adjacent to each other an organometallic compound (VI) for supplying an element belonging to the group VI of Periodic Table represented by the general formula R.sub.1 --X.sub.n --R.sub.2 wherein n is an integer of 2 or more; R.sub.1 and R.sub.Type: GrantFiled: April 17, 1996Date of Patent: February 17, 1998Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Tokunaga, Jun-ichi Hanna, Isamu Shimizu
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Patent number: 5690736Abstract: A crystal is formed by applying crystal forming treatment to a substrate, the surface of the substrate being divided into nonnucleation surface exhibiting a small nucleation density and nucleation surface having a sufficeintly small area to allow crystal growth from a single nucleus and exhibiting a larger nucleation density than the nonnucleation surface and the nonnucleation surface being constituted of the surface of a buffer layer to alleviate generation of stress in the crystal formed.Type: GrantFiled: January 31, 1996Date of Patent: November 25, 1997Assignee: Canon Kabushiki KaishaInventor: Hiroyuki Tokunaga
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Patent number: 5676752Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.Type: GrantFiled: August 16, 1994Date of Patent: October 14, 1997Assignee: Massachusetts Institute of TechnologyInventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
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Patent number: 5667586Abstract: A structure is fabricated comprising a substrate, a dielectric layer formed over the substrate, and a single crystal layer of a compound formed over the dielectric layer. The single crystal layer is formed by the chemical reaction of at least a first element with an initial single crystal layer of a second element on the dielectric layer having an initial thickness of about 100 to about 10,000 angstroms.According to another aspect, a carbide single crystal layer is provided on a substrate by depositing carbon from a solid carbon source at a low rate and low temperature, followed by reacting the carbon with the underlying layer to convert it to the carbide.Type: GrantFiled: April 1, 1996Date of Patent: September 16, 1997Assignee: International Business Machines CorporationInventors: Bruce Allen Ek, Stephen McConnell Gates, Fernando Jose Guarin, Subramanian Srikanteswara Iyer, Adrian Roger Powell
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Patent number: 5653802Abstract: A method for forming a crystal comprises implanting ions on the surface of a substrate to change the ion concentration in the depth direction of said substrate surface by said ion implantation, subjecting a desired position of said substrate surface with a sufficient area for crystal growth from a single crystal to exposure treatment to/he depth where an exposed surface having larger nucleation density than the nucleation density of the surface of said substrate is exposed, thereby forming a nucleation surface comprising said exposed surface exposed by said exposure treatment and a nonnucleation surface comprising the surface of the substrate remaining without subjected to said exposure treatment, applying a crystal growth treatment for crystal growth from a single nucleus on said substrate to grow a single crystal from said single nucleus or form a polycrystal of a mass of single crystals grown from said single nucleus.Type: GrantFiled: May 30, 1995Date of Patent: August 5, 1997Assignee: Canon Kabushiki KaishaInventor: Kenji Yamagata
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Patent number: 5648114Abstract: A substrate is prebaked in an oxygen furnace. A thin film of layered superlattice oxide is formed on the substrate by a chemical vapor deposition process. The film is RTP baked to provide grains with a mixed phase of A-axis and C-axis orientation. The film may be treated by ion implantation prior to the RTP bake and oxygen furnace annealed after the RTP bake. An electrode is deposited on the layered superlattice thin film and then the film and electrode are oxygen furnace annealed.Type: GrantFiled: July 12, 1993Date of Patent: July 15, 1997Assignees: Symetrix Corporation, Olympus Optical Co., Ltd.Inventors: Carlos A. Paz De Araujo, Hitoshi Watanabe, Michael C. Scott, Takashi Mihara
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Patent number: 5637145Abstract: In a vapor phase epitaxial growth process, formation of a silicon nodule on a back side protective film on a wafer is prevented. In the process, a susceptor situated within a reaction chamber is provided with a depression portion for supporting a wafer at a back side peripheral portion thereof. A protection film on a back side peripheral portion of the wafer, which is to be in contact with the susceptor 4 is removed in advance, prior to epitaxial growth. In addition, it is also effective to apply a silicon coating on the surface of the depression portion, prior to the epitaxial growth process.Type: GrantFiled: January 3, 1996Date of Patent: June 10, 1997Assignee: Toshiba Machine Co., Ltd.Inventors: Yoshihiro Miyanomae, Nobuo Kashiwagi
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Patent number: 5632812Abstract: A diamond electronic device constituted of a diamond crystal formed on a substrate comprises a diamond crystal having the ratio (h/L) of length (h) of the diamond crystal in direction substantially perpendicular to the face of the substrate to length (L) of the diamond crystal in direction parallel to the face of the substrate ranging from 1/4 to 1/1000 and an upper face of the diamond crystal making an angle of from substantially 0.degree. to 10.degree. to the face of the substrate, and a semiconductor layer and an electrode layer provided on the diamond crystal, wherein the diamond crystal serves as a heat-radiating layer.Type: GrantFiled: June 6, 1995Date of Patent: May 27, 1997Assignee: Canon Kabushiki KaishaInventor: Keiji Hirabayashi
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Patent number: 5603765Abstract: High breakdown voltages for AlInAs layers in InP-based devices, such as a gate layer in an InP HEMT or a collector layer in a heterojunction bipolar transistor, are achieved by growing the AlInAs layer by MBE at a substrate temperature about 70.degree.-125.degree. C. below the temperature at which a 2.times.4 reflective high energy diffraction pattern is observed. This corresponds to a growth temperature range of about 415.degree.-470.degree. C. for a 540.degree. 2.times.4 reconstruction temperature. Preferred growth temperatures within these ranges are 80.degree. C. below the 2.times.4 reconstruction temperature, or about 460.degree. C. Higher breakdown voltages are obtained than when the AlInAs layer is grown at either higher or lower temperatures.Type: GrantFiled: April 21, 1995Date of Patent: February 18, 1997Assignee: Hughes Aircraft CompanyInventors: Mehran Matloubian, Linda M. Jelloian, Mark Lui, Takyiu Liu
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Patent number: 5593497Abstract: A method for forming a deposited film comprises the step of introducing a starting material (A) which is either one of a gaseous starting material for formation of a deposited film and a gaseous halogenic oxidizing agent having the property of oxidative action on said starting material into a film forming space in which a substrate having a material which becomes crystal neclei for a deposited film to be formed or a material capable of forming crystal nuclei selectively scatteringly on its surface is previously arranged to have said starting material (A) adsorbed onto the surface of said substrate to form an adsorbed layer (I) and the step of introducing a starting material (B) which is the other one into said film forming space, thereby causing surface reaction on said adsorption layer (I) to form a crystalline deposited film (I).Type: GrantFiled: April 3, 1995Date of Patent: January 14, 1997Assignee: Canon Kabushiki KaishaInventors: Jinsho Matsuyama, Yutaka Hirai, Masao Ueki, Akira Sakai
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Patent number: 5588994Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.Type: GrantFiled: June 6, 1995Date of Patent: December 31, 1996Assignee: Massachusetts Institute of TechnologyInventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
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Patent number: 5587014Abstract: There is provided a method for manufacturing group III-V compound semiconductors including at least Ga as the group III element and at least N as the group V element by using metal-organic compounds of group III elements having at least Ga in the molecules thereof and compounds having at least N in the molecules thereof as the raw materials, and the group III-V compound semiconductor crystals are grown in a reaction tube, and epitaxial layer of crystals are grown on a substrate made of a material different from that of the crystals to be grown, wherein at least one kind of gas, selected from a group consisting of compounds including halogen elements and group V elements and hydrogen halide, is introduced before the growth of the compound semiconductor crystal begins, thereby to carry out gas-phase etching of the inner wall surface of a reaction tube.Type: GrantFiled: December 21, 1994Date of Patent: December 24, 1996Assignee: Sumitomo Chemical Company, LimitedInventors: Yasushi Iyechika, Tomoyuki Takada
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Patent number: 5578521Abstract: A silicon semiconductor substrate, on which an epitaxial layer is to be formed, is set in a reaction vessel having a heating mechanism, and a gas containing TMG and AsH.sub.3 is introduced into the reaction vessel with the substrate heated to 450.degree. C., thus forming, on the substrate, a low-temperature growth layer of amorphous or polycrystalline GaAs as a semiconductor substance having a different lattice constant from that of the substrate. Then, with the TMG removed from the introduced gas, the temperature of the semiconductor substrate is increased to 750.degree. C., to cause coagulation of atoms of the low-temperature growth layer, with a thermal treatment also being performed at this high temperature, to cause growth of island-like single crystal cores. Further, a high temperature growth process is conducted in a material gas atmosphere containing TMG, whereby a GaAs film is epitaxially grown on the semiconductor substrate surface.Type: GrantFiled: May 3, 1995Date of Patent: November 26, 1996Assignee: Nippondenso Co., Ltd.Inventors: Yasutoshi Suzuki, Takamasa Suzuki, Kunihiko Hara, Hajime Inuzuka, Naomi Awano, Kouichi Hoshino
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Patent number: 5525538Abstract: An amorphous compound is changed to single crystal structure by heating at an elevated temperature in an inert atmosphere or in an atmosphere of a forming gas, the amorphous compound is composed of at least one Group III-A element of the Periodic Table and at least one Group V-A element, the amorphous compound having an excess over stoichiometric amount of at least one Group V-A element. The single crystal phase compound, intrinsically doped with at least one element from Group V-A, has the properties of high conductivity for a semiconductor without using any extrinsic dopant and a non-alloyed ohmic contact with a metal.Type: GrantFiled: March 8, 1995Date of Patent: June 11, 1996Assignee: The United States of America as represented by the Secretary of the NavyInventors: Mark E. Twigg, Mohammad Fatemi, Bijan Tadayon
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Patent number: 5493986Abstract: A method is described which makes it possible to use VLSI-quality crystalline semiconductor substrates for the fabrication of the active devices of Active Matrix Flat Panels (AMFPD). The VLSI substrates are provided by arranging a layer of light transparent material in those areas of a semiconductor wafer in which no active device has to be provided, eliminating the semiconductor wafer whereby a transparent wafer is obtained with crystalline semiconductor regions therein and then shaping the transparent wafer into a sized module unit. Several module units can be bonded to a glass substrate and a conductive material is then deposited to make electrical interconnections between the module units. The bonding operation can be performed either at room temperature using a light-transparent glue or at higher temperature using a wafer bonding technique known in the art of Silicon-On-Insulator technology.Type: GrantFiled: January 5, 1995Date of Patent: February 27, 1996Inventor: Carlos J. R. P. Augusto
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Patent number: 5485804Abstract: A method for creating a uniform thin film of a high surface energy material on a substrate comprising the steps of providing an oppositely charged surface on the substrate, if such does not exist, from that of particles of the high surface energy material, exposing the substrate to an aqueous colloidal suspension of particles composed of the high surface energy material to adsorb seed particles onto the surface of the substrate, and then depositing a uniform thin film of the high surface energy material by chemical vapor deposition onto the seeded substrate.Type: GrantFiled: May 17, 1994Date of Patent: January 23, 1996Assignee: University of FloridaInventors: James J. Adair, Rajiv K. Singh
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Patent number: 5482002Abstract: A microprobe is provided which comprises a single crystal provided on a part of one main surface of a substrate or a part of a thin film formed on one main surface of the substrate. The microprobe may have a single crystal having an apex portion surrounded by facets having a specific plane direction and comprising a specific crystal face. The method for preparing the microprobe and an electronic device employing the microprobe also provided which is useful for recording and reproducing.Type: GrantFiled: July 8, 1993Date of Patent: January 9, 1996Assignee: Canon Kabushiki KaishaInventors: Hisaaki Kawade, Haruki Kawada, Kunihiro Sakai, Hiroshi Matsuda, Yuko Morikawa, Yoshihiro Yanagisawa, Tetsuya Kaneko, Toshimitsu Kawase, Hideya Kumomi, Hiroyasu Nose, Eigo Kawakami
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Patent number: 5474021Abstract: A plurality of single-crystalline diamond plates having principal surfaces consisting essentially of {100} planes are prepared. The diamond plates are so arranged that the respective principal surfaces are substantially flush with each other. In this arrangement, an angle formed by crystal orientations of the principal surfaces between adjacent plates is not more than 5.degree., a clearance between the adjacent plates is not more than 30 .mu.m, and a difference in height of the principal surfaces is not more than 30 .mu.m between the adjacent plates. To secure this arrangement, the plurality of diamond plates are joined to each other by depositing diamond on the plates to form a single large diamond plate. After such joining, the principal surfaces of the diamond plates are polished in order to eliminate steps or height differences. Then, diamond is epitaxially grown on a polished surface of the large diamond plate from a vapor phase.Type: GrantFiled: September 22, 1993Date of Patent: December 12, 1995Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takashi Tsuno, Takahiro Imai, Naoji Fujimori
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Patent number: 5471947Abstract: A method is disclosed for producing an oriented diamond film on a single crystal silicon substrate which comprises preconditioning the surface of the substrate by exposing the surface of the substrate to a carbon-containing plasma, subjecting the preconditioned surface to electrical bias to effect nucleation of the substrate surface for oriented diamond crystal growth while monitoring the completion of nucleation over the surface of the substrate and depositing crystalline diamond on the nucleated surface from a carbon-containing plasma. The resulting structure comprises a crystalline diamond film on the silicon substrate characterised by oriented columnar diamond crystals which form a substantially uniform tessellated pattern. In practice, the columnar crystals normally have a generally quadrilateral shape whose sides are mutually aligned.Type: GrantFiled: August 19, 1993Date of Patent: December 5, 1995Assignee: Kabushiki Kaisha Kobe Seiko ShoInventors: Paul Southworth, David S. Buhaenko, Peter J. Ellis, Carolyn E. Jenkins, Brian R. Stoner
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Patent number: 5457058Abstract: A crystal growth method for applying a crystallization treatment onto an amorphous film which includes injecting ions of the constituent material of the film into the film applied with the crystallization treatment provided with a mask to form a first region and a second region made amorphous by the ion injection, and growing a crystal from the first region to the second region by solid phase growth.Type: GrantFiled: December 30, 1992Date of Patent: October 10, 1995Assignee: Canon Kabushiki KaishaInventor: Takao Yonehara
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Patent number: 5423286Abstract: A method for forming a crystal comprises applying a crystal growth treatment to a substrate comprising:a non-nucleation surface; anda nucleation surface constituted of an amorphous material with a higher nucleation density than said non-nucleation surface, having a sufficiently small area so as to form only a single nucleus from which a single crystal is grown, and having regular anisotropy.Also a crystal article is formed by said method for forming a crystal.Type: GrantFiled: May 19, 1994Date of Patent: June 13, 1995Assignee: Canon Kabushiki KaishaInventor: Takao Yonehara
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Patent number: 5373806Abstract: Particles and particle-generated defects during gas phase processing such as during epitaxial deposition are substantially decreased by the process of controlling the various particle transport mechanisms, for example, by applying low level radiant energy during cold purge cycles in barrel reactors.Type: GrantFiled: March 14, 1994Date of Patent: December 20, 1994Assignee: Applied Materials, Inc.Inventor: Roger E. Logar
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Patent number: 5363799Abstract: A method for growth of a crystal wherein a monocrystalline seed is arranged on a substrate and a monocrystal is permitted to grow with the seed as the originating point, comprises the step of:(1) providing a substrate having a surface of smaller nucleation density;(2) arranging on the surface of the substrate primary seeds having sufficiently fine surface area to be agglomerated;(3) applying heat treatment to the primary seeds to cause agglomeration to occur, thereby forming a monocrystalline seed with a controlled face orientation; and(4) applying crystal growth treatment to permit a monocrystal to grow with the monocrystalline seed as the originating point.Type: GrantFiled: November 19, 1992Date of Patent: November 15, 1994Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Yuji Nishigaki, Kenji Yamagata