Preform In Hole Patents (Class 174/265)
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Patent number: 8278566Abstract: A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.Type: GrantFiled: February 2, 2009Date of Patent: October 2, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Hajime Kobayashi, Yasuyuki Yanase, Tetsuya Yamamoto, Yoshio Okayama
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Patent number: 8253034Abstract: Disclosed herein is a printed circuit board. The printed circuit board includes a base substrate including a first region on which a semiconductor chip is mounted and a second region positioned outside the first region, first insulating patterns covering the base substrate and including trenches formed on the second region, and second insulating patterns protruding from the first insulating patterns on the second region. The trench and the second insulating pattern may be used as a structure defining an underfill forming material in a preset shape during the process of forming an underfill.Type: GrantFiled: November 10, 2010Date of Patent: August 28, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Byoung Chan Kim, Young Hwan Shin, Chin Kwan Kim, Dong Won Kim, Kui Won Kang
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Patent number: 8253027Abstract: According to one embodiment of the invention, a circuit board comprises a conductive layer including a land portion and a line portion connected to the land portion, and; a conductor connected to a surface of the land portion. A planar shape of the connected portion between the conductor and the land portion has a elongated shape along a width direction of the line portion. A part of the connected portion is located within an imaginary region formed by imaginarily extending the line portion toward the land portion.Type: GrantFiled: February 24, 2010Date of Patent: August 28, 2012Assignee: Kyocera CorporationInventors: Kimihiro Yamanaka, Manabu Ichinose, Satoshi Nakamura
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Patent number: 8227711Abstract: A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided.Type: GrantFiled: August 18, 2010Date of Patent: July 24, 2012Assignee: Unimicron Technology CorporationInventor: Shih-Ping Hsu
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Patent number: 8217280Abstract: A circuit board includes a substrate, a circuit pattern and a through electrode. The circuit pattern is disposed on one side of the substrate in a thickness direction thereof. The through electrode is filled in a through-hole formed in the substrate with one end connected to the circuit pattern. The circuit pattern and the through electrode each have an area containing a noble metal component (e.g., Au component) and are connected to each other therethrough.Type: GrantFiled: January 31, 2011Date of Patent: July 10, 2012Assignee: Napra Co., Ltd.Inventors: Shigenobu Sekine, Yurina Sekine, Yoshiharu Kuwana
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Patent number: 8207453Abstract: Disclosed are embodiments of a glass core substrate for an integrated circuit (IC) device. The glass core substrate includes a glass core and build-up structures on opposing sides of the glass core. Electrically conductive terminals may be formed on both sides of the glass core substrate. An IC die may be coupled with the terminals on one side of the substrate, whereas the terminals on the opposing side may be coupled with a next-level component, such as a circuit board. The glass core may comprise a single piece of glass in which conductors have been formed, or the glass core may comprise two or more glass sections that have been joined together, each section having conductors. The conductors extend through the glass core, and one or more of the conductors may be electrically coupled with the build-up structures disposed over the glass core. Other embodiments are described and claimed.Type: GrantFiled: December 17, 2009Date of Patent: June 26, 2012Assignee: Intel CorporationInventors: Qing Ma, Quan A. Tran, Robert L. Sankman, Johanna M. Swan, Valluri R. Rao
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Patent number: 8188379Abstract: A package substrate structure includes: a substrate having a first surface and an opposing second surface and characterized by a plurality of wire-bonding pads provided on the first surface of the substrate, a plurality of ball-implanting pads provided on the second surface of the substrate, and at least a cavity formed to penetrate the first and second surfaces of the substrate; a metal board mounted on the second surface of the substrate and covering the cavity, wherein the metal board has a thickness greater than that of the ball-implanting pads and has an area greater than that of the cavity; and solder masks disposed on the first and second surfaces of the substrate respectively and having at least a solder-mask cavity corresponding in position to the cavity of the substrate, the solder masks further having a plurality of openings for exposing the wire-bonding pads, the ball-implanting pads and the metal board.Type: GrantFiled: June 30, 2009Date of Patent: May 29, 2012Assignee: Unimicron Technology Corp.Inventor: Shin-Ping Hsu
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Patent number: 8124885Abstract: An anisotropically conductive connector and an anisotropically conductive connector device. The anisotropically conductive connector includes a supporting member, a plurality of through-holes each extending in a thickness-wise direction of the supporting member, and anisotropically conductive sheets respectively held in the through-holes of the supporting member. Each anisotropically conductive sheet includes a frame plate, a plurality of through-holes each extending in a thickness-wise direction of the frame plate, and a plurality of anisotropically conductive elements arranged in the respective through-holes of the frame plate. Each of the anisotropically conductive elements includes a conductive part, conductive particles contained in an elastic polymeric substance in a state oriented so as to align in a thickness-wise direction of the element, and an insulating part to cover the outer periphery of the conductive part and including an elastic polymeric substance.Type: GrantFiled: March 30, 2007Date of Patent: February 28, 2012Assignee: JSR CorporationInventors: Daisuke Yamada, Kiyoshi Kimura
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Patent number: 8115108Abstract: The insulation base side of single-sided FPC is turned to the die side, and the mounting surface side of ground circuit is turned to the upper side, and the FPC is placed on die (a). When the portion of ground circuit where the conduction is realized and metal reinforcing plate are punched by punch of which the clearance dimension is made to be 50 to 95% of the thickness of the material to be punched, hole sagging will be formed (b). The insulation base 1 side is turned up, electrically conductive adhesive and metal reinforcing plate are laminated in this order, heating pressing is performed with the press apparatus for metal reinforcing plate to be laminated (c). Thereby, laminated FPC is formed (d). At this time, since electrically conductive adhesive is injected into hole sagging by press pressing, the electrical connection of metal reinforcing plate and ground circuit can be attained by the interlaminar conduction by means of electrically conductive adhesive, and there is also no residual air.Type: GrantFiled: November 14, 2008Date of Patent: February 14, 2012Assignee: Nippon Mektron, Ltd.Inventor: Nobuyuki Sakai
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Patent number: 8109768Abstract: A connector is provided that includes: a molded base part having a substrate and elastomers arranged on both sides of the substrate; a plurality of through holes in the molded base part, which pass through the molded base part in a stacked direction of the substrate and the elastomers, and are arranged in parallel at predetermined spacing; and L-shaped contacts arranged via the through holes from one surface side of the molded base part to another surface side, wherein: the elastomers incorporate a plurality of first protruding parts whose top faces are inclined, and second protruding parts that protrude from top faces of the first protruding parts in a dome shape; said contact has dome shaped convex parts whose insides are hollow, and said convex parts are formed at two ends of the contact, and the convex parts are arranged such that they cover the respective second protruding parts. Also provided is an electronic component provided with this connector.Type: GrantFiled: July 30, 2009Date of Patent: February 7, 2012Assignee: Fujikura Ltd.Inventors: Shinichi Nikaido, Haruo Miyazawa
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Patent number: 8110752Abstract: A method for manufacturing a wiring substrate includes forming a conductor circuit on an insulating layer, the conductor circuit including a pad, a circuit pattern connected to the pad, and a lead pattern connected to the pad. A solder resist layer is formed on the circuit pattern and on the insulating layer, and a plating resist layer is formed on the lead pattern and on the insulating layer and forming a metal film on a first portion of the conductor circuit not covered by the solder resist layer and not covered by the plating resist layer. The plating resist layer is removed to expose a second portion of the conductor circuit adjacent to the first portion of the conductor circuit and not covered with the metal film, and an etching resist layer is formed on the metal film and on the second portion of the conductor circuit. A third portion of the conductor circuit not covered by the etching resist layer is removed by etching, and the etching resist is removed.Type: GrantFiled: March 30, 2009Date of Patent: February 7, 2012Assignee: Ibiden Co., Ltd.Inventors: Fusaji Nagaya, Nobuhisa Kuroda, Atsushi Awano
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Patent number: 8102057Abstract: Provided is an electrically conductive via for reducing flux residue. The via has a first aperture having a first diameter size. The via further has a second aperture having a second diameter size. A chamber is disposed between the first aperture and the second aperture, the chamber having a third diameter size. At least one of the diameters being of a different dimension than the other two. In addition, the via may also provide improved test point access in addition to reducing flux residue.Type: GrantFiled: December 27, 2006Date of Patent: January 24, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventors: Alexander Leon, Rosa Reinosa, Michael David Carothers, Glen Griffiths
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Patent number: 8093506Abstract: A multilayer wiring board capable of feeding sufficient electric power to a circuit element, such as an IC chip. In one embodiment of the present invention, a multilayer wiring board is comprised of: a core board; a build up layer disposed on an upper surface of the core board; a build up layer disposed on a lower surface of the core board; and a power supply structure embedded in a through hole penetrating the core board and the build up layers. The power supply structure is comprised of: a conductive metal rod made of copper as a main material; a conductive metal tube made of copper as a main material and provided coaxially with the conductive metal rod; and an insulating material filling a gap between the conductive metal rod and the conductive metal tube.Type: GrantFiled: November 26, 2007Date of Patent: January 10, 2012Assignee: NGK Spark Plug Co., Ltd.Inventor: Tadahiko Kawabe
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Patent number: 8089007Abstract: A printed circuit board includes a reference layer, at least one first hole defined in the reference layer and adjacent from a first pin in a first column of pins of an electronic component, and at least one second hole defined in the reference layer and adjacent from a second pin of the electronic component. The at least one second hole is defined in the reference layer and opposite to the at least one first hole. The second pin is in a neighboring second column of pins from the first column of pins. A diameter of the at least one first hole is greater than a diameter of the at least one second hole such that a difference in current flowing through the first pin and the second pin is reduced.Type: GrantFiled: December 10, 2008Date of Patent: January 3, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Tso Lai, Tsung-Sheng Huang, Shou-Kuo Hsu
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Patent number: 8076586Abstract: This publication discloses a circuit-board construction and a method for manufacturing an electronic module, in which method at least one component (6) is embedded inside an insulating-material layer (1) and contacts (14) are made to connect the component (6) electrically to the conductor structures (14, 19) contained in the electronic module. According to the invention, at least one thermal via (22), which boosts the conducting of heat away from the component (6) is manufactured in the insulating-material layer (1) in the vicinity of the component (6).Type: GrantFiled: April 27, 2005Date of Patent: December 13, 2011Assignee: Imbera Electronics OyInventors: Risto Tuominen, Petteri Palm
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Patent number: 8067700Abstract: A printed circuit board (200) includes at least one via (280) defined therein, the via has an upper cap (220) formed on a top surface of the PCB, and a lower cap (240) formed on a bottom surface of the PCB. A conductive hole (290) is defined in the PCB having a plated sidewall (230) plated on its inner surface, and a first clearance hole (271) is defined in a first inner layer (260) of the PCB around the sidewall. A first transmission line (210) defined on the top surface of the PCB is coupled to the upper cap, a first void (273) extending from a boundary of the first clearance hole being disposed along the layout direction of the first transmission line.Type: GrantFiled: October 30, 2007Date of Patent: November 29, 2011Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Yu-Chang Pai, Shou-Kuo Hsu, Chien-Hung Liu
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Publication number: 20110271757Abstract: A wiring substrate includes: a substrate having a first surface and a second surface; a first insulating layer stacked on the first surface; a pad electrode stacked on the first insulating layer; a through electrode connected to the pad electrode; and a second insulating layer disposed between the substrate and the through electrode and between the first insulating layer and the through electrode, wherein a diameter of the through electrode in a connection section between the pad electrode and the through electrode is smaller than a diameter of the through electrode on the second surface side, the first insulating layer, the second insulating layer and the through electrode overlap with each other in a peripheral area of the connection section, when seen from a plan view, and the thickness of the first insulating layer in the area is thinner than the thickness of the first insulating layer in other areas.Type: ApplicationFiled: April 11, 2011Publication date: November 10, 2011Applicant: SEIKO EPSON CORPORATIONInventor: Tsuyoshi YODA
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Patent number: 8053682Abstract: There is provided a multilayer ceramic substrate including a conductive via of a dual-layer structure capable of preventing loss in electrical conductivity and signal. The multilayer ceramic substrate includes: a plurality of dielectric layers; and a circuit pattern part formed on at least a portion of the dielectric layers, the circuit pattern part including at least one conductive via and conductive pattern, wherein the at least one conductive via comprises an outer peripheral portion and an inner peripheral portion, the outer peripheral portion formed along an inner wall of a via hole extending through the dielectric layers and formed of a first conductive material containing a metal, and the inner peripheral portion filled in the outer peripheral portion and formed of a second conductive material having a shrinkage initiation temperature higher than a shrinkage initiation temperature of the first conductive material.Type: GrantFiled: May 18, 2009Date of Patent: November 8, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Yun Hwi Park, Bong Gyun Kim, Yoon Hyuck Choi
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Patent number: 8044306Abstract: A wiring board has a base substrate, a conductive pattern formed on the base substrate, an insulation layer formed on the conductive pattern and the base substrate and including a resin-impregnated inorganic cloth, a conductive pattern formed on the insulating layer, a via formed in the insulation layer and connecting the conductive pattern formed on the base substrate and the conductive pattern formed on the insulating layer, and a through-hole connected to the conductive pattern formed on the base substrate, penetrating through the base substrate and having a hole diameter in a range of 10 ?m to 150 ?m.Type: GrantFiled: April 29, 2008Date of Patent: October 25, 2011Assignee: Ibiden Co., Ltd.Inventor: Michimasa Takahashi
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Publication number: 20110240347Abstract: A shielded signal pass-through or via structure integral with an electronic circuit board is described. The structure includes a rigid inner generally cylindrical conductor; at least a semi-rigid intermediate annular dielectric surrounding the conductor; and a rigid outer annular conductor surrounding the dielectric material. Also described is an interconnect device that presents a contact array in a boss region of a unitary embossed printed circuit board (PCB) optionally equipped with one or more such shielded vias.Type: ApplicationFiled: January 28, 2011Publication date: October 6, 2011Applicant: TEKTRONIX, INC.Inventors: Brian S. MANTEL, David T. ENGQUIST
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Patent number: 8000107Abstract: A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate.Type: GrantFiled: March 28, 2008Date of Patent: August 16, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Hui Wang, In-De Ou, Chih-Pin Hung
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Patent number: 7956292Abstract: A printed circuit board manufacturing method includes: a hole-forming step of forming a through hole in a substrate that will become an element of a printed circuit board after manufacturing; and a jig insertion step of inserting a jig in the through hole formed in the hole-forming step such that the jig adheres to a portion of an inner wall of the through hole, the inner wall having a portion connecting to the outside of the through hole. The method further includes a conductive-film forming step of forming a conductive film only on the portion of the inner wall of the through hole connecting to the outside of the through hole, after the jig is inserted into the through hole in the jig insertion step.Type: GrantFiled: December 13, 2007Date of Patent: June 7, 2011Assignee: Fujitsu LimitedInventor: Mitsuhiko Sugane
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Patent number: 7944710Abstract: The disclosure involves the efficient termination of a winding PCB of a planar inductive component to a main PCB, using relatively little space and providing a low-resistance connection. The disclosed methods are especially suitable for planar structures where several winding PCBs, and/or winding PCBs and a main PCB, are all enclosed by the magnetic path components. The methods allow for a winding PCB to simply rest on the main PCB, or other winding PCBs, without any clearance. The disclosure employs mating sets of conductive annular rings with an optional interlocking terminal pin that allows two PCBs to be fixedly coupled together, while preserving a minimum distance between the solder-mask layers of the two PCBs in order to prevent the formation of unwanted electrical connections between the two PCBs. Solder is used to ensure effective coupling in each assembly of mating annular rings and optional terminal pin.Type: GrantFiled: October 6, 2008Date of Patent: May 17, 2011Assignee: Battery-Biz Inc.Inventors: Victor Marten, Aakar Patel, Mark Vanstone
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Patent number: 7897880Abstract: Plated through holes pass through clearances in a ground plane of a circuit board. A conductive collar/spoke arrangement is constructed on the ground plane adjacent the clearance, to provide an inductive component to the coupling between a plated through hole and the ground plane. The inductive component impedes the transfer of high-frequency noise between the through hole and the ground plane. Other embodiments are also described and claimed.Type: GrantFiled: December 7, 2007Date of Patent: March 1, 2011Assignee: Force 10 Networks, IncInventors: Joel R. Goergen, Greg Hunt, Peter Tomaszewski, Joseph Pankow, Michael Laudon
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Patent number: 7852635Abstract: The present invention provides a PWB for attaching electrical components thereto. One aspect of the PWB includes multiple PWB insulating layers having conductive traces therebetween. The PWB has an interconnect opening located in the multiple PWB insulating layers that intersect at least a portion of the conductive traces. The interconnect opening has ledges therein, wherein each of the ledges separates a first group of the conductive traces from a second group of the conductive traces. The present invention also provides a method of making the PWB and also provides a power converter implementing the edge plate interconnects.Type: GrantFiled: May 25, 2004Date of Patent: December 14, 2010Assignee: Lineage Power CorporationInventors: Galliano R. Busletta, Robert J. Roessler
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Patent number: 7851709Abstract: A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.Type: GrantFiled: January 5, 2007Date of Patent: December 14, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Hung-Hsiang Cheng
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Patent number: 7836590Abstract: A manufacturing method for a printed circuit board is disclosed. The method includes: forming a first circuit pattern on a metal layer of a conductive carrier, which has the metal layer stacked on one side, pressing the conductive carrier and a first insulation layer together with the first circuit pattern facing the first insulation layer, forming a via by selectively removing the conductive carrier, and removing the metal layer. Using this method, a high-density thin package can be manufactured with increased reliability, and the productivity of the manufacturing process can also be improved.Type: GrantFiled: February 1, 2008Date of Patent: November 23, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jee-Soo Mok, Jun-Heyoung Park
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Patent number: 7829793Abstract: An additive process disk drive suspension interconnect, and method therefor is provided. The interconnect has a metal grounding layer of typically stainless steel or copper metallized stainless steel, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.Type: GrantFiled: July 13, 2006Date of Patent: November 9, 2010Assignee: Magnecomp CorporationInventors: Christopher Schreiber, Christopher Dunn
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Patent number: 7790985Abstract: Methods and devices are provided for repairing a damaged contact pad that is located on a first surface of a printed circuit board and connected to a via that passes through the circuit board. According to the method, a countersink hole is created in the first surface of the printed circuit board in a location that is substantially centered on an axis passing through the via, and a replacement structure is inserted into the countersink hole. The replacement structure has a stem portion, a head portion, and a shoulder portion that connects the stem and head portions, with the angle of the shoulder portion substantially matching the angle of the shoulder of the countersink hole. The stem portion of the replacement structure is permanently attached to sidewalls of the via so as to electrically couple the head portion of the replacement structure to the via.Type: GrantFiled: June 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Joseph P. Palmeri, Vincent P. Mulligan
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Patent number: 7782629Abstract: A pre-drilled hole, providing a passageway between an upper and a lower surface of a printed circuit board layer, receives a passive component, for example a resistor or a capacitor. In one embodiment the component is cylindrical, with an electrically conductive contact point at each end. The hole diameter is approximately the same as the diameter of the cylindrical component. The hole is similar to a via in a printed circuit board, except that the hole is not plated through (such would cause an electrical short). Electrically conductive lines are provided to the openings of the hole on the upper and the lower surfaces of the PCB. The area of the exposed end of the cylindrical component and the termination of the conducting line is less than the area of a surface mounted component equivalent to the cylindrical component.Type: GrantFiled: July 25, 2007Date of Patent: August 24, 2010Assignee: Flextronics AP, LLCInventors: Bhret Graydon, William Kuang-Hua Shu
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Patent number: 7781679Abstract: A disk drive suspension interconnect, and method therefor. The interconnect has a metal grounding layer, a metal conductive layer and an insulative layer between the metal grounding layer and the conductive metal layer. A circuit component such as a slider is electrically connected to the conductive layer along a grounding path from the circuit component and the conductive layer to the metal grounding layer through an aperture in the insulative layer. For improved electrical connection a tie layer is provided through the insulative layer onto the grounding layer in bonding relation with the ground layer. A conductor is deposited onto both the conductive metal layer and the tie layer in conductive metal layer and tie layer bonding relation, and the circuit component is thus bonded to the grounding layer by the conductor.Type: GrantFiled: January 26, 2006Date of Patent: August 24, 2010Assignee: Magnecomp CorporationInventors: Christopher Schreiber, Christopher Dunn
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Patent number: 7767914Abstract: A multilayer printed wiring board includes: an insulating base including an indentation section formed thereon; a conductor pattern formed on the insulating base, the conductor pattern including a thick film section formed by embedding a conductor in the indentation section; and a via hole section formed in an upper layer of the insulating base, the via hole section including a bottom portion that is in contact with the thick film section.Type: GrantFiled: August 26, 2008Date of Patent: August 3, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kenji Hasegawa
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Patent number: 7760512Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.Type: GrantFiled: May 24, 2006Date of Patent: July 20, 2010Assignee: Seiko Epson CorporationInventor: Nobuaki Hashimoto
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Patent number: 7750250Abstract: A capture pad structure includes a lower dielectric layer, a capture pad embedded within the lower dielectric layer, the capture pad comprising a plurality of linear segments. To form the capture pad, a focused laser beam is moved linearly to form linear channels in the dielectric layer. These channels are filled with an electrically conductive material to form the capture pad.Type: GrantFiled: December 22, 2006Date of Patent: July 6, 2010Assignee: Amkor Technology, Inc.Inventor: Bob Shih-Wei Kuo
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Patent number: 7733663Abstract: A multilayer ceramic substrate includes a plurality of ceramic layers laminated each other. The plurality of ceramic layers form a bulge and a cavity having such a shape that an opening area of the cavity gradually becomes smaller toward a bottom of the cavity.Type: GrantFiled: April 29, 2008Date of Patent: June 8, 2010Assignee: TDK CorporationInventors: Kenji Endou, Kiyoshi Hatanaka, Masaharu Hirakawa, Haruo Nishino, Hideaki Fujioka
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Patent number: 7703064Abstract: A multilayered board data input unit inputs design data of a multilayered circuit board provided with through holes penetrating and mutually connecting solid-layer conductors disposed in a multilayer manner. A limitation rule setting unit sets a limitation rule for limiting the number of solid-layer conductors to be connected to the through holes. A separation processing unit separates connections of the solid-layer conductors to the through holes in the design data based on the limitation rule. At this time, when a solid-layer conductor to be separated from the through holes is selected as a candidate, the separation processing unit determines whether the solid-layer conductor is isolated by separation, when the solid-layer conductor is not isolated, determines isolation, and when the solid-layer conductor is isolated, stops separation.Type: GrantFiled: December 20, 2005Date of Patent: April 20, 2010Assignee: Fujitsu LimitedInventors: Takayuki Ashida, Kenichirou Tsubone
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Patent number: 7700885Abstract: A wiring board (1, 1a, 20, 20a) having: a board body (2, 22) including an insulating material and having a front surface (3, 23), a back surface (4, 24), a cavity (5, 25) having an opening in the front surface (3, 23) of the board body (2, 22) and having a bottom surface (6, 26) and a side surface (7, 27), and a projection which is provided on a front surface side of the side surface (7, 27) of the cavity and projects toward a center of the opening; a metal layer (11) provided on the side surface (7, 27) of the cavity; and an insulating portion which is provided on a back surface (9, 29) of the projection (8, 28) so as to define an obtuse angle (?) with the metal layer (11), or which covers at least a top end portion of the metal layer (11).Type: GrantFiled: April 25, 2006Date of Patent: April 20, 2010Assignee: NGK Spark Plug Co., Ltd.Inventors: Makoto Nagai, Hisashi Wakako, Atsushi Uchida, Masahito Morita
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Patent number: 7674989Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.Type: GrantFiled: June 9, 2006Date of Patent: March 9, 2010Assignees: NEC Electronics Corporation, NEC CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
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Patent number: 7667141Abstract: The present invention discloses a flexible printed circuit (FPC) layout and a method thereof.Type: GrantFiled: July 25, 2008Date of Patent: February 23, 2010Assignee: Wintek CorporationInventors: Ying-Fang Xu, Ning-Hua Li, Chin-Mei Huang, Tsui-Chuan Wang
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Publication number: 20100038127Abstract: An apparatus that includes a plurality of metalized planes, one or more dielectric layers separating the plurality of metalized planes; and one or more conductive trenches connecting to at least one of the plurality of metalized planes.Type: ApplicationFiled: October 23, 2009Publication date: February 18, 2010Inventors: Gary A. Brist, Gary Baxter Long, Daryl A. Sato
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Patent number: 7652896Abstract: A component for insertion into a hole in a multiple-layer substrate enables impedance matching of the substrate. The component comprises a conductive ground core arranged to extend through multiple-layers of the substrate when the component is inserted, a dielectric layer laterally encasing the conductive ground core, and a signal conductor layer coupled lateral to the dielectric layer.Type: GrantFiled: December 29, 2004Date of Patent: January 26, 2010Assignee: Hewlett-Packard Development Company, L.P.Inventors: Sachin Navin Chheda, Kirk Yates, Nitin C. Bhagwath
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Patent number: 7624501Abstract: First, a plurality of wiring boards are fabricated at separate steps. The first wiring board includes a Cu post formed on a wiring layer on one surface of a substrate, and a first stopper layer formed at a desired position around the Cu post. The second wiring board includes a through hole for insertion of the Cu post therethrough, a connection terminal formed on a wiring layer on one surface of a substrate, and a second stopper layer that engages the first stopper layer and functions to suppress in-plane misalignment. The third wiring board includes a connection terminal formed on a wiring layer on one surface of a substrate. Then, the wiring boards are stacked up, as aligned with one another so that the wiring layers are interconnected via the Cu post and the connection terminals, to thereby electrically connect the wiring boards. Thereafter, resin is filled into gaps between the wiring boards.Type: GrantFiled: February 5, 2008Date of Patent: December 1, 2009Assignee: Shinko Electric Industries Co., Ltd.Inventor: Yoshihiro Machida
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Patent number: 7624502Abstract: A conductive portion is formed in a hole formed in a material sheet. A metal foil is placed on a surface of the material sheet to provide a laminated sheet. The laminated sheet is heated and pressed to provide a circuit-forming board. The metal foil includes a pressure absorption portion and a hard portion adjacent to the pressure absorption portion. The pressure absorption portion has a thickness changing according to a pressure applied thereto. The circuit-forming board provided by this method provides a high-density circuit board of high quality having reliable electrical connection.Type: GrantFiled: January 21, 2005Date of Patent: December 1, 2009Assignee: Panasonic CorporationInventor: Toshihiro Nishii
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Patent number: 7615708Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between any two of the contact pads electrically connected to the corresponding first non-signal through vias.Type: GrantFiled: May 30, 2006Date of Patent: November 10, 2009Assignee: VIA Technologies, Inc.Inventors: Hsing-Chou Hsu, Ying-Ni Lee
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Patent number: 7603645Abstract: A calibration method of insulating washer in a circuit board is provided, which includes steps of (a) establishing an equivalent circuit model corresponding to a metal via; (b) depicting an electric characteristic curve corresponding to the model; (c) calculating a capacitance and an inductance equation corresponding to the curve; (d) substituting parameter values of the equivalent circuit model, capacitance equation, and inductance equation into a characteristic impedance expression for being calculated, so as to obtain a first radius length value of an insulating washer for the metal via; (e) making a temporary insulating washer by employing the value; (f) reestablishing an equivalent circuit model corresponding to the metal via according to the temporary insulating washer; repeating Steps (b), (c), (d), (e), and (f); and when the first radius length value is converged into a fixed value, determining the fixed value as an optimum value for designing the insulating washer.Type: GrantFiled: January 29, 2007Date of Patent: October 13, 2009Assignee: Inventec CorporationInventors: Yu-Li Su, Chun-Yu Lai
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Publication number: 20090200074Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.Type: ApplicationFiled: February 12, 2008Publication date: August 13, 2009Applicant: International Business Machines CorporationInventors: Daniel Douriet, Francesco Preda, Brian L. Singletary, Lloyd A. Walls
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Patent number: 7570493Abstract: In one embodiment, a printed circuit board includes a plurality of insulating layers in which an aperture is formed through some of the layers. A resistive plug at least partially fills the aperture and contacts respective conductive members at each end of the resistive plug to form a resistive via that traverses partially through the printed circuit board. In another embodiment, a printed circuit board includes a plurality of insulating layers in which an aperture is formed through at least some of the layers. A dielectric plug at least partially fills the aperture and contacts respective conductive members at each end of the dielectric plug to form a capacitive via that traverses at least partially through the printed circuit board.Type: GrantFiled: November 16, 2006Date of Patent: August 4, 2009Assignee: Sony Ericsson Mobile CommunicationsInventor: Ulf G. Karlsson
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Publication number: 20090145652Abstract: The present invention has for its object to provide a process for manufacturing multilayer printed circuit boards which is capable of simultaneous via hole filling and formation of conductor circuit and via holes of good crystallinity and uniform deposition can be constructed on a substrate and high-density wiring and highly reliable conductor connections can be realized without annealing.Type: ApplicationFiled: September 26, 2008Publication date: June 11, 2009Applicant: IBIDEN CO., LTD.Inventors: Honchin En, Tohru Nakai, Takeo Oki, Naohiro Hirose, Kouta Noda
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Patent number: 7508681Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.Type: GrantFiled: June 12, 2007Date of Patent: March 24, 2009Assignee: Amphenol CorporationInventors: Jason J. Payne, Mark W. Gailus, Leon M. Khilchenko, Huilin Ren
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Patent number: RE41051Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600 ?m in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.Type: GrantFiled: June 25, 2004Date of Patent: December 22, 2009Assignee: IBIDEN Co., Ltd.Inventors: Motoo Asai, Yoji Mori