Preform In Hole Patents (Class 174/265)
  • Patent number: 7491896
    Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: February 17, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Patent number: 7491895
    Abstract: A wiring substrate is provided with an insulating resin film; and first and second conductive films provided on the back side and top side of the insulating resin film, respectively. The wiring substrate includes a via formed to fill a recess provided in the insulating resin film and electrically connecting the top side and back side of the insulating resin film. The via includes a first metal film formed to cover the side wall of the recess, an oxide film formed to cover the first meal film, and a second metal film formed on the metal oxide film.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: February 17, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Takeshi Nakamura
  • Patent number: 7470864
    Abstract: A multi-conducting through hole structure is provided. The multi-conducting through hole structure has a substrate, at least two signal lines and at least a reference line. The substrate has a through hole passing therethrough. The signal lines are disposed on a portion of an inner surface of the through hole and extended through the through hole. The reference line is disposed on a portion of the inner surface of the through hole and extended through the through hole, wherein the reference line is disposed between the lines for signal. Because the signal lines are separated by the reference line, the electromagnetic coupling generated by signals can be reduced to lower the cross-talk interference between signals passing through the through hole, so as to promote the signal-transmission quality.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: December 30, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Kwun-Yao Ho, Moriss Kung, Chi-Hsing Hsu, Jimmy Hsu
  • Patent number: 7456364
    Abstract: A printed circuit board includes multiple layers on which electrically conductive traces reside, where at least two of the electrically conductive traces each has a first portion formed on one layer of the printed circuit board and a second portion formed on another layer of the printed circuit board. The printed circuit board also includes a thru-hole via that includes at least two electrically conductive portions electrically isolated from each other, such that each of the electrically conductive portions connects electrically to both the first and second portions of a corresponding one of the electrically conductive traces.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: November 25, 2008
    Assignee: Teradata US, Inc.
    Inventors: James Knighten, Jun Fan, Norman Smith
  • Publication number: 20080230264
    Abstract: The present invention discloses an interconnection structure which is formed by a method comprising providing a first conductive substrate, a second conductive substrate, and an insulating substrate; respectively forming a first circuit and a second circuit on the first conductive substrate and the second conductive substrate; forming a conductive bump on the second circuit; and connecting the insulating substrate with the first circuit and the second circuit by pressing the first conductive substrate, the insulating substrate and the second conductive substrate, wherein the conductive bump penetrates the insulating substrate to contact the first circuit.
    Type: Application
    Filed: March 10, 2008
    Publication date: September 25, 2008
    Applicant: MUTUAL-TEK INDUSTRIES CO., LTD.
    Inventor: Jung-Chien Chang
  • Patent number: 7420126
    Abstract: A circuit board and a circuit apparatus using the same are provided, which have an improved heat radiation capability near through holes piercing through its metal substrate so as to address a requirement as to heat radiation capability. The circuit apparatus has the circuit board in which a metal substrate having pierced holes is formed as a core member. Protrusions are formed at the top ends of the pierced holes, and round corners are formed at the bottom ends of the same. Insulating layers are formed on both sides of the metal substrate, and wiring pattern layers are formed on the respective insulating layers. The insulator formed on one side of the metal substrate and the insulator formed on the other side of the metal substrate are extended to inside the pierced holes. The joining surface between the extended portions is shifted off the center position of the metal substrate in the thickness direction, toward the same side as where the protrusions are formed.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: September 2, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiyoshi Shibata, Ryosuke Usui
  • Publication number: 20080185179
    Abstract: Disclosed are an electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit. The electromagnetic bandgap structure in which a first metal layer, a first dielectric layer, a second dielectric layer and a second metal layer are stacked can include a first metal plate, formed between the first dielectric layer and the second dielectric layer; a second metal plate, formed on a same planar surface as the first metal plate, accommodated into a hole which is formed in the first metal plate and electrically connected to the first metal plate through a metal line; and a via, connecting the second metal plate to any one of the first metal layer and the second metal layer. With the present invention, the electromagnetic bandgap structure can be not only miniaturized but also have a low bandgap frequency.
    Type: Application
    Filed: January 30, 2008
    Publication date: August 7, 2008
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Han Kim, Jae-Joon Lee, Mi-Ja Han, Dae-Hyun Park
  • Patent number: 7408120
    Abstract: Disclosed is a PCB having axially parallel via holes, in which an outer ground via hole, acting as a ground, is formed around a via hole for intercircuit connection in the PCB, thereby minimizing the effect of noise caused by the via hole.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: August 5, 2008
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Woo Kim, Byoung Youl Min, Chang Myung Ryu, Han Kim
  • Patent number: 7402760
    Abstract: A multi-layer printed wiring board has a core substrate, a throughhole structure, a first interlayer insulation layer, a first via, a second interlayer insulation layer and a second via. The core substrate has a throughhole opening, and the throughhole structure is formed in the throughhole opening. The first interlayer insulation layer is formed over the core substrate. The first via is formed in the first interlayer insulation layer and has a bottom portion having a first radius. The second interlayer insulation layer is formed over the first interlayer insulation layer and the first via. The second via is formed in the second interlayer insulation layer and has a bottom portion having a second radius greater than the first radius.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 22, 2008
    Assignee: IBIDEN Co., Ltd.
    Inventor: Youhong Wu
  • Patent number: 7399930
    Abstract: Methods and devices are provided for repairing a damaged contact pad that is located on a first surface of a printed circuit board and connected to a via that passes through the circuit board. According to the method, a countersink hole is created in the first surface of the printed circuit board in a location that is substantially centered on an axis passing through the via, and a replacement structure is inserted into the countersink hole. The replacement structure has a stem portion, a head portion, and a shoulder portion that connects the stern and head portions, with the angle of the shoulder portion substantially matching the angle of the shoulder of the countersink hole. The stem portion of the replacement structure is permanently attached to sidewalls of the via so as to electrically couple the head portion of the replacement structure to the via.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Joseph P. Palmeri, Vincent P. Mulligan
  • Publication number: 20080156523
    Abstract: A printed-wiring board includes: a board made of insulator; a wiring pattern to transfer an electric signal which is made of patterned metallic conductor and formed on at least one of a main surface and a rear surface of the board; and an electric power layer formed on the rear surface of the board and/or in the board. The electric power layer includes a mechanism to increase and decrease a capacitance and an inductance thereof.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 3, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Shinichiro SAITO
  • Publication number: 20080149384
    Abstract: A multilayer wiring board capable of feeding sufficient electric power to a circuit element, such as an IC chip. In one embodiment of the present invention, a multilayer wiring board is comprised of: a core board; a build up layer disposed on an upper surface of the core board; a build up layer disposed on a lower surface of the core board; and a power supply structure embedded in a through hole penetrating the core board and the build up layers. The power supply structure is comprised of: a conductive metal rod made of copper as a main material; a conductive metal tube made of copper as a main material and provided coaxially with the conductive metal rod; and an insulating material filling a gap between the conductive metal rod and the conductive metal tube.
    Type: Application
    Filed: November 26, 2007
    Publication date: June 26, 2008
    Inventor: Tadahiko Kawabe
  • Patent number: 7378601
    Abstract: A signal transmission structure is provided. The structure mainly comprises at least a conductive via, at least a via land and a conductive wall. One end of the conductive via is connected to the via land. The conductive wall covers only a portion of the inner wall of a through hole in the core layer of a circuit substrate. The conductive wall has a semi-circular or a C-shaped structure. Therefore, when a signal passes the conductive via and the via land of the circuit substrate through the conductive wall in the interior of the via, because of a more continuous impedance between the via land and the conductive wall, signal reflection due to impedance mismatch along the signal transmission pathway can be reduced to enhance signal transmission quality.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: May 27, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Jimmy Hsu, Chi-Hsing Hsu
  • Patent number: 7365272
    Abstract: A circuit board with identifiable information and a method for fabricating the same are proposed. At least one insulating layer within the circuit board has a non-circuit area free of a circuit layout. A plurality of openings are formed in the non-circuit area of the insulating layer. A patterned circuit layer is formed on the insulating layer. Metal identifiable information is disposed in the openings of the non-circuit area. By this arrangement, a product status of the circuit board can be traced and identified via the metal patterned information.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: April 29, 2008
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Shang-Wei Chen, Suo-Hsia Tang, Chao-Wen Shih
  • Publication number: 20080060839
    Abstract: Contacts (16) of a circuit component (12) have contact top regions (30) that extend down close to the upper face of a circuit board, and have contact inboard regions (32) that each lies primarily in a plated circuit board hole (34), wherein each contact is formed of bent sheet metal. The contact has a box-shaped cross-section along most of its length, which includes rear and front walls (40, 41) and first and second side walls (42, 44). Along the inboard region, the first side wall has a forward extension (90) that is bent by 90° to form a front wall with a free edge (94) that lies against the front (52) of the second side wall. Along a lower portion of the top region the side walls have forward projections (64, 66) that form upper shoulders (60, 62) for receiving downward forces to press the inboard portions down into the circuit board holes.
    Type: Application
    Filed: September 12, 2006
    Publication date: March 13, 2008
    Inventor: Woody Wurster
  • Patent number: 7342470
    Abstract: A microwave filter has resonator comprised of a cylindrical structure having conductive walls filled with a dielectric material where the cylindrical structure is recessed inside a multi-layered substrate. First and second conductive coupling arms are disposed on a top layer of the substrate for coupling signals to the cylindrical structure. The conductive coupling arms are separated by a dielectric layer. The first and second conductive coupling arms extend away from the center of the cylindrical structure to form a microstrip line. The cylindrical structure further comprises a bottom portion having a solid conductive bottom plate perpendicular to the axis of the cylinder and a bottom conductive ground layer separated from the conductive bottom plate by a second dielectric layer.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: March 11, 2008
    Inventor: Fred Bassali
  • Patent number: 7342802
    Abstract: To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an interlayer insulating film allows for interlayer connection between plural wiring films insulated from one another with plural interlayer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the interlayer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 ?m or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: March 11, 2008
    Assignee: Tessera Interconnect Materials, Inc.
    Inventors: Tomoo Iijima, Yoshitaka Fukuoka
  • Patent number: 7334324
    Abstract: A method of manufacturing a, in order to accommodate the words range and to clarify the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, a metallic foil is embedded within the grooves so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material formed by curing a conductive paste is used for filling the via holes.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 26, 2008
    Assignees: Sony Corporation, Mitsubishi Plastics, Inc.
    Inventors: Minoru Ogawa, Masahiro Izumi, Shigeyasu Itoh, Shingetsu Yamada, Shuuji Suzuki, Hiroo Kurosaki
  • Patent number: 7294921
    Abstract: The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: November 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7293995
    Abstract: An electrical contact formed from a compliant folded sheet that includes a top surface, a bottom surface, a first contact edge and a second contact edge. A plurality of corrugations are formed in the top surface and the bottom surface that terminate at the first contact edge and the second contact edge. A connector system having a housing that has a plurality of through openings. A plurality of electrical contacts, each being formed from a compliant folded sheet that includes a top surface, a bottom surface, a first contact edge and a second contact edge. A plurality of corrugations are formed in the top surface and the bottom surface that terminate at the first contact edge and the second contact edge.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: November 13, 2007
    Assignee: Che-Yu Li & Company, LLC
    Inventor: Che-Yu Li
  • Patent number: 7294790
    Abstract: Apparatus is provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Mark T. Van Horn, Richard N. Hedden, David R. Cuthbert, Aaron M. Schoenfeld
  • Patent number: 7292452
    Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: November 6, 2007
    Assignee: Intel Corporation
    Inventors: Kok-Siang Ng, King Keong Wong, Michael E. Ryan
  • Publication number: 20070221405
    Abstract: A circuit board includes a plurality of signal lines and a plurality of shielding walls. The shield walls are disposed between the signal lines. Each shield wall includes an upper surface, a lower surface, a rectangular groove, a first metal layer and a second metal layer. The lower surface is opposite to the upper surface. The rectangular groove extends from the upper surface to the lower surface. The first metal layer is disposed on the upper surface. The second metal layer is disposed in the rectangular groove and electrically connected to the first metal layer.
    Type: Application
    Filed: January 5, 2007
    Publication date: September 27, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hung-Hsiang Cheng
  • Patent number: 7273806
    Abstract: Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: September 25, 2007
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Groves, Peter A. Gruber, Kevin S. Petrarca, Richard P. Volant, George F. Walker
  • Patent number: 7271349
    Abstract: A protective coating of insulating material is formed around a clearance hole in a conductive layer of a printed circuit board, so that the conductive material in a via within the clearance hole will not contact the conductive layer and create a short circuit. In one embodiment, the protective coating is sufficiently hard to deflect a drill bit being used to drill the via hole, thus protecting against misregistered drilled holes.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventors: Rebecca A. Jessep, Terrance J. Dishongh, Carolyn R. McCormick, Thomas O. Morgan
  • Patent number: 7262368
    Abstract: Provided are connection structures for a microelectronic device and methods for forming the structure. A substrate is included having opposing surfaces and a plurality of holes extending through the surfaces. Also included is a plurality of electrically conductive posts. Each post extends from a base to a tip located within a corresponding hole of the substrate. An additional substrate may be provided such that the base of each post is located on a surface thereof. Additional electrically conductive posts may be provided having tips in corresponding holes of the additional substrate. Optionally, a dielectric material may be placed between the substrate and the posts.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: August 28, 2007
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Masud Beroz, David B. Tuckerman, Giles Humpston, Richard Dewitt Crisp
  • Patent number: 7242592
    Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: July 10, 2007
    Assignee: Amphenol Corporation
    Inventors: Jason J. Payne, Mark W. Gailus, Leon M. Khilchenko, Huilin Ren
  • Patent number: 7230835
    Abstract: A circuit board has, in a first signal layer, a signal conductor having a relatively small width and a contact pad having a relatively large width. The relatively large width of the contact pad combined with the relatively narrow signal conductor creates an impedance mismatch between the contact pad and the signal conductor. The circuit board has, in a second signal layer, a ground plane separated from the first signal layer by a nonconductive layer. The circuit board defines an opening in the second signal layer underneath the contact pad. The presence of the ground plane underneath the contact pad typically affects the impedance of the contact pad. The opening in the second signal layer removes a portion the ground plane relative to the contact pad and, therefore, reduces the impedance mismatch between the contact pad and the signal conductor.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: June 12, 2007
    Assignee: Cisco Technology, Inc.
    Inventor: Bilal Ahmad
  • Patent number: 7204018
    Abstract: A technique for reducing via capacitance is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for reducing via capacitance. The method may comprise forming, in a circuit board, a via hole that bridges a first trace and a second trace. The method may also comprise forming a channel in a sidewall of the via hole. The method may further comprise filling the via hole and the channel with a conductive material. The method may additionally comprise removing the conductive material from the via hole without depleting the channel, thereby forming an interconnect that couples the first trace to the second trace.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: April 17, 2007
    Assignee: Nortel Networks Limited
    Inventors: Herman Kwong, Larry Marcanti, Aneta Wyrzykowska, Kah Ming Soh
  • Patent number: 7199309
    Abstract: A method to replace an electrical interface on a printed circuit board having a plurality of contact pads on a top surface, the contact pads being connected to conducting material extending through said circuit board. For the contact pad being replaced, drilling a hole through said printed circuit board at that location, and removing any remaining conductor material attached to the contact pad on the top board surface. Providing a replacement conductor/contact pad structure having a generally T-configuration with a stem and a head that completely surrounds the stem, wherein said head has a diameter greater than the diameter of the drilled hole. Inserting the replacement conductor/contact pad into the hole with said stem extending beyond the second surface of the board with the bottom surface of the head being in contact with the first surface of said board. A replacement conductor/contact pad on repaired board is also described.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: April 3, 2007
    Assignee: International Business Machines Corporation
    Inventors: Bruce John Chamberlin, Mark Kenneth Hoffmeyer, Wai Mon Ma, Arch Nuttall, James R. Stack
  • Patent number: 7190592
    Abstract: An integrated library core for embedded passive components and a method for forming an electronic device on the library core are provided. An insulating core layer is formed with a plurality of openings penetrating therethrough and with electrically conductive layers on upper and lower surfaces thereof. The openings of the core layer are filled with materials for forming passive components such as resistors and capacitors. This thereby provides an integrated library core on which the electrically conductive layers of the core layer can be desirably patterned to electrically interconnect the passive components, and this library core can be electrically connected to an electronic device such as substrate or printed circuit board to enhance performances of electrical characteristics for the electronic device.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: March 13, 2007
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Chu-Chin Hu
  • Patent number: 7186927
    Abstract: A high frequency coax via structure is configured with a stripped semi-rigid cable (no shield), and an inductive compensation loop to mitigate transition discontinuity between that via structure's center conductor and the pad to which the center conductor is connected. The performance of top-to-bottom microwave transitions at high frequencies (e.g., 1 to 12 GHz) for such boards is enhanced. A non-metallized via hole embodiment that is configured with surrounding ground vias provides a greater degree of compensation for connection pads associated with greater capacitance (such as those coupled to a component).
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: March 6, 2007
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: John S Greeley
  • Patent number: 7180009
    Abstract: A high frequency coax transmission line structure is configured with a stripped semi-rigid cable (no shield). The stripped cable is inserted lengthwise into a metallized grounded slot formed in a printed wiring board. The dielectric barrel of the stripped cable contacts each of the elongated side and bottom walls of the slot. An exposed portion of center conductor at each end of the cable lays tangent on a corresponding one of connection points (at each end of the slot). The structure reduces loss for long transmission line lengths, and fixes the mounting depth and routing for a consistent transition. Inductive compensation can be provided at the connections point at each end of the slot to mitigate transition discontinuity.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 20, 2007
    Assignee: BAE Systems Information and Electronic Systems Inteegration Inc.
    Inventor: John S Greeley
  • Patent number: 7151228
    Abstract: The present invention comprises a plurality of laminating double-side circuit boards and a plurality sheets of prepreg for interlayer connection that are placed one on another. Via holes extend from the circuit on one side of each laminating double-side circuit board to the circuit on the other side thereof. Each via hole is filled with electro-conductive material to connect the circuits on both sides of the laminating double-side circuit board. The pad on a laminating double-side circuit board and the pad on another laminating double-side circuit board are laminated via a sheet of prepreg for interlayer connection so that the respective pads are opposed to each other via the through hole filled with electro-conductive material formed through the sheet of prepreg for interlayer connection. Thereby, the respective pads on the laminating double-side wiring circuit boards are electrically connected with one another.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: December 19, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihisa Takase, Tsuneshi Nakamura
  • Patent number: 7084350
    Abstract: A green ceramic insert having a green ceramic body provided with a recess extending through the ceramic body is provided, the recess being filled with a paste which may be converted into an electrical plated hole. A ceramic insert made from a sintered green ceramic insert of this type is also described. In addition, a ceramic green body or a green body composite is provided, which has at least one recess in some areas, into which one of the described green ceramic inserts is inserted. The ceramic insert may be integrally joined to the laminated composite, a conductive paste converted by sintering into a printed conductor being routed on the laminated composite in a manner electrically insulated from it, and electroconductively connecting the top of the laminated composite to its bottom via the electrical plated hole.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 1, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Claudio De La Prieta, Andreas Hachtel, Thomas Schulte, Uwe Glanz, Erhard Hirth
  • Patent number: 7081672
    Abstract: A substrate is provided, which has a pattern of voltage supply vias extending through at least a portion of the substrate. Each of a plurality of the voltage supply vias is surrounded by four of the voltage supply vias of a same polarity in four orthogonal directions and by four voltage supply vias of an opposite polarity in four diagonal directions.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: July 25, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anand Govind, Aritharan Thurairajaratnam, Farshad Ghahghahi
  • Patent number: 6998540
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: February 14, 2006
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Robert Edward Belke, Jr., Vivek A. Jairazbhoy, Thomas B. Krautheim, William F. Quitty, Jr.
  • Patent number: 6996903
    Abstract: A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Donald S. Farquhar, Robert M. Japp, John M. Lauffer, Konstantinos I. Papathomas
  • Patent number: 6984886
    Abstract: The present invention is directed to a high-performance system on a chip which uses multi-layer wiring/insulation through-hole interconnections to provide short wiring and controlled low-impedance wiring including ground planes and power supply distribution planes between chips.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: January 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 6974916
    Abstract: In a laminated ceramic electronic component, the sectional size of via-hole conductors extending through thicker ceramic layers is larger than that of via-hole conductors extending through thinner ceramic layers. This makes it possible to facilitate filling of a conductive paste for the via-hole conductors having a larger height and to inhibit a conductive paste for the via-hole conductors having a smaller height from being lost after filling.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: December 13, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Norio Sakai
  • Patent number: 6933449
    Abstract: A printed circuit board having at least one layer of conductive traces on an external surface has at least one preformed solder element placed on a conductive trace area of the printed circuit board requiring a greater than standard amount of solder. The at least one preformed solder element is reflowed to form a connection with the layer of printed solder.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventor: Dudi Amir
  • Patent number: 6893576
    Abstract: This invention is a method of manufacturing a multi-layer printed wiring board including an internal layer circuit forming step, a outer layer circuit forming step, and a solder resist forming step. In the solder resist forming step, the surface of a board subjected to the outer layer circuit forming step is coated with a photosensitive solder resist material, the solder resist material is coated with a photosensitive film; a light shielding mask is formed by irradiating a laser beam on the photosensitive film according to a formed pattern of the solder resist, the solder resist material is exposed by using the light shielding mask, the light shielding mask is removed, and the solder resist material which is not exposed is removed.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: May 17, 2005
    Assignee: Fujitsu Limited
    Inventors: Akitaka Nakayama, Akio Ikeda, Kiyoshi Hyodo, Kazuo Uchida
  • Patent number: 6894220
    Abstract: A grounding member support forms an interference or friction fit with an opening defined by a circuit board. A compliant, electrically conductive grounding member couples to the grounding member support. The grounding member electrically couples a grounding layer of the circuit board with a support mount coupled to the circuit board. During assembly, insertion of the grounding member support within the opening defined by the circuit board creates an expansive or lateral force on the opening. Furthermore, during assembly, the support mount compresses the compliant, electrically conductive grounding member against the circuit board. The interference fit between the grounding member support and the opening along with compression of the grounding member between the circuit board and the support mount limits the amount of stress received by a surface of the circuit board.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: May 17, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Frederic Michael Kozak, Lester Creekmore
  • Patent number: 6846993
    Abstract: A conductive film has a plurality of clearances (openings) and a plurality of auxiliary clearances. The plurality of clearances and the plurality of auxiliary clearances are formed to have such numerical apertures and locations that generate no bias in the distribution of conductive film in consideration of the entire conductive film. The conductive film can disperse stress caused by thermal expansion etc., to ease by having the plurality of clearances and the plurality of auxiliary clearances. Accordingly, the conductive film is less prone to being peeled off the insulating film. Further, since the distribution of conductive film is substantially uniform as a whole, the transfer characteristics that are fixed by the distribution become substantially uniform as a whole.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: January 25, 2005
    Assignee: NEC Corporation
    Inventor: Isao Matsui
  • Patent number: 6820332
    Abstract: A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: November 23, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Japp, Voya R. Markovich, Konstantinos I. Papathomas
  • Publication number: 20040216919
    Abstract: A method to replace an electrical interface on a printed circuit board having a plurality of contact pads on a top surface, the contact pads being connected to conducting material extending through said circuit board. For the contact pad being replaced, drilling a hole through said printed circuit board at that location, and removing any remaining conductor material attached to the contact pad on the top board surface. Providing a replacement conductor/contact pad structure having a generally T-configuration with a stem and a head that completely surrounds the stem, wherein said head has a diameter greater than the diameter of the drilled hole. Inserting the replacement conductor/contact pad into the hole with said stem extending beyond the second surface of the board with the bottom surface of the head being in contact with the first surface of said board. A replacement conductor/contact pad on repaired board is also described.
    Type: Application
    Filed: June 3, 2004
    Publication date: November 4, 2004
    Applicant: International Business Machines Corporation
    Inventors: Bruce John Chamberlin, Mark Kenneth Hoffmeyer, Wai Mon Ma, Arch Nuttall, James R. Stack
  • Patent number: 6784780
    Abstract: A coupling adjusting structure for a double-tuned circuit contains first and second coils that are configured such that a pair of first conductive patterns formed on a first surface of a printed circuit and a corresponding pair of second conductive patterns formed on a second surface of the printed circuit board are connected via corresponding connecting conductors. One end of the first coil and the corresponding end of the second coil are disposed close to each other. A first ground conductive pattern is disposed at least on the first surface of the printed circuit. A first jumper connected to the first ground conductive pattern is disposed between the first and second coils to adjust an inductive coupling of the double-tuned circuit.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: August 31, 2004
    Assignee: Alps Electric Co., Ltd.
    Inventor: Shigeru Osada
  • Patent number: 6784377
    Abstract: A method to replace an electrical interface on a printed circuit board having a plurality of contact pads on a top surface, the contact pads being connected to conducting material extending through said circuit board. For the contact pad being replaced, drilling a hole through said printed circuit board at that location, and removing any remaining conductor material attached to the contact pad on the top board surface. Providing a replacement conductor/contact pad structure having a generally T-configuration with a stem and a head that completely surrounds the stem, wherein said head has a diameter greater than the diameter of the drilled hole. Inserting the replacement conductor/contact pad into the hole with said stem extending beyond the second surface of the board with the bottom surface of the head being in contact with the first surface of said board. A replacement conductor/contact pad on repaired board is also described.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bruce John Chamberlin, Mark Kenneth Hoffmeyer, Wai Mon Ma, Arch Nuttall, James R. Stack
  • Patent number: 6781066
    Abstract: Various aspects of the present invention provide microelectronic component assemblies and methods for packaging such assemblies. In one example, a microelectronic component assembly includes a substrate and a microelectronic component. This substrate has a recess in its back face and a communication opening extending through a base of the recess. This microelectronic component has an active face positioned within the substrate recess, a back face positioned outside the substrate recess, and a plurality of component contacts carried by the component active face and electrically coupled to the substrate contacts through the communication opening. This exemplary microelectronic component assembly may also include a mold compound which encapsulates the microelectronic component and a portion of the substrate active face. The mold compound may also substantially fill a gap between the periphery of the microelectronic component and a sidewall of the recess.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: August 24, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Puah Kia Heng
  • Patent number: 6771348
    Abstract: Disclosed are a displaying substrate and a liquid crystal display device having the same. A pad portion formed on the displaying substrate has a plurality of via holes for exposing a pad metal layer. A width of the via hole is smaller than a diameter of a conductive particle. Where the width of the via hole is larger than the diameter of the conductive particle, a depth of the via hole is smaller than the diameter of the conductive particle. Thus, a driving failure which may occur in the pad portion is prevented while maintaining a deformation ratio of the conductive particle at about 20˜60%, thereby enhancing a connecting force between the pad portion and a circuit substrate.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: August 3, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Weon-Sik Oh, Hyeong-Suk Yoo, Ju-Young Yoon, Won-Gu Cho