Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract: Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates.

Abstract: A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer.

Abstract: A junction field effect transistor (JFET) can include a top gate structure and an active semiconductor region. The active semiconductor region can include a side surface and a top surface formed below the top gate structure. The active semiconductor region can also include a channel region formed below the top gate structure, a bottom gate region formed below the channel region, and a gate tie region formed on the side surface that makes an electrical connection between the top gate structure and the bottom gate region.

Abstract: An n type impurity region is continuously formed on the bottom portion of a channel region below a source region, a gate region and a drain region. The n type impurity region has an impurity concentration higher than the channel region and a back gate region, and is less influenced by the diffusion of p type impurities from the gate region and the back gate region. Moreover, by continuously forming the impurity region from a portion below the source region to a portion below the drain region, the resistance value of a current path in the impurity region is substantially uniformed. Therefore, the IDSS is stabilized, the forward transfer admittance gm and the voltage gain Gv are improved, and the noise voltage Vno is decreased. Furthermore, the IDSS variation within a single wafer is suppressed.

Abstract: A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided intermediate the gate and the drain. Field gradients around the drain are thereby reduced.

Abstract: A junction field effect transistor semiconductor device and method can include a top gate interposed between a source region and a drain region, and which can extend across an entire surface of the channel region from the source region to the drain region. Top gate doping can be configured such that the top gate can remain depleted throughout operation of the device. An embodiment of a device so configured can be used in precision, high-voltage applications.

Abstract: A semiconductor device includes a principal IGBT controllable in accordance with a gate voltage applied to a gate electrode thereof, a current detecting IGBT connected to the principal IGBT in parallel and a current detecting part including a detecting resistor capable of detecting a current passing through the current detecting IGBT. The base region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other, and the emitter region of the current detecting IGBT and the emitter region of the principal IGBT are electrically connected to each other through the detecting resistor.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode.

Abstract: Monolithic electronic device including a common nitride epitaxial layer are provided. A first type of nitride device is provided on the common nitride epitaxial layer including a first at least one implanted n-type region on the common nitride epitaxial layer. The first at least one implanted n-type region has a first doping concentration greater than a doping concentration of the common nitride epitaxial layer. A second type of nitride device, different from the first, including a second at least one implanted n-type region is provided on the common nitride epitaxial layer. The second at least one implanted n-type region is different from the first at least one implanted n-type region and has a second doping concentration that is greater than the doping concentration of the common nitride epitaxial layer. First and second pluralities of contacts respectively define first and second electronic devices on the common nitride epitaxial layer.

Abstract: A monolithic electronic device includes a first nitride epitaxial structure including a plurality of nitride epitaxial layers. The plurality of nitride epitaxial layers include at least one common nitride epitaxial layer. A second nitride epitaxial structure is on the common nitride epitaxial layer of the first nitride epitaxial structure. A first plurality of electrical contacts is on the first epitaxial nitride structure and defines a first electronic device in the first nitride epitaxial structure. A second plurality of electrical contacts is on the first epitaxial nitride structure and defines a second electronic device in the second nitride epitaxial structure. A monolithic electronic device includes a bulk semi-insulating silicon carbide substrate having implanted source and drain regions and an implanted channel region between the source and drain regions, and a nitride epitaxial structure on the surface of the silicon carbide substrate. Corresponding methods are also disclosed.

Abstract: An insulated gate semiconductor device includes a one conductivity type semiconductor layer, a first operation part in a surface of the semiconductor layer and a second operation part in the surface of the semiconductor layer that is smaller in area than the first operation part. A first channel region and a first transistor of an opposite conductivity type are provided in the first operation part and a second channel region and a second transistor of the opposite conductivity type are provided in the second operation part. The first operation part is disposed around the second operation part. Accordingly, design rules for four corner portions can be made uniform and depletion layer spreading in corner portions at a peripheral edge of a channel region of an operation part in application of a reverse voltage is also made approximately uniform. Thus, stable VDSS breakdown voltage characteristics can be obtained.

Abstract: A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

Abstract: In a MOSFET using SiC a p-type channel is formed by epitaxial growth, so that the depletion layer produced in the p-type region right under the channel is reduced, even when the device is formed in a self-aligned manner. Thus, a high breakdown voltage is obtained. Also, since the device is formed in a self-aligned manner, the device size can be reduced so that an increased number of devices can be fabricated in a certain area and the on-state resistance can be reduced.

Abstract: Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

Abstract: An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof.

Abstract: A field-effect transistor with improved moisture resistance without an increase in gate capacitance, and a method of manufacturing the field-effect transistor are provided. The field-effect transistor includes: a T-shaped gate electrode on a semiconductor layer; and a first highly moisture-resistant protective film including one of an insulating film and an organic film having high etching resistance, the first highly moisture-resistant protective film being located above the T-shaped gate electrodes over all of a region in which the T-shaped gate electrode is located. A cavity is located between the semiconductor layer and the first highly moisture-resistant protective film below a canopy of the T-shaped gate electrode. An end surface of the cavity is closed by a second highly moisture-resistant film.

Abstract: In a high voltage junction field effect transistor, a first well (11) of a first conductivity type is formed in a substrate (10) of a second conductivity type. A source (14) and a drain (15) which are each of the first conductivity type are formed in the first well. A gate (16) of the second conductivity type is arranged in a second well (12) of the second conductivity type, wherein the second well is of the retrograde type. The source, gate and drain are spaced apart from one another by field oxide regions (13a to 13d). Field plates (17a, 17b) extend over the field oxide (13a, 13b) from the gate (16) in the direction of source and drain.

Abstract: A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.

Abstract: A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

Abstract: A surface component film (2) is etched using a resist (3) as a mask, and the surface component film (2) is patterned according to the shape of an aperture (3a). This results in a step portion (4) having the same shape as the aperture (3a), with the sidewall (4a) of the step portion (4) exposed through the aperture (3a). The aperture (3a) is spin-coated with a shrink agent, reacted at a first temperature, and developed to shrink the aperture (3a). To control the shrinkage with high accuracy, in the first round of reaction, the aperture is shrunk by, for example, about half of the desired shrinkage. The aperture (3a) is further spin-coated with a shrink agent, reacted at a second temperature, and developed to shrink the aperture (3a). In this embodiment, the second-round shrink process will result in the desired aperture length. The second temperature is adjusted based on the shrinkage in the first round.

Abstract: A photo-FET based on a compound semiconductor including a channel layer formed on a substrate constituting a current path between source and drain electrodes, serving as part of a photodiode and a photosensitive region. A back-gate layer that serving as a substrate-side depletion layer formation layer is disposed between the substrate and the channel layer, and applies to the channel layer a back-gate bias by photogenerated carriers upon illumination. A barrier layer is disposed on the front side of the channel layer that causes one of the photogenerated carriers to run through the channel layer and other of the photogenerated carriers to sojourn or be blocked off. A front-side depletion layer formation layer is disposed on the front side of the channel layer brings the front-side depletion layer into contact with the substrate-side depletion layer without illumination to close the current path in the channel layer, bringing the photo-FET to an off-state.

Abstract: A field effect transistor includes a channel region fabricated on a compound semiconductor substrate, a gate electrode fabricated on the channel region, a source electrode and a drain electrode alternately arranged on the channel region with a gate electrode interposed between the source electrode and the drain electrode, a bonding pad to be connected with an external circuit; and an air-bridge connected with the bonding pad. The air-bridge includes an electrode contact terminal to be connected with the source electrode or the drain electrode and an aerial circuit line for connecting the electrode contact terminal with a contact terminal of the bonding pad, the widthwise cross sectional area of the electrode contact terminal being equal to or less than that of the aerial circuit line.

Abstract: Silicon-on-insulator JFET (SOI JFET) having a fully depleted body and fabrication methods therefor. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time). The devices and techniques include a fully-depleted body SOI-JFET, with improved switching characteristic over partially-depleted SOI JFET or bulk silicon devices. In one example, by tuning the thickness of the silicon containing layer of the SOI substrate, the body region of the JFET can be fully depleted during the OFF-state thus offering the performance benefits of suppressed leakage current. Additionally, improved AC performance (e.g., faster switching time) is achieved.

Abstract: Silicon-on-insulator JFET having a body bias and a fully depleted body and fabrication methods therefore are disclosed. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time), and have poor leakage performance at high temperatures. The techniques herein introduced include a fully-depleted body SOI-JFET, with a non-zero bias applied to its body. In one example, the body region of the JFET can be fully depleted by tuning the thickness of the silicon containing layer of the SOI substrate. Additionally, the deep depletion can be induced by applying a non-zero bias to the body region, at a range of operating temperatures. Full body depletion and/or the application of body bias offers the benefits of suppressed leakage current at higher operating temperatures (e.g., between or above 25-115 C) and improved AC performance (e.g., faster switching time).

Abstract: A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well with a hole; then, a drive-in process of the type II semiconductor is performed to allow the implant dosage of the type II well getting less gradually from the surroundings of the hole toward the center of the hole; and finally, the gate, the source and the drain of the junction field effect transistor being formed successively on the type II well. The implant dosage at the hole, which is acted as a channel, is determined in accordance with the preset size of the hole during the type II well being formed such that it is capable being compatible with the output voltages of different junction field effect transistors to achieve the purpose of the adjustment of the pinch-off voltage of the junction field effect transistor without the need of the mask and the manufacturing process.

Abstract: In accordance with the present techniques, there is provided a JFET device structures and methods for fabricating the same. Specifically, there is provided a transistor including a semiconductor substrate having a source and a drain. The transistor also includes a doped channel formed in the semiconductor substrate between the source and the drain, the channel configured to pass current between the source and the drain. Additionally, the transistor has a gate comprising a semiconductor material formed over the channel and dielectric spacers on each side of the gate. The source and the drain are spatially separated from the gate so that the gate is not over the drain and source.

Abstract: A description is given of a semiconductor component comprising a drift zone of a first conduction type and at least one Schottky metal zone arranged in the drift zone, and of a method for producing a semiconductor component.

Abstract: An input surge suppression device and method that uses a simple JFET structure. The JFET has its gate clamped to a predetermined value, its the drain receives the input voltage from an input power source, its source is connected to the input of a down-stream device, and a resistor connected between the drain and the gate or between the source and the gate. Thus, when the drain voltage approximates the clamped gate voltage, the source voltage nearly equals the drain voltage. When the drain voltage rises above the clamped gate voltage, the source voltage is lower than the drain voltage. The downstream device may be a DC-DC converter and the gate is biased by the enable (EN) pin of a DC-DC converter.

Abstract: An apparatus for controlling a signal includes an optical waveguide having a variable refractive index; an active device formed within the waveguide, the device having three electrodes, a drain, a source and a gate; and wherein the device is located within the waveguide so that current flowing from the drain to the source changes the refractive index.

Abstract: A rectifier device (10) comprising a multi-layer epitaxial film (12) and a rectifier and a transistor manufactured in the film (12), wherein the transistor is oriented vertically relative to the plane of the rectifier. The rectifier and transistor are separated by a transition zone of inverted bias. The rectifier is a Schottky barrier rectifier, and the transistor is a JFET. More specifically, the device (1) comprises the film (12), a trench (16), a first region (18) associated with an upper portion of the trench (16), and second region (20) associated with a lower portion. The interface between the p+ material of the second region (20) and the n material of the film (12) creates a p+/n junction. The device (10) has use in high frequency, low-loss power circuit applications in which high switching speed and low forward voltage drop are desirable.

Abstract: To solve the foregoing problems, provided is a ZnO-based semiconductor element having an entirely novel function distinct from hitherto, using a ZnO-based semiconductor and organic matter for an active role. An organic electrode 2 is formed on a ZnO-based semiconductor 1, and an Au film 3 is formed on the organic electrode 2. An electrode formed of a multilayer metal film including a Ti film 4 and an Au film 5 is formed on the back surface of the ZnO-based semiconductor 1 so as to be opposed to the organic electrode 2. A bonding interface between the organic electrode 2 and the ZnO-based semiconductor 1 is in a pn junction-like state. Thus, rectification occurs therebetween.

Abstract: A memory cell (FIG. 6A) compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The memory cell includes a first junction field effect transistor (600) having a first conductivity type. A second junction field effect transistor (602) having a second conductivity type is coupled to the first junction field effect transistor. An access transistor (610) is coupled to the first and second junction field effect transistors.

Abstract: There is provided a technique for reducing the occurrence of higher harmonics which occur from a field effect transistor, particularly a field effect transistor configuring a switching element of an antenna switch. In a transistor having a meander structure, the gate width of a partial transistor closest to a gate input side is increased. More specifically, a comb-like electrode is made longer than the other comb-like electrodes. In other words, a finger length is made greater than any other finger length. In particular, the comb-like electrode has the greatest length in all the comb-like electrodes.

Abstract: On a p? epitaxial layer, an n-type epitaxial layer and a gate region are formed in this order. A gate electrode is electrically connected to the gate region, and a source electrode and a drain electrode are spaced apart from each other with the gate electrode sandwiched therebetween. A control electrode is used for applying to the p? epitaxial layer a voltage that causes a reverse biased state of the p? epitaxial layer and the n-type epitaxial layer in an OFF operation.

Abstract: The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region and a second source/drain region separated from one another by the channel region. A control gate structure, comprising a semiconductor layer doped to the first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells.

Abstract: This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.

Abstract: A semiconductor device includes an active region defined in a semiconductor substrate, and gate electrodes crossing over the active region. Source/drain regions are defined in the active region on two sides of the gate electrode. At least one of the source/drain regions is a field effect source/drain region generated by a fringe field of the gate. The other source/drain region is a PN-junction source/drain region having different impurity fields and different conductivity than the substrate. At least one of the source/drain regions is a field effect source/drain region. Accordingly, a short channel effect is reduced or eliminated in the device.

Abstract: An junction field effect transistor (JFET) is fashioned with a patterned layer of silicide block (SBLK) material utilized in forming gate, source and drain regions. Utilizing the silicide block in this manner helps to reduce low-frequency (flicker) noise associated with the JFET by suppressing the impact of surface states, among other things.

Abstract: Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise.

Abstract: Provided is a method of sensing biomolecules using a bioFET, the method including: forming a layer including Au on a gate of the bioFET; forming a probe immobilized on a substrate separated from the gate by a predetermined distance, and a biomolecule having a thiol group (—SH) which is incompletely bonded to the probe; reacting the probe with a sample including a target molecule; and measuring a current flowing in a channel region between a source and a drain of the bioFET.

Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.

Abstract: A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region.

Abstract: A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

Abstract: A current sense device for a power transistor is described. The power transistor is formed in a cellular structure including a cellular array of transistor cells. The current sense device includes multiple transistor cells in the cellular array of transistor cells of the power transistor being used as sense transistor cells. The sense transistor cells are evenly distributed throughout the cellular array where the source terminal of each sense transistor cell is electrically connected to a first node through a metal line in the first metal layer and through a metal line in the second metal layer where the metal lines are electrically isolated from the metal lines connecting the transistor cells of the power transistor. The sense transistor cells measure a small portion of the current flowing through the power transistor based on the size ratio of the current sense device and the power transistor.

Abstract: An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device.

Abstract: A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

Abstract: A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer.