In Complementary Field Effect Transistor Integrated Circuit Patents (Class 257/357)
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Patent number: 7589386Abstract: A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and between the source and the drain. The device also includes a first conductivity type well region, a second conductivity type channel layer formed on the surface of the well region, a first wire that connects an end of the second conductivity type channel layer to the first conductivity type drain, a second wire that connects the other end of the second conductivity type channel layer to a power source, and a third wire 208 that connects the first conductivity type well region to the gate of the first field effect transistor. This semiconductor device and manufacturing method thereof enables low power consumption and simple control of threshold voltage values as well as decreases the number of conventional manufacturing processes.Type: GrantFiled: November 9, 2006Date of Patent: September 15, 2009Assignee: Sony CorporationInventor: Tsutomu Imoto
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Patent number: 7589566Abstract: A CMOS LSI includes an inverter including first and second MOS transistors, a relatively long metal interconnection connected to an input node of the inverter, first and second diodes releasing charges born by the metal interconnection during a plasma process to first and second wells, and first and second MOS transistors maintaining a voltage between the first and second wells at a level not higher than a prescribed voltage. Therefore, even when an antenna ratio is high, a gate oxide film in the first and second MOS transistors is not damaged during the plasma process.Type: GrantFiled: December 1, 2005Date of Patent: September 15, 2009Assignee: Renesas Technology Corp.Inventors: Shigeki Ohbayashi, Hiroaki Suzuki, Koichiro Ishibashi, Hiroshi Makino
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Publication number: 20090218626Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.Type: ApplicationFiled: May 18, 2009Publication date: September 3, 2009Inventors: Ryuji SHIBATA, Shigeru Shimada
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Patent number: 7582938Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.Type: GrantFiled: October 25, 2005Date of Patent: September 1, 2009Assignee: LSI CorporationInventor: Jau-Wen Chen
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Patent number: 7579669Abstract: A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.Type: GrantFiled: October 16, 2006Date of Patent: August 25, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Norio Yasuhara, Tomoko Matsudai, Kenichi Matsushita, Akio Nakagawa
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Patent number: 7576961Abstract: Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.Type: GrantFiled: January 23, 2008Date of Patent: August 18, 2009Assignee: Electronics and Telecommunications Research InstituteInventors: Kwi Dong Kim, Chong Ki Kwon, Jong Dae Kim
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Patent number: 7554158Abstract: An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.Type: GrantFiled: January 25, 2006Date of Patent: June 30, 2009Assignee: NEC Electronics CorporationInventors: Ryota Yamamoto, Kuniko Kikuta
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Publication number: 20090152632Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: ApplicationFiled: December 14, 2007Publication date: June 18, 2009Inventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
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Patent number: 7545001Abstract: A semiconductor device including an isolation region located in a substrate, an NMOS device located partially over a surface of the substrate, and a PMOS device isolated from the NMOS device by the isolation region and located partially over the surface. A first one of the NMOS and PMOS devices includes one of: (1) first source/drain regions recessed within the surface; and (2) first source/drain regions extending from the surface. A second one of the NMOS and PMOS devices includes one of: (1) second source/drain regions recessed within the surface wherein the first source/drain regions extend from the surface; (2) second source/drain regions extending from the surface wherein the first source/drain regions are recessed within the surface; and (3) second source/drain regions substantially coplanar with the surface.Type: GrantFiled: November 25, 2003Date of Patent: June 9, 2009Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Shui-Ming Cheng, Ka-Hing Fung, Kuan Lun Cheng, Yi-Ming Sheu
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Publication number: 20090140340Abstract: An electrostatic discharge (ESD) protective device structure is disclosed. The ESD protection device includes: at least a first conductive type metal-oxide semiconductor (MOS), in which the drain and source of the first conductive type MOS are electrically connected to a first power terminal and a second power terminal separately; at least a second conductive type diffusion region; and at least a dummy gate disposed between the first conductive type MOS and the second conductive type diffusion region, wherein the gate length of the dummy gate is less than the gate length of the first conductive type MOS gate, such that the junction between the second conductive type diffusion region and the drain of the first conductive type MOS have a low breakdown voltage.Type: ApplicationFiled: February 4, 2009Publication date: June 4, 2009Inventor: Ching-Hung Kao
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Patent number: 7541647Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.Type: GrantFiled: June 28, 2005Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Ryuji Shibata, Shigeru Shimada
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Patent number: 7541235Abstract: A method for providing a programmable electrostatic discharge (ESD) protection device is provided. The method includes providing a source diffusion in a substrate, providing a deeper body diffusion in the substrate, providing a gate at a space between the source diffusion and the body diffusion, and providing a variable structure for shorting the source diffusion and the body diffusion to each other when ESD voltage is encountered on a circuit connected thereto, wherein the variable structure comprises a plurality of contacts over the source diffusion for the source diffusion to be grounded to the body diffusion.Type: GrantFiled: June 5, 2006Date of Patent: June 2, 2009Assignee: Micrel, Inc.Inventor: John D. Husher
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Patent number: 7521713Abstract: A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.Type: GrantFiled: July 14, 2005Date of Patent: April 21, 2009Assignee: Oki Semiconductor Co., Ltd.Inventor: Hirokazu Hayashi
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Patent number: 7511338Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.Type: GrantFiled: September 6, 2006Date of Patent: March 31, 2009Assignees: Renesas Technology Corp., Tokyo Electron LimitedInventors: Toshihide Nabatame, Masaru Kadoshima, Hiroyuki Takaba
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Patent number: 7511345Abstract: The present invention provides a MOS transistor device for providing ESD protection including at least one interleaved finger having a source, drain and gate region formed over a channel region disposed between the source and the drain regions. The transistor device further includes at least one isolation gate formed in at least one of the interleaved fingers. The device can further include a bulk connection coupled to at least one of the source, drain and gate regions via through at least one of diode, MOS, resistor, capacitor inductor, short, etc. The bulk connection is preferably isolated through the isolation gate.Type: GrantFiled: June 12, 2006Date of Patent: March 31, 2009Assignees: Sarnoff Corporation, Sarnoff EuropeInventors: Benjamin Van Camp, Gerd Vermont
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Publication number: 20090079003Abstract: A protection circuit network includes one or more protection devices, used to protect one or more devices in an integrated circuit (IC) design. The protection devices are globally coupled together, for connection to an internal or external power supply. During manufacture of the IC, the protection circuit network protects the at-risk devices. During operation of the IC, the protection circuit network is powered down, such that excessive current leakage is avoided.Type: ApplicationFiled: October 31, 2008Publication date: March 26, 2009Inventor: Wallace W. Lin
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Patent number: 7504693Abstract: Structures and methods of manufacturing are disclosed of dislocation free stressed channels in bulk silicon and SOI (silicon on insulator) CMOS (complementary metal oxide semiconductor) devices by gate stress engineering with SiGe and/or Si:C. A CMOS device comprises a substrate of either bulk Si or SOI, a gate dielectric layer over the substrate, and a stacked gate structure of SiGe and/or Si:C having stresses produced at the interfaces of SSi(strained Si)/SiGe or SSi/Si:C in the stacked gate structure. The stacked gate structure has a first stressed film layer of large grain size Si or SiGe over the gate dielectric layer, a second stressed film layer of strained SiGe or strained Si:C over the first stressed film layer, and a semiconductor or conductor such as p(poly)-Si over the second stressed film layer.Type: GrantFiled: April 23, 2004Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Huilong Zhu, Bruce B. Doris, Huajie Chen
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Publication number: 20090067105Abstract: A system includes a driving device operating at first supply voltage Vdd1 and having a CMOS output. A driven devise operates at a second supply voltage Vdd2 lower than the first supply voltage Vdd1, and has a CMOS input with an NMOS pull-down transistor. A protection circuit includes a first resistor coupled to the CMOS output of the driving device and a gate of the NMOS pull-down transistor. A parasitic NPN bipolar junction transistor has a drain connected to the gate of the NMOS pull-down transistor sad a source coupled to a lower-voltage supply rail VSS. A second resistor connects a gate of the parasitic NPN bipolar junction transistor to Vss. The second resistor has a resistance sized for controlling a trigger voltage of the parasitic NPN bipolar junction transistor for protecting a gate oxide layer of the NMOS pull-down transistor from an electrostatic discharge.Type: ApplicationFiled: September 10, 2007Publication date: March 12, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Huei Lin, Chong-Gim Gan, Yi-Hsun Wu, Yu-Chang Lin
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Publication number: 20090057767Abstract: A semiconductor device includes a protected device formed on a semiconductor substrate, a first protection transistor formed in a second well of a second conductivity type, and a second protection transistor formed in a first well of a first conductivity type. A fourth source/drain diffusion layer of the second protection transistor is in contact with a second diffusion layer, and a third source/drain diffusion layer is in contact with a second source/drain diffusion layer of the first protection transistor in the second well. A first source/drain diffusion layer of the first protection transistor is in contact with a first diffusion layer, which is in contact with a protected device electrode.Type: ApplicationFiled: August 25, 2008Publication date: March 5, 2009Inventors: Nobuyoshi Takahashi, Keita Takahashi
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Patent number: 7482671Abstract: A MOS semiconductor device isolated by a trench device isolation region includes a p-channel MOS field effect transistor having a source/drain region with a length in the channel direction that is not more than 1 micrometer, and a gate length that is not more than 0.2 micrometers. The n-channel MOS field effect transistor is designed so that a face of the sourced/drain region in parallel to the gate width direction is adjacent to the device isolation film with the inserted silicon nitride film, and a face of the source/drain region parallel to the gate length direction is adjacent to the device isolation film including the silicon oxide film only.Type: GrantFiled: March 23, 2006Date of Patent: January 27, 2009Assignee: NEC CorporationInventors: Akio Toda, Haruihiko Ono
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Publication number: 20090020818Abstract: A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.Type: ApplicationFiled: July 16, 2007Publication date: January 22, 2009Inventor: Steven Howard Voldman
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DECOUPLING CAPACITOR CIRCUIT AND LAYOUT FOR LEAKAGE CURRENT REDUCTION AND ESD PROTECTION IMPROVEMENT
Publication number: 20090014801Abstract: In order to reduce the leakage current and increase the ESD protection performance, several MOS capacitors are serially connected. The E field between the gate and the source/drain of the MOS transistor is lowered and so is the gate leakage current. Besides, because the ESD voltage is distributed on the gates of the MOS capacitors, the MOS capacitors have good ESD protection performance.Type: ApplicationFiled: July 10, 2007Publication date: January 15, 2009Applicant: FARADAY TECHNOLOGY CORP.Inventors: Wang-Jin Chen, Chia-Nan Hong -
Patent number: 7476941Abstract: A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.Type: GrantFiled: March 1, 2007Date of Patent: January 13, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Masashi Shima, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20080303093Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.Type: ApplicationFiled: May 28, 2008Publication date: December 11, 2008Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hideaki Sai
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Patent number: 7456477Abstract: The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.Type: GrantFiled: July 9, 2002Date of Patent: November 25, 2008Assignee: Texas Instruments IncorporatedInventors: E. Ajith Amerasekera, Vikas Gupta, Stanton P. Ashburn
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Publication number: 20080277728Abstract: A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate and enclosing the N-well and the P-well; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; and a first ground and a second ground respectively disposed to positions corresponding to outside and inside of the N+ section. Also, the second doping regions are isolated from the first doping regions. The first and second doping regions located within the N+ section are isolated from the substrate by the N+ section. Furthermore, the second ground is electrically connected to at least one of the second doping regions.Type: ApplicationFiled: May 11, 2007Publication date: November 13, 2008Applicant: SYSTEM GENERAL CORP.Inventor: Chih-Feng Huang
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Patent number: 7449751Abstract: A high voltage operating electrostatic discharge protection device is provided. The high voltage operating electrostatic discharge protection device includes: a first gate structure and a second gate structure disposed on a substrate of a first conductive type with a predetermined distance; a well of the first conductive type formed in a first region of the substrate such that the well contacts one bottom portion of the first gate structure; a source region of a second conductive type formed within in the well; a counter pocket source region of the first conductive type formed within the well encompassing the source region; and a drift region of the second conductive type contacting a bottom surface of the second gate structure and formed in a second region of the substrate such that the drift region contacts the other bottom portion of the first gate structure.Type: GrantFiled: September 7, 2005Date of Patent: November 11, 2008Assignee: Magnachip Semiconductor, Ltd.Inventor: Kil-Ho Kim
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Patent number: 7439590Abstract: A semiconductor device features connecting gate patterns of all transistors to a N+ or +P junction by the first connected wiring layer to prevent degradation of characteristics of the semiconductor device which results from plasma damages during a process. In order to connect a junction to a gate layer weak to plasma damages, the gate layer is connected to the N+ or P+ junction when a first wiring layer after a transistor is formed. As a result, when the gate layer is charged up by plasma damages, the gate layer is discharged by the junction or provided to receive (?) ions or electrons so that a gate oxide is not affected by plasma damages.Type: GrantFiled: July 3, 2006Date of Patent: October 21, 2008Assignee: Hynix Semiconductor Inc.Inventor: Dong Hoon Kim
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Patent number: 7429774Abstract: An NMOS device having protection against electrostatic discharge. The NMOS device includes a P-substrate, a P-epitaxial layer overlying the P-substrate, a P-well in the P-epitaxial layer, an N-well in the P-epitaxial layer and encompassing the P-well, an N-Buried Layer (NBL) underneath the P-well and bordering the N-well. The P-well is fully isolated by the N-well and the NBL. The NMOS device further includes a first isolation structure consisting of a gate-insulating layer connected with a field oxide layer, which is formed on the P-epitaxial layer. A gate overlies the first isolation structure. A second isolation structure laterally spaced apart from the first isolation structure is approximately situated on the N-well. An N+ source doping region, which functions as a source of the NMOS device, is disposed in the P-well. An N+ drain doping region, which functions as a drain of the NMOS device, is disposed in the N-well.Type: GrantFiled: February 22, 2005Date of Patent: September 30, 2008Assignee: United Microelectronics Corp.Inventors: Chih-Nan Cheng, Yii-Chian Lu, Fang-Mei Chao
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Publication number: 20080224220Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).Type: ApplicationFiled: October 5, 2006Publication date: September 18, 2008Applicant: NXP B.V.Inventors: Fabrice Blanc, Frederic Francois Barbier
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Patent number: 7423324Abstract: In a double-gate MOS transistor, a substrate, an insulating layer, and a semiconductor layer are formed or laminated in that order, an opening extending to the insulating layer is formed in the semiconductor layer while leaving an island-shaped region, the island-shaped region including a semiconductor crystal layer having a predetermined length and height and a predetermined shape of horizontal section, the semiconductor crystal layer including P-type or N-type source region, channel region, and drain region, in that order, formed therein, a source electrode, gate electrodes, and a drain electrode are provided in contact with side surfaces of the respective regions, and the gate electrodes are provided in contact with the side surfaces of the channel region.Type: GrantFiled: April 5, 2005Date of Patent: September 9, 2008Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Toshihiro Sekigawa, Yongxun Liu, Meishoku Masahara, Hanpei Koike, Eiichi Suzuki
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Patent number: 7417303Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: September 15, 2006Date of Patent: August 26, 2008Assignee: Broadcom CorporationInventors: Agnes N. Woo, Kenneth R. Kindsfater, Fang Lu
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Publication number: 20080197416Abstract: A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS.Type: ApplicationFiled: September 21, 2007Publication date: August 21, 2008Inventor: Keita Takahashi
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Patent number: 7403361Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.Type: GrantFiled: July 12, 2006Date of Patent: July 22, 2008Assignees: Renesas Technology, Hitachi ULSI Systems Co., Ltd.Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
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Patent number: 7402846Abstract: An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure includes an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure.Type: GrantFiled: October 20, 2005Date of Patent: July 22, 2008Assignee: Atmel CorporationInventors: Stefan Schwantes, Michael Graf, Volker Dudek, Gayle W. Miller, Jr., Irwin Rathbun, Peter Grombach, Manfred Klaussner
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Patent number: 7396709Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the semiconductor layer includes a minute protruding portion, and the side surface inclination angle of the gate electrode is larger than the inclination angle of the protruding portion of the semiconductor layer.Type: GrantFiled: July 20, 2007Date of Patent: July 8, 2008Assignee: Sharp Kabushiki KaishaInventor: Naoki Makita
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Patent number: 7394156Abstract: A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cells is constituted by using only upper n (n<m) wiring layers. It becomes possible to shorten a development period and reduce a development cost when a gate array type semiconductor integrated circuit device becomes large in scale.Type: GrantFiled: January 25, 2005Date of Patent: July 1, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Shigeki Furuya, Yuuji Hinatsu
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Publication number: 20080135940Abstract: A semiconductor device includes an NMOS switching element having an N-type drain diffusion region coupled to an input and/or output terminal, and an N-type source diffusion region and a P-type substrate contact diffusion region coupled to a ground line; and an NMOS protection element having an N-type drain diffusion region coupled to the input and/or output terminal, and a gate, an N-type source diffusion region and a P-type substrate contact diffusion region coupled to the ground line, wherein the N-type source diffusion region and the P-type substrate contact diffusion region of the NMOS switching element are arranged adjacent to each other, and the N-type source diffusion region and the P-type substrate contact diffusion region of the NMOS protection element are arranged with a spacing therebetween. If the N and P types are interchanged, the ground line is replaced by a power supply line.Type: ApplicationFiled: September 19, 2006Publication date: June 12, 2008Inventor: Hiroyuki Hashigami
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Patent number: 7385253Abstract: Disclosed herein are a device for electrostatic protection and circuit thereof.Type: GrantFiled: February 4, 2005Date of Patent: June 10, 2008Assignee: Magnachip Semiconductor, Ltd.Inventor: Kil Ho Kim
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Publication number: 20080116518Abstract: The present invention provides a device for ESD protection and voltage stabilizing in order to let chip space be put in better utilization. During different conditions (i.e. ESD current occurrences and normal operation), identical elements of the device are used both for ESD protection and for voltage stabilization. The chip size and manufacturing costs necessary for the additional voltage stabilizing capacitors are thereby saved.Type: ApplicationFiled: November 15, 2007Publication date: May 22, 2008Applicant: Realtek Semiconductor Corp.Inventors: Tung-Cheng Kuo, Yi-Lin Chen
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Patent number: 7365386Abstract: A semiconductor device having improved reliability is provided. The semiconductor device has a pixel portion. The pixel portion has a TFT and a storage capacitor. The TFT and the storage capacitor has a semiconductor layer which includes first and second regions formed continuously. The TFT has the first region of the semiconductor layer including a channel forming region, a source region and a drain region located outside the channel forming region, a gate insulating film adjacent to the first region of the semiconductor layer, and a gate electrode formed on the gate insulating film. The storage capacitor has the second region of the semiconductor layer, an insulating film formed adjacent to the second region of the semiconductor layer, and a capacitor wiring formed on the insulating film. The second region of the semiconductor layer contains an impurity element for imparting n-type or p-type conductivity.Type: GrantFiled: August 28, 2003Date of Patent: April 29, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tatsuya Arao, Hideomi Suzawa
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Patent number: 7361534Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.Type: GrantFiled: May 11, 2005Date of Patent: April 22, 2008Assignee: Advanced Micro Devices, Inc.Inventor: Mario M. Pelella
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Patent number: 7361957Abstract: The present invention relates to a device for electrostatic discharge protection (ESD).Type: GrantFiled: June 23, 2006Date of Patent: April 22, 2008Assignee: Magnachip Semiconductor, Ltd.Inventors: Kil Ho Kim, Yong Icc Jung
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Patent number: 7355250Abstract: An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept between a second P+ doped region and a third N+ doped region. In addition, the holding current of the ESD device can be set to a specific value by modulating the first distance and the second distance. The holding current is in inverse proportion to the first distance and the second distance.Type: GrantFiled: September 8, 2005Date of Patent: April 8, 2008Assignee: System General Corp.Inventors: Chih-Feng Huang, Ta-yung Yang, Jenn-yu G. Lin, Tuo-Hsin Chien
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Patent number: 7345345Abstract: A CMOS semiconductor device having a triple well structure which can block latch-up by preventing parasitic thyristors from turning on is offered with reduced layout area. The CMOS semiconductor device includes a P-type silicon substrate, a first and a second deep N-type wells formed in a surface of the P-type silicon substrate and separated from each other, a P-type well formed in the first deep N-type well, a shallow N-type well formed in the second deep N-type well, an N-channel type MOS transistor formed on a surface of the P-type well and a P-channel type MOS transistor formed on a surface of the shallow N-type well.Type: GrantFiled: August 4, 2004Date of Patent: March 18, 2008Assignee: Sanyo Electric Co., Ltd.Inventors: Ryoichi Ando, Akira Uemoto, Toshio Kakiuchi
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Publication number: 20080042207Abstract: A transistor layout is disclosed for improving electrostatic discharge capabilities. The layout has a first gate region with a first active region and a second active region formed on two sides thereof, and a second gate region placed next to the second active region with a third active region placed on an opposing side of the second gate region from the second active region. A first and a second set of contacts formed on the first and the third active regions, and a third set of contacts formed on the second active region, wherein the third set of contacts are spaced in parallel with and offset from the other two sets of contacts such that no contact from the third set is aligned laterally with a contact from either the first or the second set of contacts.Type: ApplicationFiled: August 17, 2006Publication date: February 21, 2008Inventors: Yi-Hsun Wu, Jian-Hsing Lee, Kuo-Feng Yu, C.S. Tang, Cheng-Chun Ting
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Patent number: 7317633Abstract: A method for protecting NROM devices from charge damage during process steps, the method including providing X-decoder structure for word line connections, wherein each word line is connected to a pair of transistors, a PMOS transistor and an NMOS transistor the PMOS transistors sharing a common deep N well and the NMOS transistors connected to a P well, wherein during negative charging, the NMOS transistors shunt leakage current to ground, and during positive charging, the PMOS transistors shunt leakage current to ground, providing an N+ tap connected to the N well and connecting the N+ tap to a positive voltage clamping device, and connecting all the P wells together to a common P+ tap and connecting the P+ tap to a negative voltage clamping device, wherein during process steps, the negative and positive voltage clamping devices direct leakage current to ground.Type: GrantFiled: July 5, 2005Date of Patent: January 8, 2008Assignee: Saifun Semiconductors LtdInventors: Eli Lusky, Ilan Bloom, Assaf Shappir, Boaz Eitan
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Patent number: 7315063Abstract: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.Type: GrantFiled: February 28, 2006Date of Patent: January 1, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-eun Lee, Seong-ghil Lee, Yu-gyun Shin, Jong-wook Lee, Young-pil Kim
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Patent number: 7315066Abstract: A semiconductor structure and method for forming the same. The structure includes a hybrid orientation block having first and second silicon regions having different lattice orientations. The first silicon region is directly on the block, while the second silicon region is physically isolated from the block by a dielectric region. First and second transistors are formed on the first and second regions, respectively. Also, first and second doped discharge prevention structures are formed on the block wherein the first doped discharge prevention structure prevents discharge damage to the first transistor, whereas the second doped discharge prevention structure prevents discharge damage to the second transistor during a plasma process. During the normal operation of the first and second transistors, the first and second discharge prevention structures behave like dielectric regions.Type: GrantFiled: June 1, 2005Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: James W. Atkisson, Jeffrey P. Gambino, Alain Loiseau, Kirk D. Peterson
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Publication number: 20070284665Abstract: According to an embodiment of the present invention, an electrostatic discharge protection circuit used for a semiconductor device including a first power supply terminal, a second power supply terminal, and an input/output terminal, includes: a thyristor passing a surge current from the input/output terminal to the second power supply terminal; and a bipolar transistor passing a surge current from the first power supply terminal to the input/output terminal.Type: ApplicationFiled: June 5, 2007Publication date: December 13, 2007Applicant: NEC ELECTRONICS CORPORATIONInventor: Takayuki Nagai