Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure.

Abstract: The output circuit uses an IGBT incorporating a normal latch-up operation measure and the ESD clamp circuit uses an IGBT that can more easily latch up than the output circuit device which has the latch-up prevention layer lowered in impurity density or removed.

Abstract: A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled to the external circuit by bonding wires, a bump coupling part and a bonding pad are both provided in a single uppermost wiring layer. When the bump electrodes are used, an opening is provided in an insulating film on the bump coupling part and a surface of the bonding pad is covered with the insulating film. On the other hand, when the bonding wires are used, an opening is provided in an insulating film on the bonding pad and a surface of the bump coupling part is covered with the insulating film.

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract: CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions and source regions placed alternately with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: the first metal interconnects formed on the source regions are electrically connected to the second metal interconnect through constant size via-holes, and a ratio between the numbers of the via-holes arranged above each of the source regions is controlled to be less than four according to a distance from the ground potential supply line.

Abstract: An electrostatic discharge (ESD) protection circuit, methods of fabricating an ESD protection circuit, methods of providing ESD protection, and design structures for an ESD protection circuit. An NFET may be formed in a p-well and a PFET may be formed in an n-well. A butted p-n junction formed between the p-well and n-well results in an NPNP structure that forms an SCR integrated with the NFET and PFET. The NFET, PFET and SCR are configured to collectively protect a pad, such as a power pad, from ESD events. During normal operation, the NFET, PFET, and SCR are biased by an RC-trigger circuit so that the ESD protection circuit is in a high impedance state. During an ESD event while the chip is unpowered, the RC-trigger circuit outputs trigger signals that cause the SCR, NFET, and PFET to enter into conductive states and cooperatively to shunt ESD currents away from the protected pad.

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract: A semiconductor device includes: a semiconductor substrate having a first conductivity type; a well having a second conductivity type and provided inside the semiconductor substrate; a first impurity region having the first conductivity type and provided within the well; a second impurity region having the second conductivity type, provided inside the well and away from the first impurity region; and a third impurity region having a first conductivity type, provided surrounding the well and away from the second impurity region. In this semiconductor device, the well is formed to be deeper than the first impurity region, the second impurity region, and the third impurity region, in a thickness direction of the semiconductor substrate; and a minimum distance between the first impurity region and the second impurity region is smaller than a minimum distance between the second impurity region and the third impurity region.

Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.

Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

Abstract: An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.

Abstract: A technique for enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: Provided is an electrostatic discharge (ESD) protection circuit including a multi-finger transistor. The multi-finger transistor includes a plurality of drains and a plurality of sources alternately arranged in parallel, and a plurality of gate electrodes arranged between the drains and the sources. The drains are electrically coupled to an input/output pad through a plurality of first finger patterns which are coupled to a plurality of first contact patterns. The sources are electrically coupled to a specific voltage line through a path which comprises a plurality of second finger patterns coupled to a plurality of second contact patterns. The number of the first contact patterns corresponding to the drains is gradually reduced as the distance to the voltage line becomes shorter.

Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.

Abstract: An electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, comprises, first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first width and second width. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vtl and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vtl, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

Abstract: A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A silicon control rectifier and an electrostatic discharge protection device of an integrated circuit including the silicon control rectifier. The silicon control rectifier includes a silicon body formed in a silicon layer in direct physical contact with a buried oxide layer of a silicon-on-insulator substrate, a top surface of the silicon layer defining a horizontal plane; and an anode of the silicon control rectifier formed in a first region of the silicon body and a cathode of the silicon control rectifier formed in an opposite second region of the silicon body, wherein a path of current flow between the anode and the cathode is only in a single horizontal direction parallel to the horizontal plane.

Abstract: A metal line in a semiconductor device includes an insulation layer having trenches formed therein, a barrier metal layer formed over the insulation layer and the trenches, a metal layer formed over the barrier metal layer, wherein the metal layer fills the trenches, and an anti-galvanic corrosion layer formed on an interface between the metal layer and the barrier metal layer.

Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.

Abstract: An ESD protection system providing extra headroom at an integrated circuit (IC) terminal pad. The system includes an ESD protection circuit having one or more first diodes coupled in series between the supply voltage and terminal pad, and a second diode coupled to ground. One or more third diodes are coupled in series between the terminal pad and second diode, and are configured to permit a voltage on the interconnection nodes between the one or more third diodes and second diode different from ground. The one or more third diodes include an n+ on an area of P-substrate. A deep N-well separates the area of P-substrate from a common area of P-substrate, which is coupled to ground. The allowable signal swing at the terminal pad is increased to greater than supply voltage plus 1.4 V. The ESD protection circuit is useful for, among other things, relatively low supply voltage ICs.

Abstract: The present invention relates to electrostatic discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enters a snapback region and begins to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: The present invention relates to methods and devices for reducing the threshold voltage difference between an n-type field effect transistor (n-FET) and a p-type field effect transistor (p-FET) in a complementary metal-oxide-semiconductor (CMOS) circuit located on a silicon-on-insulator (SOI) substrate. Specifically, a substrate bias voltage is applied to the CMOS circuit for differentially adjusting the threshold voltages of the n-FET and the p-FET. For example, a positive substrate bias voltage can be used to reduce the threshold voltage of the n-FET but increase that of the p-FET, while a negative substrate bias voltage can be used to increase the threshold voltage of the n-FET but reduce that of the p-FET. Further, two or more substrate bias voltages of different magnitudes and/or directions can be used for differentially adjusting the n-FET and p-FET threshold voltages in two or more different CMOS circuits or groups of CMOS circuits.

Abstract: A semiconductor device for electrostatic discharge (ESD) protection includes a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

Abstract: A driving circuit, which drives a display panel in a voltage range between a high negative voltage and a high positive voltage, includes: an electric charge discharging circuit; and a test external terminal. The electric charge discharging circuit connects a first terminal supplied with the high negative voltage to a second terminal of a ground voltage in response to a drop of a power source voltage. The test external terminal is connected to the electric charge discharging circuit. The high negative voltage is supplied to the semiconductor substrate. The electric charge discharging circuit interrupts a connection between the first terminal and the second terminal based on a control signal from the test external terminal.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A semiconductor structure. The semiconductor structure includes a semiconductor layer, a charge accumulation layer on top of the semiconductor layer, a doped region in direct physical contact with the semiconductor layer; and a device layer on and in direct physical contact with the charge accumulation layer. The charge accumulation layer includes trapped charges of a first sign. The doped region and the semiconductor layer forms a P?N junction diode. The P?N junction diode includes free charges of a second sign opposite to the first sign. The trapped charge in the charge accumulation layer exceeds a preset limit above which semiconductor structure is configured to malfunction. A first voltage is applied to the doped region. A second voltage is applied to the semiconductor layer. A third voltage is applied to the device layer. The third voltage exceeds the first voltage and the second voltage.

Abstract: An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions.

Abstract: An electrostatic discharge protection device and methodology are provided for protecting semiconductor devices against electrostatic discharge events by temporarily forming during normal (non-ESD) operation two more inversion layers (112, 113) in a first well region (104) that is disposed between anode and cathode regions (105, 106) in response to one or more bias voltages (G1, G2) that are close to Vdd in order to reduce leakage current and capacitance during normal operation (non-ESD) condition. During an electrostatic discharge event, the bias voltages can be removed (e.g., decoupled or set to 0V) to eliminate the inversion layers, thereby forming a semiconductor resistor for shunting the ESD current.

Abstract: A method and apparatus for crystallizing a semiconductor that includes a first layer having a first crystal lattice orientation and a second layer having a second crystal lattice orientation, comprising amorphizing at least a portion of the second layer, applying a stress to the second layer and heating the second layer above a recrystallization temperature.

Abstract: A breakdown voltage of a clamp diode can be reduced while a leakage current is suppressed. A P? type diffusion layer is formed in a surface of an N? type semiconductor layer. An N+ type diffusion layer is formed in a surface of the P? type diffusion layer. A P+ type diffusion layer is formed adjacent the N+ type diffusion layer in the surface of the P? type diffusion layer. An N+ type diffusion layer is formed adjacent the P? type diffusion layer in the surface of the N? type semiconductor layer. There is formed a cathode electrode, which is electrically connected with the N+ type diffusion layer through a contact hole formed in an insulation film on the N+ type diffusion layer. There is formed a wiring (an anode electrode) connecting between the P+ type diffusion layer and the N+ type diffusion layer through a contact hole formed in the insulation film on the P+ type diffusion layer and a contact hole formed in the insulation film on the N+ type diffusion layer.

Abstract: In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

Abstract: A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, formed on part of a surface region of the first well shallower than the first well, and a third well of a conductivity type opposite to that of the semiconductor substrate, formed in a surface region of the first well, in a region where the second well is not formed and shallower than the first well, by having a fourth well, formed in a region of the main surface of the semiconductor substrate where the first well is not formed and doped with impurities of the same conductivity type as the semiconductor substrate at a lower concentration than the third well, and controlling a reference voltage to be low, it is possible suppress the occurrence of a latch up phenomenon.

Abstract: The invention provides an electrostatic discharge (ESD) protection device with an increased capability to discharge ESD generated current with a reduced device area. The ESD protection device comprises a grounded gate MOS transistor (1) with a source region (3) and a drain region (4) of a first semiconductor type interposed by a first well region (7) of a second semiconductor type. Second well regions (6) of the first semiconductor type, interposed by the first well region (7), are provided beneath the source region (3) and the drain region (4). Heavily doped buried regions (8,9) of the same semiconductor types, respectively, as the adjoining well regions (6,7) are provided beneath the well regions (6,7).

Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.

Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: Disclosed herein is a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the standard cells, wherein each of the gate electrodes of the standard cells and the reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.

Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.

Abstract: In a CMOS implemented free or parasitic pnp transistor, triggering is controlled by introducing a low side zener reference voltage.

Abstract: Provided is a semiconductor device including an electrostatic discharge (ESD) protection element provided between an external connection terminal and an internal circuit region. In the semiconductor device, interconnect extending from the external connection terminal to the ESD protection element includes a plurality of metal interconnect layers so that a resistance of the interconnect extending from the external connection terminal to the ESD protection element is made smaller than a resistance of interconnect extending from the ESD protection element to an internal element. The interconnect extending from the ESD protection element to the internal element includes metal interconnect layers equal to or smaller in number than the plurality of interconnect layers used in the interconnect extending from the external connection terminal to the ESD protection element.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.

Abstract: The present invention is directed to an electrostatic discharge (ESD) device with an improved ESD robustness for protecting output buffers in I/O cell libraries. The ESD device according to the present invention uses a novel I/O cell layout structure for implementing a turn-on restrained method that reduces the turn-on speed of an ESD guarded MOS transistor by adding a pick-up diffusion region and/or varying channel lengths in the layout structure.