In Complementary Field Effect Transistor Integrated Circuit Patents (Class 257/357)
-
Patent number: 7888739Abstract: An electrostatic discharge circuit between a first pad and a second pad including an electrostatic discharge circuit element, including a bipolar transistor path and a resistor path, the electrostatic discharge circuit element alternately discharging an electrostatic current through the bipolar transistor path and the resistor path.Type: GrantFiled: August 11, 2005Date of Patent: February 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Chan-hee Jeon, Han-gu Kim, Sung-pil Jang
-
Patent number: 7880235Abstract: A semiconductor integrated circuit device has an SOI substrate comprising an insulating film laminated on a semiconductor support substrate and a semiconductor thin film laminated on the insulating film. A first N-channel MOS transistor, a first P-channel MOS transistor, and a resistor are each disposed on the semiconductor thin film. A second N-channel MOS transistor serving as an electrostatic discharge (ESD) protection element is disposed on a surface of the semiconductor support substrate that is exposed by removing a part of the semiconductor thin film and a part of the insulating film. The second N-channel MOS transistor has a gate electrode, a source region and a drain region surrounding the source region through the gate electrode to maintain a constant distance between the drain region and the source region.Type: GrantFiled: December 12, 2006Date of Patent: February 1, 2011Assignee: Seiko Instruments Inc.Inventor: Naoto Saitoh
-
Patent number: 7880206Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.Type: GrantFiled: July 17, 2009Date of Patent: February 1, 2011Assignee: Crosstek Capital, LLCInventor: Hee-Jeong Hong
-
Patent number: 7868391Abstract: A 3-D (Three Dimensional) inverter having a single gate electrode. The single gate electrode has a first gate dielectric between the gate electrode and a body of a first FET (Field Effect transistor) of a first doping type, the first FET having first source/drain regions in a semiconductor substrate, or in a well in the semiconductor substrate. The single gate electrode has a second gate dielectric between the gate electrode and a body of a second FET of opposite doping to the first FET. Second source/drain regions of the second FET are formed from epitaxial layers grown over the first source/drain regions.Type: GrantFiled: June 4, 2009Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Phil Christopher Felice Paone, David P. Paulsen, John E. Sheets, II, Kelly L. Williams
-
Patent number: 7863687Abstract: A semiconductor apparatus includes an internal circuit, a CMOS composed of a P-channel MOS transistor with a source connected to a high-potential power supply line and a gate connected to the internal circuit, and an N-channel MOS transistor with a source connected to a low-potential power supply line and a gate connected to the internal circuit, an output terminal connected to a drain of the P-channel MOS transistor and a drain of the N-channel MOS transistor and a protection transistor with a source and a gate connected to one power supply line of the high-potential power supply line and the low-potential power supply line and a drain connected to the output terminal, a conductivity type of the protection transistor being the same as a conductivity type of one MOS transistor of the P-channel MOS transistor and the N-channel MOS transistor, the source of the one MOS transistor being connected to the one power supply line.Type: GrantFiled: May 28, 2008Date of Patent: January 4, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hideaki Sai
-
Publication number: 20100320539Abstract: A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively.Type: ApplicationFiled: May 27, 2010Publication date: December 23, 2010Applicant: NEC Electronics CorporationInventor: Hiroshi Furuta
-
Patent number: 7855420Abstract: A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: GrantFiled: March 6, 2008Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
-
Patent number: 7855419Abstract: An improved layout pattern for electrostatic discharge protection is disclosed. A first heavily doped region of a first type is formed in a well of said first type. A second heavily doped region of a second type is formed in a well of said second type. A battlement layout pattern of said first heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. A battlement layout pattern of said second heavily doped region is formed along the boundary of said first heavily doped region and said second heavily doped region. By adjusting a distance between the battlement layout pattern of a heavily doped region and a edge of well of said second type, i.e. n-well, a first distance will be shorter than what is typically required by the layout rules of internal circuit; and a second distance will be longer than the first distance to ensure that the I/O device have a better ESD protection capability.Type: GrantFiled: June 15, 2006Date of Patent: December 21, 2010Assignee: Himax Technologies LimitedInventor: Tung-Yang Chen
-
Patent number: 7851864Abstract: A test structure includes a transistor, a dummy transistor and a pad unit. The transistor is formed on a first active region of a substrate. The dummy transistor is formed on a second active region of the substrate and electrically connected to the transistor. The pad unit is electrically connected to the transistor. Plasma damage to the transistor is reduced due to the presence of dummy transistor.Type: GrantFiled: July 18, 2008Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Young Chung, Ji-Hae Kim
-
Patent number: 7843010Abstract: An island of a crystalline semiconductor according to the present invention has an upper surface and a sloped side surface, which are joined together with a curved surface. Crystal grains in a body portion of the island, including the upper surface, and crystal grains in an edge portion of the island, including the sloped side surface, both have average grain sizes that are greater than 0.2 ?m.Type: GrantFiled: June 21, 2005Date of Patent: November 30, 2010Assignee: Sharp Kabushiki KaishaInventors: Tomohiro Kimura, Takuto Yasumatsu
-
Patent number: 7843009Abstract: An integrated circuit is made of a semiconductor material and comprises an input and/or terminal connected to an output transistor forming a parasitic element capable of triggering itself under the effect of an electrostatic discharge applied to the terminal. The integrated circuit comprises a protection device formed so as to be biased at the same time as the parasitic element under the effect of an electrostatic discharge, and more than the parasitic element to evacuate a discharge current as a priority.Type: GrantFiled: July 26, 2007Date of Patent: November 30, 2010Assignee: STMicroelectronics SAInventors: John Brunel, Nicolas Froidevaux
-
Patent number: 7838937Abstract: Circuits including a laterally diffused output driver transistor and a distinct device configured to provide electrostatic discharge (ESD) protection for the laterally diffused output driver transistor are presented. In general, the device configured to provide ESD protection includes a drain extended metal oxide semiconductor transistor (DEMOS) transistor configured to breakdown at a lower voltage than a breakdown voltage of the laterally diffused output driver transistor. The laterally diffused output driver transistor may be a pull-down or a pull-up output driver transistor. The device also includes a silicon controlled rectifier (SCR) configured to inject charge within a semiconductor layer of the circuit upon breakdown of the DEMOS transistor. Moreover, the device includes a region configured to collect the charge injected from the SCR and further includes an ohmic contact region configured to at least partially affect the holding voltage of the SCR.Type: GrantFiled: September 23, 2005Date of Patent: November 23, 2010Assignee: Cypress Semiconductor CorporationInventors: Andrew J. Walker, Helmut Puchner, Harold M. Kutz, James H. Shutt
-
Patent number: 7821076Abstract: There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer.Type: GrantFiled: April 12, 2009Date of Patent: October 26, 2010Assignee: Renesas Electronics CorporationInventors: Naozumi Morino, Atsushi Hiraiwa, Kazutoshi Oku, Toshiaki Ito, Motoshige Igarashi, Takayuki Sasaki, Masao Sugiyama, Hiroshi Yanagita, Shinichi Watarai
-
Patent number: 7812415Abstract: A semiconductor device including a gate insulating layer formed over a semiconductor substrate; a gate insulating layer pattern formed over an exposed uppermost surface of the semiconductor substrate along the same horizontal plane as the gate insulating layer; an isolation insulating layer formed over the gate insulating layer; a plurality of first gate conductive patterns formed over the gate insulating layer and the gate insulating layer pattern; a source/drain conductor formed over an exposed uppermost surface of the semiconductor substrate; a second gate conductive pattern formed over one of the plurality of the first gate conductive patterns that is provided over the gate insulating layer pattern; a plurality of salicide layers formed over the second gate conductive pattern, the source/drain conductor, and at least one of the plurality of first gate conductive patterns that are provided over the gate insulating layer; and a pair of spacers formed over the gate insulating layer pattern and on sidewalls oType: GrantFiled: November 23, 2007Date of Patent: October 12, 2010Assignee: Dongbu HiTek Co., Ltd.Inventor: Jeong-Ho Park
-
Patent number: 7791514Abstract: A digital-to-analog converter includes MOS transistors formed in the identical configuration and arranged in a matrix array. Ones of the MOS transistors placed on the inner part of the array serve as constant current cells, while others placed around the inner MOS transistors function as dummy transistors and a MOS capacitance. Each dummy transistor has its gate, source and drain electrodes connected to a metal strip to which the gate electrode of each constant current cells is connected. Thus, the gate electrodes of the constant current cells are connected to a substrate or potential well via diodes consisting of the dummy transistors, thereby electric charges generated in metal strips due to plasma etching and like treatment being discharged through the diodes to the substrate or potential well. The digital-to-analog converter is thus able to produce even constant currents.Type: GrantFiled: January 13, 2009Date of Patent: September 7, 2010Assignee: Oki Semiconductor Co., Ltd.Inventor: Katsuyoshi Yagi
-
Patent number: 7781841Abstract: Certain embodiments of the invention may be found in, for example, a system that reduces noise in a substrate of a chip and may comprise a substrate layer that is integrated within the chip. A transistor layer is integrated within the chip and is shielded from the substrate layer by a shielding layer. At least one transistor of a first transistor type couples the transistor layer to the shielding layer and a quiet voltage source may be coupled to the transistor of the first transistor type. At least one transistor of a second transistor type is coupled to the shielding layer. The transistor of the second transistor type may be a n-type transistor, which may be disposed within the transistor layer and the transistor of the second transistor type may be resistively coupled to the shielding layer.Type: GrantFiled: March 15, 2004Date of Patent: August 24, 2010Inventor: Ichiro Fujimori
-
Publication number: 20100201427Abstract: A level shifter circuit for integrated circuits has one or more inputs that operate in a first voltage domain, and a signal output that operates in a second voltage domain. In some embodiments, the level shifter circuit receives two complementary input signals. The level shifter uses cross-coupled PMOS transistors with drain-bulk breakdown voltage less than the gate-oxide breakdown voltage of high-voltage PMOS transistors to prevent gate-oxide breakdown caused by sub-threshold leakage of auxiliary high-voltage PMOS transistors in the off state. Permanent gate-oxide breakdown is prevented through non-permanent sub-nanoamp drain-bulk junction breakdown. The level shifter circuit has the advantages of small circuit size and low static power consumption.Type: ApplicationFiled: February 7, 2010Publication date: August 12, 2010Inventors: Leendert Jan van den Berg, Duncan George Elliott
-
Patent number: 7763908Abstract: A silicon-controlled rectifier apparatus, comprising a substrate upon which a low-voltage triggered silicon-controlled rectifier is configured. A plurality of triggering components (e.g., NMOS fingers) are formed upon the substrate and integrated with the low-voltage triggered silicon-controlled rectifier, wherein the plurality of triggering components are inserted into the low-voltage triggered silicon-controlled rectifier in order to permit the low-voltage triggered silicon-controlled rectifier to protect against electrostatic discharge during human-body model and charged-device model stress events.Type: GrantFiled: July 25, 2005Date of Patent: July 27, 2010Assignee: LSI CorporationInventor: Jau-Wen Chen
-
Patent number: 7763915Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.Type: GrantFiled: January 18, 2007Date of Patent: July 27, 2010Assignee: Commissariat a l'Energie AtomiqueInventors: Jean-Pierre Joly, Olivier Faynot, Laurent Clavelier
-
Patent number: 7759744Abstract: A semiconductor device 100 includes a silicon substrate 102, an N-type MOSFET 118 including a first high dielectric constant film 111 and a polycrystalline silicon film 114 on the silicon substrate 102, and a P-type MOSFET 120 including a second high dielectric constant film 12 and a polycrystalline silicon film 114 juxtaposed to N-type MOSFET 118 on the silicon substrate 102. The second high dielectric constant film 112 is formed to have the film thickness thinner than the film thickness of the first high dielectric constant film 111. The first high dielectric constant film 111 and the second high dielectric constant film 112 contains one or more element(s) selected from Hf and Zr.Type: GrantFiled: May 16, 2005Date of Patent: July 20, 2010Assignees: NEC Electronics Corporation, NEC CorporationInventors: Naohiko Kimizuka, Kiyotaka Imai, Yuri Masuoka, Toshiyuki Iwamoto, Motofumi Saitoh, Hirohito Watanabe, Masayuki Terai
-
Patent number: 7755143Abstract: A semiconductor device is described. The semiconductor device comprises a protected device in a protected device area of a substrate. An electrostatic discharge power clamp device comprising an outer first guard ring and an inner second guard ring is in a guard ring area of the substrate, enclosing the protected device. The first guard ring comprises a first well region having a first conductive type. A first doped region having the first conductive type and a second doped region having a second conductive type are in the first well region. The second guard ring comprises a second well region having a second conductive type. A third doped region has the second conductive type in the second well region. An input/output device is in a periphery device area, coupled to the electrostatic discharge power clamp device.Type: GrantFiled: July 22, 2008Date of Patent: July 13, 2010Assignee: Vanguard International Semiconductor CorporationInventors: Yeh-Ning Jou, Geeng-Lih Lin
-
Patent number: 7750403Abstract: An individual identifier is easily provided in a semiconductor device capable of wireless communication. The semiconductor device includes a thin film transistor including a channel forming region, an island-like semiconductor film including a source region and a drain region, a gate insulating film, and a gate electrode; an interlayer insulating film; a plurality of contact holes formed in the interlayer insulating film which reach one of the source region and the drain region; and a single contact hole which reaches the other of the source region and the drain region, wherein a diameter of the single contact hole is larger than a diameter of each of the plurality of contact holes, and a sum of areas of bases of the plurality of contact holes is equal to an area of a base of the single contact hole.Type: GrantFiled: June 19, 2007Date of Patent: July 6, 2010Assignee: Semiconductor Energy Laboratory Co., LtdInventors: Yutaka Shionoiri, Takuro Ohmaru
-
Patent number: 7750409Abstract: Provided is a semiconductor device including an n-type metal oxide semiconductor transistor for electrostatic discharge protection including drain regions connected with a first metal interconnect and source regions connected with another first metal interconnect alternately placed with each other, and gate electrodes each placed between each of the drain regions and each of the source regions, in which: at least one of the first metal interconnect and the other first metal interconnect being connected to a plurality of layers of metal interconnects other than the first metal interconnect; and the source regions include via-holes for electrically connecting the other first metal interconnect and the plurality of layers of metal interconnects other than the first metal interconnect, a greater number of the via-holes is formed as a distance of an interconnect connected to the NMOS transistor for ESD protection becomes larger.Type: GrantFiled: August 14, 2008Date of Patent: July 6, 2010Assignee: Seiko Instruments Inc.Inventors: Hiroaki Takasu, Takayuki Takashina, Sukehiro Yamamoto
-
Patent number: 7750407Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.Type: GrantFiled: December 18, 2006Date of Patent: July 6, 2010Assignee: Spansion LLCInventors: Wei Zheng, Jean Yang, Mark Randolph, Ming Kwan, Yi He, Zhizheng Liu, Meng Ding
-
Patent number: 7750400Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).Type: GrantFiled: August 15, 2008Date of Patent: July 6, 2010Assignee: Texas Instruments IncorporatedInventors: Ajit Shanware, Srikanth Krishnan
-
Patent number: 7746608Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).Type: GrantFiled: October 10, 2006Date of Patent: June 29, 2010Assignee: Texas Instruments IncorporatedInventors: Chih-Ming Hung, Charvaka Duvvury
-
Patent number: 7745890Abstract: A semiconductor device and system for a hybrid metal fully silicided (FUSI) gate structure is disclosed. The semiconductor system comprises a PMOS gate structure, the PMOS gate structure including a first high-? dielectric layer, a P-metal layer, a mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric layer, the P-metal layer and a fully silicided layer formed on the P-metal layer. The semiconductor system further comprises an NMOS gate structure, the NMOS gate structure includes a second high-? dielectric layer, the fully silicided layer, and the mid-gap metal layer, wherein the mid-gap metal layer is formed between the high-? dielectric and the fully silicided layer.Type: GrantFiled: September 28, 2007Date of Patent: June 29, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Cheng-Tung Lin, Cheng-Hung Chang, Hsiang-Yi Wang, Chen-Nan Yeh
-
Patent number: 7741164Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying a monocrystalline silicon substrate and separated therefrom by a dielectric layer. A well region is ion implanted in the monocrystalline silicon substrate. A gate electrode material is deposited overlying the monocrystalline silicon layer. The gate electrode material is photolithographically patterned and etched using a minimum lithography feature size to form a first gate electrode, a second gate electrode and a spacer having the minimum lithography feature size. The gate electrode material is then isotropically etched to reduce the width of the first gate electrode, the second gate electrode and the spacer.Type: GrantFiled: February 19, 2008Date of Patent: June 22, 2010Assignee: Advanced Micro Devices, Inc.Inventor: Mario M. Pelella
-
Patent number: 7741681Abstract: A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate between the I/O cell and an ESD protection circuit and at least one of the logic circuits.Type: GrantFiled: December 14, 2007Date of Patent: June 22, 2010Assignee: International Business Machines CorporationInventors: Phillip Francis Chapman, David S. Collins, Steven H. Voldman
-
Patent number: 7741680Abstract: The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region, which includes a voltage input terminal. The isolation layer is located between the backgate region and the substrate layer and has a doping type opposite that of the backgate region. The diode includes a first terminal connected to the isolation layer and a second terminal coupled to an isolation voltage source.Type: GrantFiled: August 13, 2008Date of Patent: June 22, 2010Assignee: Analog Devices, Inc.Inventors: Haiyang Zhu, David Foley
-
Patent number: 7737500Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.Type: GrantFiled: April 26, 2006Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: David M. Onsongo, Werner Rausch, Haining S. Yang
-
Patent number: 7709898Abstract: A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS.Type: GrantFiled: September 21, 2007Date of Patent: May 4, 2010Assignee: Panasonic CorporationInventor: Keita Takahashi
-
Patent number: 7709924Abstract: A semiconductor structure and a method for operating the same. The method includes providing a semiconductor structure. The semiconductor structure includes first, second, third, and fourth doped semiconductor regions. The second doped semiconductor region is in direct physical contact with the first and third doped semiconductor regions. The fourth doped semiconductor region is in direct physical contact with the third doped semiconductor region. The first and second doped semiconductor regions are doped with a first doping polarity. The third and fourth doped semiconductor regions are doped with a second doping polarity. The method further includes (i) electrically coupling the first and fourth doped semiconductor regions to a first node and a second node of the semiconductor structure, respectively, and (ii) electrically charging the first and second nodes to first and second electric potentials, respectively. The first electric potential is different from the second electric potential.Type: GrantFiled: July 16, 2007Date of Patent: May 4, 2010Assignee: International Business Machines CorporationInventor: Steven Howard Voldman
-
Patent number: 7709896Abstract: An ESD protection device includes a source region, a channel region adjacent the source region, and an elongated drain region spaced from the source region by the channel region. The elongated drain region includes an unsilicided portion adjacent the channel and a silicided portion spaced from channel region by the unsilicided portion. A first ESD region is located beneath the silicided portion of the elongated drain region and a second ESD region is located beneath the unsilicided portion of the elongated drain region, the second ESD region being spaced from the first ESD region.Type: GrantFiled: March 8, 2006Date of Patent: May 4, 2010Assignee: Infineon Technologies AGInventors: Cornelius Christian Russ, David Alvarez, Kiran V. Chatty, Jens Schneider, Robert Gauthier, Martin Wendel
-
Patent number: 7692247Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: July 26, 2007Date of Patent: April 6, 2010Assignee: Broadcom CorporationInventors: Agnes N. Woo, Kenneth R. Kindsfater, Fang Lu
-
Patent number: 7687862Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.Type: GrantFiled: May 13, 2008Date of Patent: March 30, 2010Assignee: Infineon Technologies AGInventors: Frank Huebinger, Richard Lindsay
-
Patent number: 7687858Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.Type: GrantFiled: January 3, 2008Date of Patent: March 30, 2010Assignee: Broadcom CorporationInventors: Agnes N. Woo, Kenneth R. Kindsfater, Fang Lu
-
Patent number: 7687859Abstract: An electronic circuit includes at least one field effect transistor that is to be protected against electrostatic discharge events, and at least one protection field effect transistor. The protection field effect transistor has a crystal orientation that is different from a crystal orientation of the field effect transistor to be protected.Type: GrantFiled: September 7, 2007Date of Patent: March 30, 2010Assignees: Infineon Technologies AG, IMEC VZW.Inventors: Christian Russ, David Trémouilles, Steven Thijs
-
Patent number: 7667330Abstract: A semiconductor device includes an input/output pad, an input line of an internal circuit, and a plurality of metal lines formed on a lower portion of the input/output pad to have a buffer area overlapping with a plane area of the input/output pad, wherein one of an entirety and a portion of the plurality of metal lines included in the buffer area forms protective resistance interconnecting the input/output pad to the input line.Type: GrantFiled: September 10, 2008Date of Patent: February 23, 2010Assignee: Hynix Semiconductor, Inc.Inventor: Si Woo Lee
-
Publication number: 20100038718Abstract: The present invention relates to a semiconductor device including a substrate layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), a backgate region, an isolation layer and a diode. The MOSFET includes a gate region, a source region and a drain region. The source and drain regions are embedded in the backgate region, which includes a voltage input terminal. The isolation layer is located between the backgate region and the substrate layer and has a doping type opposite that of the backgate region. The diode includes a first terminal connected to the isolation layer and a second terminal coupled to an isolation voltage source.Type: ApplicationFiled: August 13, 2008Publication date: February 18, 2010Inventors: Haiyang ZHU, David Foley
-
Publication number: 20100019295Abstract: A CMOS single photon avalanche diode (SPAD) design uses conventional, or at least known, CMOS processes to produce a device having a breakdown region in which the main p-n junction is formed of a deep n-well layer, and optionally on the other side, a p-add layer. The SPAD may also have a guard ring region which comprises the p-epi layer without any implant. The SPAD may have curved or circular perimeters. A CMOS chip comprises SPADs as described and other NMOS devices all sharing the same deep n-well.Type: ApplicationFiled: July 7, 2009Publication date: January 28, 2010Applicant: STMicroelectronics (Research & Development) LimitedInventors: Robert K. Henderson, Justin Richardson
-
Patent number: 7646067Abstract: A CMOS transistor and a method of manufacturing the CMOS transistor are disclosed. An NMOS transistor is formed on a first region of a semiconductor substrate. A PMOS transistor is formed on a second region of a semiconductor substrate. The NMOS transistor includes a first gate conductive layer. The PMOS transistor includes a second gate conductive layer. The first gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.0 eV to about 4.3 eV. The third gate conductive layer includes a metal having a nitrogen concentration increasing in a direction from a lower portion toward an upper portion. In addition, the metal has a work function of about 4.7 eV to about 5.0 eV.Type: GrantFiled: August 10, 2007Date of Patent: January 12, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Gab-Jin Nam, Myoung-Bum Lee
-
Patent number: 7642601Abstract: In a semiconductor integrated circuit device and a method of designing the same, design information about circuit cells each having a desired function are described as objects according to selected purposes. The pieces of design information are registered in a cell library as cell information capable of forming any of substrate potential fixed cells and substrate potential variable cells. Further, a data sheet common to the substrate potential fixed cell and the substrate potential variable cell is offered to a user, so that the user is able to make a selection according to the user's purposes. The substrate potential fixed cells and the substrate potential variable cells are mixed together on a semiconductor chip so as to be properly used according to the functions or the like of circuit portions in which the cells are used.Type: GrantFiled: May 18, 2009Date of Patent: January 5, 2010Assignee: Renesas Technology Corp.Inventors: Ryuji Shibata, Shigeru Shimada
-
Patent number: 7638847Abstract: An ESD protection structure includes, in part, a NMOS transistor having a source and drain in a well in a substrate and a gate on the substrate with the source and drain being connected between ground and a series diode, and the gate being connected to ground. The structure further includes a diode having a cathode connected to the input pad and an anode connected to the well so that the diode is reverse-biased in the event of a positive voltage ESD event on the input pad. As a result, in a positive voltage ESD event, the avalanche effect rapidly injects current into the substrate and therefore into the base of the parasitic bipolar transistor so as to trigger the transistor into conduction and discharge the ESD pulse. Alternatively, the diode is a Zener diode and the current is generated by the Zener effect. A complementary structure provides protection against a negative ESD pulse.Type: GrantFiled: January 25, 2006Date of Patent: December 29, 2009Assignee: Altera CorporationInventors: Hugh Sungki O, Chih-Ching Shih, Cheng-Hsiung Huang, Yow-Juang Bill Liu
-
Publication number: 20090294856Abstract: A technique to enhancing substrate bias of grounded-gate NMOS fingers (ggNMOSFET's) has been developed. By using this technique, lower triggering voltage of NMOS fingers can be achieved without degrading ESD protection in negative zapping. By introducing a simple gate-coupled effect and a PMOSFET triggering source with this technique, low-voltage triggered NMOS fingers have also been developed in power and I/O ESD protection, respectively. A semiconductor device which includes a P-well which is underneath NMOS fingers. The device includes an N-well ring which is configured so that the inner P-well underneath the NMOS fingers is separated from an outer P-well. The inner P-well and outer P-well are connected by a P-substrate resistance which is much higher than the resistance of the P-wells. A P+-diffusion ring surrounding the N-well ring is configured to connect to VSS, i.e., P-taps.Type: ApplicationFiled: July 21, 2009Publication date: December 3, 2009Applicant: LSI CORPORATIONInventor: Jau-Wen Chen
-
Publication number: 20090294847Abstract: A plasma display apparatus which in its driving circuit mounts at least one of IGBTs having diodes built-in which are reverse conducting in a driving device which supplies a light emitting current and IGBTs having diodes built-in which have a reverse blocking function in a driving device which collects and charges the power.Type: ApplicationFiled: August 5, 2009Publication date: December 3, 2009Inventor: Mutsuhiro Mori
-
Patent number: 7608896Abstract: A semiconductor device has an n-channel MIS transistor and a p-channel MIS transistor on a substrate. The n-channel MIS transistor includes a p-type semiconductor region formed on the substrate, a lower layer gate electrode which is formed via a gate insulating film above the p-type semiconductor region and which is one monolayer or more and 3 nm or less in thickness, and an upper layer gate electrode which is formed on the lower layer gate electrode, whose average electronegativity is 0.1 or more smaller than the average electronegativity of the lower layer gate electrode. The p-channel MIS transistor includes an n-type semiconductor region formed on the substrate and a gate electrode which is formed via a gate insulating film above the n-type semiconductor region and is made of the same metal material as that of the upper layer gate electrode.Type: GrantFiled: September 18, 2007Date of Patent: October 27, 2009Assignee: Kabushiki Kaisha ToshibaInventors: Reika Ichihara, Yoshinori Tsuchiya, Hiroki Tanaka, Masato Koyama
-
Patent number: 7605059Abstract: A semiconductor device comprises: a MOS transistor including: a semiconductor substrate; a source region, formed in the semiconductor substrate, that comprises an impurity of a first conductive type; a drain region, formed in the semiconductor substrate, that comprises an impurity of the first conductive type; and a gate electrode, formed through a gate insulating film on the semiconductor substrate, between the source region and the drain region; an impurity region of the first conductive type formed in the semiconductor substrate; an impurity region of a second conductive type to be opposite to the first conductive type formed in the semiconductor substrate; and a wiring provided to connect each of the impurity region of the first conductive type and the impurity region of the second conductive type to the gate electrode.Type: GrantFiled: May 25, 2007Date of Patent: October 20, 2009Assignee: Fujifilm CorporationInventors: Noriaki Suzuki, Masanori Nagase
-
Patent number: 7598605Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.Type: GrantFiled: July 31, 2006Date of Patent: October 6, 2009Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
-
Patent number: 7589384Abstract: It is made possible to easily set a protection voltage even when a semiconductor device to be protected includes a gate insulating film having a low dielectric breakdown voltage.Type: GrantFiled: April 14, 2006Date of Patent: September 15, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Atsuhiro Kinoshita