Abstract: The invention provides a color display device structure, including a substrate (1), an anode (21), a thin film transistor array (23), a hole injection layer (24), a hole transport layer (25), a light emitting layer (26), an electron transport layer (27), a cathode (28), a cover plate (3), a color conversion layer (4) formed on the inner side of the cover plate (3), and a sealant (6). The light emitting layer (26) is a blue and green light emitting layer (26). The color conversion layer (4) includes a blue filter unit (41), a green filter unit (43) and a red conversion unit (45) separated one another. The blue light and the green light emitted by the blue and green light emitting layer (26) is filtered to become blue light by the blue filter unit (41). The blue light and the green light emitted by the blue and green light emitting layer (26) is filtered to become green light by the green filter unit (43).

Abstract: A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack.

Abstract: A display device includes a first substrate, a second substrate, a space layer, and a protective film. The first substrate has a first surface, and the second substrate comprises a visible region and a non-visible region. The second substrate has a second surface, and the second surface is opposite to the first surface. The space layer includes a plurality of spacers and at least one space component. The spacers are located on the visible region, and the space component is located in the non-visible region. The protective film has water vapor barrier property. The protective film covers the space component, and forms at least one barrier wall. The barrier wall touches the first surface and the second surface.

Abstract: A new driving method of a display device that makes it possible to reduce power consumption and to improve display quality is proposed. A first gray scale is displayed in all pixels in a first initialization period, a second gray scale is displayed in all the pixels in a second initialization period, an objective image is displayed in a writing period, and the image is held in a holding period. Alternatively, an electrical history of a gray scale storage display element for displaying a number of gray scales is erased in the first initialization period and the second initialization period. Alternatively, a potential of a common electrode is changed in the first initialization period, the second initialization period, the writing period, and the holding period. Alternatively, a potential of a capacitor wiring is changed in synchronization with the potential of the common electrode.

Abstract: A flat panel detector includes a photoelectric conversion layer and a pixel detecting element disposed under the photoelectric conversion layer. The pixel detecting element includes: a pixel electrode for receiving charges, a storage capacitor for storing the received charges, and a thin film transistor for controlling outputting of the stored charges. The storage capacitor includes a first electrode and a second electrode. The first electrode includes an upper electrode and a bottom electrode that are disposed opposite to each other and electrically connected. A second electrode is sandwiched between the upper electrode and the bottom electrode. It is insulated between the upper electrode and the second electrode and between the second electrode and the bottom electrode.

Abstract: A thin-film semiconductor device having two thin-film transistors, wherein each of the two thin-film transistors includes: a gate electrode; a gate insulating film; a semiconductor layer; a channel protection layer; an intrinsic semiconductor layer; a contact layer in contact with a portion of sides of the channel region; a source electrode on the contact layer; and a drain electrode opposite to the source electrode on the contact layer, wherein the contact layer of one of the two thin-film transistors has a conductivity type different from a conductivity type of the contact layer of the other of the two thin-film transistors.

Abstract: An integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which has a body region that is implanted concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and has a resistor silicide block layer over the body region which is formed of separate material from the sidewall spacers on the CMOS gates. A process of forming an integrated circuit containing CMOS gates and a counterdoped polysilicon gate material resistor which implants the body region of the resistor concurrently with the NSD layers of the NMOS transistors of the CMOS gates and concurrently with the PSD layers of the PMOS transistors of the CMOS gates, and forms a resistor silicide block layer over the body region of separate material from the sidewall spacers on the CMOS gates.

Abstract: A semiconductor structure with a high voltage area and a low voltage area includes a substrate of a first conductivity type accommodating the high voltage area and the low voltage area. A resistor is on the substrate, connecting the high voltage area and the low voltage area, and the resistor resides substantially in the high voltage area. The structure further includes a first doped region of the first conductivity type in the substrate between the high voltage area and the low voltage area, and a second doped region of a second conductivity type between the substrate and the first doped region. Moreover, an insulating layer is formed between the resistor and the first doped region.

Abstract: A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.

Abstract: A production method for a liquid crystal display device having a plurality of thin film transistors (TFTs) including reflection sections disposed to correspond to a plurality of pixels includes: a step of forming on a substrate a metal layer having apertures; a step of forming a semiconductor layer on the metal layer; a step of forming a protection layer on the semiconductor layer; a step of forming a resist layer on the protection layer; a photolithography step of irradiating the resist layer with light through the metal layer to pattern the protection layer by photolithography technique; and a step of stacking a reflective layer on the patterned protection layer. A plurality of bumps are formed from the protection layer in the photolithography step, and a plurality of bumps corresponding to the plurality of bumps of the protection layer are formed on the reflective layer.

Abstract: A repairing method, repairing device and repairing structure for repairing a signal line of an array substrate having the disconnected defect, including: setting a repairing route according to a position of the disconnected defect and determining a position at which a filling portion is required to be formed according to the repairing route; forming the filling portion at the position at which the filling portion is required to be formed; and forming a repairing line along the repairing route. By detecting the repairing route before repairing the disconnected defect by forming the filling portion according to the repairing route, the present disclosure can avoid the disconnection of the repairing line caused by great height differences of the surface under the repairing line and improve the repairing success rate of the disconnected defect.

Abstract: A device comprises a semiconductor substrate having first and second implant regions of a first dopant type. A gate insulating layer and a gate electrode are provided above a resistor region between the first and second implant regions. A first dielectric layer is on the first implant region. A contact structure is provided, including a first contact portion conductively contacting the gate electrode, at least part of the first contact portion directly on the gate electrode. A second contact portion directly contacts the first contact portion and is formed directly on the first dielectric layer. A third contact portion is formed on the second implant region.

Abstract: A fin resistor and method of fabrication are disclosed. The fin resistor comprises a plurality of fins arranged in a linear pattern with an alternating pattern of epitaxial regions. An anneal diffuses dopants from the epitaxial regions into the fins. Contacts are connected to endpoint epitaxial regions to allow the resistor to be connected to more complex integrated circuits.

Abstract: To increase the integration degree of a semiconductor device, the semiconductor device having a Plasma-Induced Damage (PID) protective diode includes a well, at least a first transistor region formed over the well, a gate electrode formed over the first transistor region, a well guard disposed to include an open region while surrounding the first transistor region, a diode disposed in the open region, and a metal line configured to electrically connect the gate electrode and the diode. A space between transistor regions may be efficiently reduced, thus increasing the integration degree of a semiconductor device.

Abstract: A CMOS SGT manufacturing method includes a step of forming first and second fin-shaped silicon layers on a substrate, forming a first insulating film around the first and second fin-shaped silicon layers, and forming first and second pillar-shaped silicon layers; a step of forming n-type diffusion layers; a step of forming p-type diffusion layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers in upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing the first and second polysilicon gate electrodes, etching the first and second polysilicon gate electrodes, and then depositing a metal to form first and second metal gate electrodes.

Abstract: Provided is a flexible substrate wherein a connection portion between the flexible substrate and an electric circuit board meets requirements of narrow wiring pitch and low resistance at the connection portion. An electric circuit structure, which has the flexible substrate and the electric circuit board to which the flexible substrate is connected, is also provided. A wiring pattern (22) is formed on a flexible base film (21), a connection terminal (25) connected electrically to an electrode terminal of another electric circuit board is arranged at an end portion of the wiring pattern (22), and the connection terminal (25) includes wide connection terminals (25b, 25c) having a terminal width extending across plural lines of the wiring pattern (22).

Abstract: Disclosed is a semiconductor device and a method of manufacturing the same. The semiconductor device includes first material layers and second material layers alternately stacked on a first conductive layer. Through holes, each through holes including a first through region, second through region and trench, wherein the first and second through regions pass through the first and second material layers, and the trench is formed in the first conductive layer to connect the first through region and the second through region. Resistive layers, each resistive layer including a first region are disposed in the first through region, a second region disposed in the second through region, and a third region disposed in the trench.

Abstract: A semiconductor device has a semiconductor substrate, a field insulating film disposed on a surface of the semiconductor substrate, a base insulating film disposed on a surface of the field insulating film, and a resistor disposed on the base insulating film. The resistor is formed of a polycrystalline silicon film and has a resistance region and electrode lead-out regions disposed at both ends of the resistance region. A portion of the base insulating film below the resistance region projects with respect to portions of the base insulating film below the electrode lead-out regions so that a height difference occurs therebetween. The resistance region has a thickness thinner than that of each of the electrode lead-out regions.

Abstract: The present invention discloses an isolated SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a first high density doped region located in the first well and having a second conductivity type; a second well nearby the first well and having the second conductivity type; a second high density doped region located in the second well and having the second conductivity type; and a third high density doped region located in the second well and having the first conductivity type, wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad.

Abstract: A manufacturing method for a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor, a transitional structure, and a dielectric layer covering the transistor and the transitional structure formed thereon, forming a recess in between two opposite polysilicon end portions in the transitional structure, forming a U-shaped resistance modulating layer and an insulating layer filling the recess, removing a dummy gate of the transistor and the polysilicon end portions of the transitional structure to form a gate trench and two terminal trenches respectively in the transistor and the transitional structure, and forming a metal gate in the gate trench and conductive terminals in the terminal trenches simultaneously.

Abstract: Drive units arranged on a transistor array substrate include faulty drive units. The pixel electrodes include first pixel electrodes and second pixel electrodes, the first pixel electrodes corresponding one-to-one to the faulty drive units, and the second pixel electrodes corresponding one-to-one to the non-faulty drive units, a portion of each second pixel electrode is embedded in the contact hole corresponding thereto, and is in contact with a power supply pad of the non-faulty drive unit corresponding thereto, so that the second pixel electrode is electrically connected to the non-faulty drive unit. Each first pixel electrode is electrically insulated from the faulty drive unit corresponding thereto, and is connected by a connector to any of the second pixel electrodes adjacent thereto. A surface of each connector facing the interlayer insulation film is entirely in contact with the interlayer insulation film.

Abstract: The present disclosure is directed to an integrated circuit having a substrate and a first and a second interconnect structure over the substrate. Each interconnect structure has a first conductive layer over the substrate and a second conductive layer over the first conductive layer. The integrated circuit also includes a thin film resistor over a portion of the substrate between the first and the second interconnect structure that electrically connects the first conductive layers of the first and second interconnect structures.

Abstract: Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.

Abstract: A thin film transistor is provided, which includes a gate insulating layer covering a gate electrode, a microcrystalline semiconductor layer provided over the gate insulating layer, an amorphous semiconductor layer overlapping the microcrystalline semiconductor layer and the gate insulating layer, and a pair of impurity semiconductor layers which are provided over the amorphous semiconductor layer and to which an impurity element imparting one conductivity type is added to form a source region and a drain region. The gate insulating layer has a step adjacent to a portion in contact with an end portion of the microcrystalline semiconductor layer. A second thickness of the gate insulating layer in a portion outside the microcrystalline semiconductor layer is smaller than a first thickness thereof in a portion in contact with the microcrystalline semiconductor layer.

Abstract: A method for fabricating a flexible semiconductor device includes: preparing a layered film 80 including a first metal layer 10, an inorganic insulating layer 20, a semiconductor layer 30, and a second metal layer 40 which are sequentially formed; etching the first metal layer 10 to form a gate electrode 12g; compression bonding a resin layer 50 to a surface of the layered film 80 provided with the gate electrode 12g to allow the gate electrode 12g to be embedded in the resin layer 50; and etching the second metal layer 40 to form a source electrode 42s and a drain electrode 42d, wherein the inorganic insulating layer 20 on the gate electrode 12g functions as a gate insulating film 22, and the semiconductor layer 30 between the source electrode 42s and drain electrode 42d on the inorganic insulating layer 20 functions as a channel 32.

Abstract: One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

Abstract: An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology.

Abstract: A semiconductor device includes a thin-film diode (1) and a protection circuit with a protection diode (20). The thin-film diode (1) includes: a semiconductor layer with first, second and channel regions; a gate electrode; a first electrode (S1) connected to the first region and the gate electrode; and a second electrode (D1) connected to the second region. The conductivity type of the thin-film diode (1) may be N-type and the anode electrode of the protection diode (20) may be connected to a line (3) that is connected to either the gate electrode or the first electrode of the thin-film diode (1). Or the conductivity type of the thin-film diode may be P-type and the cathode electrode of the protection diode may be connected to the line that is connected to either the gate electrode or the first electrode of the thin-film diode. The protection circuit includes no other diodes that are connected to the line (3) so as to have a current flowing direction opposite to the protection diode's (20).

Abstract: A semiconductor body includes a protective structure. The protective structure (10) includes a first and a second region (11, 12) which have a first conductivity type and a third region (13) that has a second conductivity type. The second conductivity type is opposite the first conductivity type. The first and the second region (11, 12) are arranged spaced apart in the third region (13), so that a current flow from the first region (11) to the second region (12) is made possible for the limiting of a voltage difference between the first and the second region (11, 12). The protective structure includes an insulator (14) that is arranged on the semiconductor body (9) and an electrode (16) that is constructed with floating potential and is arranged on the insulator (14).

Abstract: The present invention relates to a touching-type electronic paper and method for manufacturing the same. The touching-type electronic paper includes a TFT substrate and a transparent electrode substrate which are disposed as a cell. The transparent electrode substrate includes a common electrode, microcapsule electronic ink and light guiding poles as light transmitting passages, all of which are formed on a first substrate. The TFT substrate comprises displaying electrodes, first TFTs for driving the displaying electrodes, second TFTs for detecting lights transmitting through the light guiding poles and for producing level signals, and third TFTs for reading the level signals and sending the level signals to a back-end processing system, all of which are formed on a second substrate. The light guiding poles are opposite to the second TFTs respectively.

Abstract: In a method of manufacturing a semiconductor device, a barrier metal film and an aluminum metal film are formed on an insulating film on a semiconductor substrate. Two aluminum electrodes are formed in parallel with each other by patterning the barrier metal film and the aluminum metal film. The aluminum metal film in a region of part of each of the two aluminum electrodes are selectively removed to form two single-layer barrier metal electrodes separated from each other. A resistor is formed between the two single-layer barrier metal electrodes so as to electrically connect the two single-layer barrier metal electrodes to each other.

Abstract: A transistor device having a metallic source electrode, a metallic drain electrode, a metallic gate electrode and a channel in a deposited semiconductor material, the transistor device comprising: a first layer comprising the metallic gate electrode, a first metal portion of the metallic source electrode and a first metal portion of the metallic drain electrode; a second layer comprising a second metal portion of the metallic source electrode, a second metal portion of the metallic drain electrode, the deposited semiconductor material and dielectric material between the semiconductor material and the metallic gate electrode; and a third layer comprising a substrate, wherein the first, second and third layers are arranged in order such that the second layer is positioned between the first layer and the third layer.

Abstract: A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.

Abstract: In a replacement gate approach, the semiconductor material or at least a significant portion thereof in a non-transistor structure, such as a precision resistor, an electronic fuse and the like, may be preserved upon replacing the semiconductor material in the gate electrode structures. To this end, an appropriate dielectric material may be provided at least prior to the removal of the semiconductor material in the gate electrode structures, without requiring significant modifications of established replacement gate approaches.

Abstract: An electronic apparatus having a substrate with a bottom gate p-channel type thin film transistor; a resist pattern over the substrate; and a light shielding film operative to block light having a wavelength shorter than 260 nm over at least a channel part of said thin film transistor.

Abstract: The present disclosure is directed to a thin film resistor having a first resistor layer having a first temperature coefficient of resistance and a second resistor layer on the first resistor layer, the second resistor layer having a second temperature coefficient of resistance different from the first temperature coefficient of resistance. The first temperature coefficient of resistance may be positive while the second temperature coefficient of resistance is negative. The first resistor layer may have a thickness in the range of 50 and 150 angstroms and the second resistor layer may have a thickness in the range of 20 and 50 angstroms.

Abstract: There is provided a CMOSFET device with a threshold voltage controlled by means of its gate stack configuration and a method of fabricating the same. The CMOSFET device comprises: a semiconductor substrate; am interface layer grown on the silicon substrate; a first high-k gate dielectric layer deposited on the interface layer; a very thin metal layer deposited on the first high-k gate dielectric layer; a second high-k gate dielectric layer deposited on the very thin metal layer; and a gate electrode layer deposited on the second high-k gate dielectric layer.

Abstract: A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Abstract: An integrated circuit that includes a resistor module with improved linearity is disclosed. The resistor module includes a diffused resistor body of a first conductivity type; a first terminal and a second terminal, each making direct electrical contact with the diffused resistor body; a doped well of a second conductivity type substantially surrounding the diffused resistor body on all but one major surface of the diffused resistor body, the doped well having contact regions; a first amplifier connected to the first terminal and to one contact region of the doped well; and a second amplifier connected to the second terminal and to another contact region of the well, such that the first amplifier and the second amplifier are connected for power supply only to the first terminal and second terminal, respectively. The first and second amplifiers may be unity gain buffer amplifiers or inverting opamps.

Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.

Abstract: Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.

Abstract: A method of manufacture of a package system includes: providing a base package substrate having conductive elements; providing an internal stacking module having a semiconductor die mounted on a package substrate and a first encapsulant surrounding at least portions of the semiconductor die and the package substrate; covering at least portions of the first encapsulant in the internal stacking module with an electromagnetic interference shield, the electromagnetic interference shield shaped to have an outside face; mounting the internal stacking module over the base package substrate with the outside face of the electromagnetic interference shield facing the base package substrate; and encapsulating at least portions of the internal stacking module, the electromagnetic interference shield, and the base package substrate using a second encapsulant.

Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).

Abstract: Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer.

Abstract: A thin film transistor, a method of fabricating the thin film transistor, and an organic light emitting diode (OLED) display device including the thin film transistor, the thin film transistor including: a substrate; a buffer layer formed on the substrate; a first semiconductor layer disposed on the buffer layer; a second semiconductor layer disposed on the first semiconductor layer, which is larger than the first semiconductor layer; a gate electrode insulated from the first semiconductor layer and the second semiconductor layer; a gate insulating layer to insulate the gate electrode from the first semiconductor layer and the second semiconductor layer; source and drain electrodes insulated from the gate electrode and connected to the second semiconductor layer; an insulating layer disposed on the source and drain electrodes, and an organic light emitting diode connected to one of the source and drain electrodes.

Abstract: In an ESD clamp formed in a SOI process, voltage tolerance is increased by introducing multiple blocking junctions between the anode and cathode of the device.

Abstract: A thin film field effect transistor including, on a substrate, at least a gate electrode, a gate insulating layer, an active layer, a source electrode and a drain electrode, wherein an electric resistance layer is provided in electric connection between the active layer and at least one of the source electrode or the drain electrode.

Abstract: An embodiment is a method and apparatus to fabricate a flat panel display. A poly-last structure is formed for a display panel using an amorphous silicon or amorphous silicon compatible process. The poly-last structure has a channel silicon precursor. The display panel is formed from the poly-last structure using a polysilicon specific or polysilicon compatible process.