Abstract: A semiconductor display device which includes the polycrystalline silicon TFTs is constructed by a pixel region and a peripheral circuit and TFT characteristics required for each circuit are different. For example, an LDD structure TFT having a large off-current suppressing effect is suitable for the pixel region. Also, a GOLD structure TFT having a large hot carrier resistance is suitable for the peripheral circuit. When the performance of the semiconductor display device is improved, it is suitable that difference TFT structures are used for each circuit. In the case where the GOLD structure TFT having both Lov regions and Loff regions is formed, ion implantation into the Lov regions is independently performed using a negative resist pattern formed in a self alignment by a rear surface exposure method as a mask, and thus impurity concentrations of the Lov regions and the Loff regions can be independently controlled.

Abstract: To form a driver circuit to be mounted to a liquid crystal display device or the like on a glass substrate, a quartz substrate, etc., and to provide a display device mounting driver circuits formed from different TFTs suited for their respective operational characteristics. A stick driver circuit on the scanning line side and a stick driver circuit on the data line side are different in structure, and have different TFTs in which the thickness of a gate insulating film, the channel length and other parameters are varied depending on required circuit characteristics. In the stick driver on the scanning line side, which is composed of a shift register circuit, a level shifter circuit, and a buffer circuit, the buffer circuit has a TFT with a thick gate insulating film because it is required to have a withstand voltage of 30 V.

Abstract: An electro-optical device having a plurality of pixels including a plurality of EL elements, wherein the electro-optical device provides a gray scale display by controlling a period of time at which the plurality of the EL elements emit light in one frame period; the plurality of the EL elements have a first electrode and a second electrode; the first electrode is held at a constant potential; and a potential of the second electrode changes in such a manner that a polarity of an EL driving voltage, which is a difference between the potentials applied to the first and second electrodes, is inverted for each one frame period.

Abstract: A semiconductor device including a resistor and a method of forming the same. In the semiconductor device, a conductive pattern, which connects source regions, and a resistor are formed of the same material, which can be polysilicon. In the method, the conductive pattern and the resistor are simultaneously formed. Thus, it is possible to obtain a constant sheet resistance without an additional photo mask.

Abstract: A chip resistor comprising a substrate having opposite parallel symmetrical first and second surfaces, a central longitudinal plane of symmetry, separate and spaced first and second resistive layers on the first and second surfaces. The resistive layers are electrically connected in parallel to each other and the first and second surfaces of the substrate are symmetrically located with respect to and equidistant from a central longitudinal plane. Thus, when electrical current passes through the resistive layers, a temperature distribution within the substrate will be substantially symmetrical about the central longitudinal plane of the substrate for eliminating thermal bending thereof. The splitting of the surge current between two resistive layers results in the lower temperature in each resistive layer when compared with the temperature in the single resistive layer of the prior art chip resistor loaded by the same current.

Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A semiconductor device for ESD protection of an input/output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I/O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: The present invention has an object of providing a light emitting device including an OLED formed on a plastic substrate, which can prevent the degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light emitting layer in the OLED (hereinafter, referred to as barrier films) and a film having a smaller stress than that of the barrier films (hereinafter, referred to as a stress relaxing film), the film being interposed between the barrier films, are provided. Owing to a laminate structure of a plurality of barrier films, even if a crack occurs in one of the barrier films, the other barrier film(s) can effectively prevent moisture or oxygen from penetrating into the organic light emitting layer. Moreover, the stress relaxing film, which has a smaller stress than that of the barrier films, is interposed between the barrier films, thereby making it possible to reduce a stress of the entire sealing film.

Abstract: In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are spaced apart in a manner as to avoid significant heat buildup.

Abstract: In an electrode means comprising a first and a second thin-film electrode layers (L1, L2) with electrodes (&egr;) in the form of parallel strip-like electrical conductors in each layer, the electrodes (&egr;) are provided only separated by a thin film (6) of an electrically insulating material with a thickness at most a fraction of the width of the electrodes and at least extending along the side edges thereof and forming an insulating wall (6a) therebetween. The electrode layers (L1, L2) are planarized to obtain an extremely planar surface. In an apparatus comprising one or more electrode means (EM), the electrode layers (L1, L2) of each are mutually oriented with their respective electrodes (1;2) crossing at an angle, preferably orthogonally and with a functional medium (3) provided globally in sandwich therebetween, such that a preferably passive matrix-addressable apparatus is obtained and suited for use as e.g.

Abstract: An NMOS transistor circuit has a surge protection circuit connected in parallel with the NMOS transistor. A resistor is connected between a back gate of the NMOS transistor and ground. As a result, an input impedance higher than the input impedance of the surge protection circuit is applied to a semiconductor terminal at the electrode pad side of the NMOS transistor.

Abstract: The present invention relates to a structure and a fabrication method of a storage capacitor used in the pixel region of a display panel such as LCD or OELD. The present invention simultaneously forms a poly-crystalline silicon TFT and a storage capacitor in the pixel region of a display panel using MILC phenomena. By applying MILC inducing metal along at least two edges of storage capacitor, the time required to crystallize the silicon layer in storage capacitor region may be significantly reduced.

Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.

Abstract: A film thickness of a gate oxide film of a lateral high breakdown voltage MOSFET of a first conduction type is formed with a thickness in which an electric field value to an absolute maximum rated voltage between a source and a drain becomes equal to or less than 4 MV/cm, and a drain diffused layer is formed so that a total amount of impurities therein becomes equal to or more than 2×1012/cm2 to reduce an on-resistance of the lateral high breakdown voltage MOSFET while ensuing a breakdown voltage thereof, and to reduce an area of the lateral high breakdown voltage MOSFET.

Abstract: An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Abstract: A fabricating method of low temperature poly-silicon film is described. An amorphous silicon layer is formed on a substrate first; then, an anneal treatment is performed on the amorphous silicon layer for forming a poly-silicon layer (poly-silicon film) from the amorphous silicon layer. Several mounds are formed on the surface of the poly-silicon layer. A surface treatment step is performed; then, another laser anneal step is conducted on the poly-silicon layer. Since the size of these mounds on the surface of the poly-silicon layer can be reduced, the issue that the mounds are too big and have different sizes in the prior art can be resolved.

Abstract: A silicon controlled rectifier electrostatic discharge protection circuit with external on-chip triggering and compact internal dimensions for fast triggering. The ESD protection circuit includes a silicon controlled rectifier (SCR) having an anode coupled to the protected circuitry and a cathode coupled to ground, where the cathode has at least one high-doped region. At least one trigger-tap is disposed proximate to the at least one high-doped region and an external on-chip triggering device is coupled to the trigger-tap and the protected circuitry.

Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.

Abstract: An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.

Abstract: A pixel structure comprising a thin film transistor, a pixel electrode, a scan line, a data line and an alignment mark. The alignment mark is formed beneath the data line. Misalignment is assessed through the degree of shifting between the alignment mark and the data line relative to each other. In addition, misalignment is also gauged through the degree of shifting between the alignment mark and the channel layer within the thin film transistor relative to each other.

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract: A semiconductor device including a resistive conductive layer and a method of manufacturing the semiconductor device.

Abstract: A resin-sealed semiconductor device is provided which allows unwanted air to be bled out steadily and readily from the space defined between the resistor of a plate-like shape and the insulating substrate in the resin sealing step. The resin-sealed semiconductor device includes a resistor of a plate-like form anchored at both ends to the upper main surface of a substrate thereof. A space is provided between the resistor and the substrate. The primary components including the resistor mounted on the substrate are sealed with a curing resin material. In particular, the resistor has an aperture provided in a portion thereof, which is opposite to the substrate and defines the space with the substrate, for communication between the space and the upper side of the resistor.

Abstract: A structure and method of using microfluidic channels to form an array of semiconductor devices is described. The microfluidic channels have been found to be particularly useful when formed in a self aligned process and used to interconnect a series of thin film transistor (TFT) devices.

Abstract: A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

Abstract: Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

Abstract: A semiconductor device has a semiconductor element formed on a semiconductor substrate and a first insulating film having contact holes. The semiconductor element has a gate electrode, a source region and a drain region. The semiconductor element also has metal wirings each for connecting a respective one of the contact holes to the gate electrode, the source region and the drain region of the semiconductor element. A second insulating film is formed on the first insulating film and the metal wirings. The second insulating film has a chemical-mechanical polished portion defining a flattened upper surface of the second insulating film. Resistors are formed on and are disposed directly in contact with the flattened upper surface of the second insulating film and are connected in series to form a bleeder resistor circuit or a ladder circuit.

Abstract: A thin film transistor having a single LDD structure is provided. The single LDD structure is disposed between source/drain structures, and having a first side adjacent to a first one of the source/drain structures and a second side spaced from a second one of the source/drain structures by essentially a semiconductor material. Another thin film transistor having a first kind of LDD and a second kind of LDD structure is also provided. The second kind of LDD structure is adjacent to the first kind of LDD structure. The process for manufacturing such thin film transistor is also disclosed.

Abstract: A bi-directional silicon controlled rectifier formed in a silicon layer and disposed over shallow trench isolations and therefore electrically isolated from the substrate to be insensitive to substrate noise for electrostatic discharge protection an electrostatic discharge protection device that includes a semiconductor substrate, including a first p-type portion, a first n-type portion contiguous with the first p-type portion, a second p-type portion contiguous with the first p-type portion and the first n-type portion, a second n-type portion, a third p-type portion, a third n-type portion contiguous with the third p-type portion, and a fourth p-type portion contiguous with the third p-type portion and the third n-type portion, wherein at least one of the first p-type portion, second p-type portion, third p-type portion, fourth p-type portion, first n-type portion, second n-type portion, and third n-type portion overlaps the isolation structure.

Abstract: The invention includes semiconductor constructions having a thin film stacked resistor in electrical connection with a source/drain region of a transistor device. The resistor includes first and second crystalline layers which may or may not differ from one another. One of the first and second crystalline layers comprises doped silicon/germanium, and the other comprises doped silicon. The transistor device and resistor can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The invention also includes processes of forming semiconductor constructions, and in particular aspects, includes processes of forming resistor constructions.

Abstract: The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second dielectric layer located over the resistive layer and the first and second contact pads. In an illustrative embodiment, the thin film resistor further includes a first interconnect that contacts the first contact pad and a second interconnect that contacts the second contact pad.

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a one-transistor SOI non-volatile memory cell. In various embodiments, the memory cell includes a substrate, a buried insulator layer formed on the substrate, and a transistor formed on the buried insulator layer. The transistor includes a floating body region that includes a charge trapping material. A memory state of the memory cell is determined by trapped charges or neutralized charges in the charge trapping material. The transistor further includes a first diffusion region and a second diffusion region to provide a channel region in the body region between the first diffusion region and the second diffusion region. The transistor further includes a gate insulator layer formed over the channel region, and a gate formed over the gate insulator layer. Other aspects are provided herein.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.

Abstract: A semiconductor device has a first IGBT (1) for controlling a principal current and a second IGBT (2) for preventing an over-current of the first IGBT (1). A diode portion (11) is disposed between the emitter (5) of the first IGBT (1) and the emitter (6) of the second IGBT (2) so as to be in parallel with a sensing resistor (8). The diode portion (11) is composed of a first diode (9) and a second diode (10), which are connected in reverse series to each other. In order to prevent the over-current of the first IGBT (1) and the destruction of the second IGBT (2), each of the diodes (9, 10) has a breakdown voltage in the reverse voltage direction, which is lower than the endurance voltage between the emitters (5, 6) and is higher than the upper limit of the voltage sensed by the sensing resistor (8).

Abstract: An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P+ diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N+ diffusion) next to the it. The drain and the P+ diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P+ diffusion) is located on either side of each source (N+ diffusion) and together are coupled to a reference potential.

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground.

Abstract: An organic electroluminescent display device includes a first substrate, a second substrate spaced apart and facing the first substrate, a switching thin film transistor disposed on an inner surface of the first substrate, a driving thin film transistor electrically connected to the switching thin film transistor, a connecting electrode electrically connected to the driving thin film transistor, a first electrode disposed on an inner surface of the second substrate, a partition wall disposed on the first electrode and having a transmissive hole corresponding to a pixel region between the first and second substrates, an organic layer disposed within the transmissive hole on the first electrode, and a second electrode disposed on the organic layer, wherein the second electrode is electrically connected to the driving thin film transistor through the connecting electrode.

Abstract: A layer of material is transformed from a first state to a second state by the application of energy from an energy beam. For example, large direction- and location-controlled p-Si grain growth utilizes recrystallization of amorphous silicon from superpositioned laser irradiation. The superpositioned laser irradiation controls cooling and solidification processes that determine the resulting crystal structure. Specifically, a first laser beam of a first pulse duration is used to melt an amorphous silicon (a-Si) film and to create a temperature gradient. After an initial delay, a second laser beam with shorter pulse duration is superpositioned with the first laser beam. When a-Si is irradiated by the second laser beam, the area heated by the first laser beam becomes completely molten. Spontaneous nucleation is initiated in the supercooled liquid-Si when the liquid-Si temperature drops below the nucleation temperature.

Abstract: A method of passivation layer deposition using a cyclical deposition process is described. The cyclical deposition process may comprise alternately adsorbing a silicon-containing precursor and a reactant gas on a substrate structure. Thin film transistors, such as a bottom-gate transistor or a top-gate transistor, including a silicon-containing passivation layer, may be formed using such cyclical deposition techniques.

Abstract: Disclosed herein is a semiconductor device wherein a thyristor protective element and a trigger element are provided in a semiconductor layer formed on a buried insulating layer, and a trigger electrode (gate) of the thyristor protective element and a back gate of the trigger element are provided in the same p well and electrically connected to each other to thereby drive the thyristor protective element based on a substrate current produced by the breakdown of the trigger element.

Abstract: An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.

Abstract: A substrate and a method for fabricating variable quality substrate materials are provided. The method comprises: selecting a first mask having a first mask pattern; projecting a laser beam through the first mask to anneal a first area of semiconductor substrate; creating a first condition in the first area of the semiconductor film; selecting a second mask having a second mask pattern; projecting the laser beam through the second mask to anneal a second area of the semiconductor film; and, creating a second condition in the second area of the semiconductor film, different than the first condition. More specifically, when the substrate material is silicon, the first and second conditions concern the creation of crystalline material with a quantitative measure of lattice mismatch between adjacent crystal domains. For example, the lattice mismatch between adjacent crystal domains can be measured as a number of high-angle grain boundaries per area.

Abstract: A semiconductor device having a display unit, which is small in size, suppresses the defect caused by the mounting of IC chips and the like on the substrate, and operates at a high speed. A semiconductor display unit and other circuit blocks are integrally formed on the substrate having an insulating surface by using a process for fabricating TFTs that realize a high degree of mobility. Concretely, there is employed a process for crystallizing a semiconductor active layer by using a continuously oscillating laser. Further, the process for crystallization relying upon the continuously oscillating laser is selectively effected for only those circuit blocks that must be operated at high speeds, thereby to realize a high production efficiency.

Abstract: An insulation film in a thin film transistor is an insulation film formed by heating a coating film having a hydrogen silsesquioxane compound or a methyl silsesquioxane compound as its principal component. By designing the insulation film so as to have pores mainly of a diameter of 4 nm or less, the dielectric constant of the insulation film can thereby be lowered. As a result, it is possible to improve the operating speed of the thin film transistor. Thus, improvement in the operating speed of a thin film transistor structure is thereby realized.

Abstract: To provide a high precision bleeder resistance circuit having an accurate divided voltage ratio and a small temperature coefficient of a resistance value, and to provide semiconductor devices having high precision and a small temperature coefficient by using the bleeder resistance circuit. For example, semiconductor devices such as a voltage detector and a voltage regulator are provided. Electric potentials of a conductor on thin film resistors and of a conductor under the thin film resistors are made nearly equal to that of each thin film resistor in a bleeder resistance circuit using the thin film resistors. In addition, if polysilicon is used in the thin film resistors, dispersion in the resistance values is suppressed, and temperature dependence of the resistance values is eliminated, by making a film thickness of the polysilicon thin film resistors thin, and making an impurity introduced into the polysilicon thin film resistors p-type.

Abstract: Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve the moisture resistance of the organic resin substrate for the sake of maintaining the reliability of an EL element. Hard carbon films are formed to cover a surface of the organic resin substrate and outer surfaces of a sealing member. Typically, DLC (Diamond like Carbon) films are used as the carbon films. The DLC films have a construction where carbon atoms are bonded into an SP3 bond in terms of a short-distance order, although the films have an amorphous construction from a macroscopic viewpoint. The DLC films contain 95 to 70 atomic % carbon and 5 to 30 atomic % hydrogen, so that the DLC films are very hard and minute and have a superior gas barrier property and insulation performance.