Abstract: The present invention relates to an image sensor in which substrates are stacked, wherein a substrate-stacked image sensor according to the present invention is configured such that a first photodiode is formed on a first substrate, a second photodiode is formed on a second substrate, the two substrates are aligned with and bonded to each other to electrically couple the two photodiodes to each other, thereby forming a complete photodiode within one pixel.

Abstract: Capacitance between a detection capacitor and a reset transistor is the largest among the capacitances between the detection capacitor and transistors placed around the detection capacitor. In order to reduce this capacitance, it is effective to reduce the channel width of the reset transistor. It is possible to reduce the effective channel width by distributing, in the vicinity of the channel of the reset transistor and the boundary line between an active region and an element isolation region, ions which enhance the generation of carriers of an opposite polarity to the channel.

Abstract: A thin-film transistor includes a semiconductor pattern, a first gate electrode, a source electrode, a drain electrode and a second gate electrode. The semiconductor pattern is formed on a substrate. A first conductive layer has a pattern that includes the first gate electrode which is electrically insulated from the semiconductor pattern. A second conductive layer has a pattern that includes a source electrode electrically connected to the semiconductor pattern, a drain electrode spaced apart from the source electrode, and a second gate electrode electrically connected to the first gate electrode. The second gate electrode is electrically insulated from the semiconductor pattern, the source electrode and the drain electrode.

Abstract: An image sensor arranged inside and on top of a semiconductor substrate, having a plurality of pixels, each including: a photosensitive area, a read area, and a storage area extending between the photosensitive area and the read area; at least one first insulated vertical electrode extending in the substrate between the photosensitive area and the storage area; and at least one second insulated vertical electrode extending in the substrate between the storage area and the read area.

Abstract: The present invention is directed to photodiode arrays comprising a dielectric structure containing an array of face conductive areas (pads) and. Each photodiode is fully separated from each other. Every photodiode has a face electrode formed on sensitive side of the semiconductor substrate and an individual back electrode formed on the opposite side. The number of conductive areas on the dielectric structure is equal to number of photodiodes in the array. The photodiodes of the array are installed on the conductive areas so that their back electrodes have electrical contact with the corresponding conductive area. Each conductive area contains at least one individual conductive hole penetrating the dielectric package from the face side to the opposite side of the dielectric structure. The conductive holes going to backside of the dielectric structure are connected with the back conductive areas formed on back side of dielectric package.

Abstract: An apparatus includes a flip-chip semiconductor substrate, a light detection element configured to be formed over the flip-chip semiconductor substrate and to have a laminate structure including a first semiconductor layer of a first-conductive-type, a light-absorption layer formed over the first semiconductor layer, and a second semiconductor layer of a second-conductive-type formed over the light-absorption layer, an inductor configured to be connected to the light detection element over the flip-chip semiconductor substrate, an output electrode for bump connection configured to output a current generated by the light detection element through the inductor, a bias electrode for bump connection configured to apply a bias voltage to the light detection element through a bias electrode, and a line configured to cause a metal line of the inductor and the light detection element to be connected to the output electrode or the bias electrode.

Abstract: The present disclosure relates to photodetectors with high efficiency of light detection, and may be used in a wide field of applications, which employ the detection of very weak and fast optical signals, such as industrial and medical tomography, life science, nuclear, particle, and/or astroparticle physics etc. A highly efficient CMOS-technology compatible Silicon Photoelectric Multiplier may comprise a substrate and a buried layer applied within the substrate. The multiplier may comprise cells with silicon strip-like quenching resistors, made by CMOS-technology, located on top of the substrate and under an insulating layer for respective cells, and separating elements may be disposed between the cells.

Abstract: A device includes a Backside Illumination (BSI) image sensor chip, which includes an image sensor disposed on a front side of a first semiconductor substrate, and a first interconnect structure including a plurality of metal layers on the front side of the first semiconductor substrate. A device chip is bonded to the image sensor chip. The device chip includes an active device on a front side of a second semiconductor substrate, and a second interconnect structure including a plurality of metal layers on the front side of the second semiconductor substrate. A first via penetrates through the BSI image sensor chip to connect to a first metal pad in the second interconnect structure. A second via penetrates through a dielectric layer in the first interconnect structure to connect to a second metal pad in the first interconnect structure, wherein the first via and the second via are electrically connected.

Abstract: In a solid-state imaging device and an imaging device, transistors on a first substrate are configured as N-type transistors. Of transistors on a second substrate, a sampling transistor and an analog memory reset transistor connected to an analog memory are configured as P-type transistors. A difference between the potential of back gates of the sampling transistor and the analog memory reset transistor and a potential at the time of resetting the analog memory is less than a difference between the potential of a back gate of the N-type transistor and the potential at the time of resetting the analog memory.

Abstract: A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

Abstract: A CMOS type semiconductor image sensor module wherein a pixel aperture ratio is improved, chip use efficiency is improved and furthermore, simultaneous shutter operation by all the pixels is made possible, and a method for manufacturing such semiconductor image sensor module are provided. The semiconductor image sensor module is provided by stacking a first semiconductor chip, which has an image sensor wherein a plurality of pixels composed of a photoelectric conversion element and a transistor are arranged, and a second semiconductor chip, which has an A/D converter array. Preferably, the semiconductor image sensor module is provided by stacking a third semiconductor chip having a memory element array. Furthermore, the semiconductor image sensor module is provided by stacking the first semiconductor chip having the image sensor and a fourth semiconductor chip having an analog nonvolatile memory array.

Abstract: According to embodiments of the present invention, a photodetector is provided. The photodetector includes a substrate having a first side and a second side opposite to the first side, the substrate being adapted to receive light incident on the photodetector on the first side of the substrate, a plurality of cells formed in the substrate, and at least one trench defined by a first sidewall and a second sidewall, wherein a spacing between the first sidewall and the second sidewall increases in a direction from the first side of the substrate towards the second side, wherein a respective trench of the at least one trench is arranged in between adjacent cells of the plurality of cells. According to further embodiments of the present invention, a method for forming a photodetector is also provided.

Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.

Abstract: A method of fabricating a photodiode array having different photodiode structures includes providing a semiconductor substrate having first and second diode areas including a bottom substrate portion doped with a first doping type, an intrinsic layer, and a top silicon layer doped with a second doping type. The second diode areas are implanted with the second doping type. A dopant concentration in the surface of the second diode areas is at least three times higher than in the first diode areas. The top silicon layer is thermally oxidized to form a thermal silicon oxide layer to provide a bottom Anti-Reflective Coating (ARC) layer. The second diode areas grow thermal silicon oxide thicker as compared to the first diode areas. A top ARC layer is deposited on the bottom ARC layer. First PDs are provided in the first diode areas and second PDs provided in the second diode areas.

Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

Abstract: An X-ray detection device includes a gate electrode and a lower electrode on a substrate and laterally spaced from each other, a dielectric layer covering the gate electrode and the lower electrode, and a conductive pattern on the dielectric layer at a side of the gate electrode adjacent to the lower electrode and overlapping the lower electrode. The device also includes a source electrode spaced apart from the conductive pattern that is on the dielectric layer at the other side of the gate electrode, and an interlayer insulation layer covering the conductive pattern and the source electrode. A collector electrode, a photoelectric conversion layer, and a bias electrode are sequentially stacked on the interlayer insulation layer.

Abstract: A semiconductor detector device comprises a layer of semiconductor material for generating charge in response to an input event and an array of pixels for collecting charge. Tracks are connected to the pixels to supply signals representing the collected charge to a reader circuit. The pixels are grouped into sets, all the pixels within a set being connected to the same track, the sets of pixels being interwoven so that so that any group of n adjacent pixels capable of collecting charge generated by a single input event is connected to a combination of n tracks that is unique to the group of pixels, where n has a value of one of 2, 3 or 4. This allows detection of position of the area of charge collection on the basis of temporally coincident signals on a combination of at least n tracks.

Abstract: A IDCA system with internal nBn photo-detector comprising: a photo-absorbing layer comprising an n-doped semiconductor exhibiting valence band energy level; a barrier layer, a first side of the barrier layer adjacent a first side of the photo-absorbing layer, the barrier layer exhibiting a valence band energy level substantially equal to the valence band energy level of the doped semiconductor of the photo absorbing layer; and a contact area comprising a doped semiconductor, the contact area being adjacent a second side of the barrier layer opposing the first side, the barrier layer exhibiting a thickness and conductance band gap sufficient to prevent tunneling of majority carriers from the photo-absorbing layer to the contact area, blocking the flow of thermalized majority carriers from the photo-absorbing layer to the contact area. Alternatively, a p-doped semiconductor is utilized, equalizing barrier conductance band energy levels and photo-absorbing layers.

Abstract: A solid-state image sensing device has a unit pixel containing a photoelectric conversion element for detecting a light to generate photoelectrons and pixel drive circuits for driving the unit pixel. The photoelectric conversion element has a photogate structure, and the pixel drive circuits apply a voltage selected from three voltages to the photogate of the photoelectric conversion element to generate or transfer the photoelectrons. The three voltages include at least a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the first voltage and lower than the second voltage.

Abstract: A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. An LDD region 207 provided in an n-channel TFT 302 forming a driving circuit enhances the tolerance for hot carrier injection. LDD regions 217-220 provided in an n-channel TFT (pixel TFT) 304 forming a pixel portion greatly contribute to the decrease in the OFF current value. Here, the LDD region of the n-channel TFT of the driving circuit is formed such that the concentration of the n-type impurity element becomes higher as the distance from an adjoining drain region decreases.

Abstract: The present disclosure relates to a method of forming a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the method comprises forming a plurality of photodetectors within a front-side of a semiconductor substrate. An implant is performed on the back-side of the semiconductor substrate to form an implantation region having a doping concentration that is greater in the center than at the edges of the semiconductor substrate. The back-side of the workpiece is then exposed to an etchant, having an etch rate that is inversely proportional to the doping concentration, which thins the semiconductor substrate to a thickness that allows for light to pass through the back-side of the substrate to the plurality of photodetectors. By implanting the substrate prior to etching, the etching rate is made uniform over the back-side of the substrate improving total thickness variation between the photodetectors and the back-side of the substrate.

Abstract: A semiconductor chip is specified that has a contact layer that is not optimum for many common applications. For example, the contact layer is too thin to tolerate an operating current intended for the semiconductor chip without considerable degradation. Also specified is an optoelectronic component in which the semiconductor chip can be integrated so that the suboptimal quality of the contact layer is compensated for. In the component the semiconductor chip is applied to a carrier body so that the contact layer is arranged on a side of the semiconductor body that is remote from the carrier body. The semiconductor chip and the carrier body are at least partly covered with an electrically isolating layer, and an electrical conductor applied to the isolating layer extends laterally away from the semiconductor body and contacts at least a partial surface of the contact layer. In addition, an advantageous process for producing the component is specified.

Abstract: A method for producing a semiconductor component is disclosed. A carrier substrate includes a mounting region and an opening, which is formed in the mounting region of the carrier substrate. After mounting a semiconductor chip, an electrically insulating layer is applied to the carrier substrate in such a way that the electrically insulating layer completely fills the first opening in the carrier substrate. A second opening is formed in the electrically insulating layer. An electrically conductive layer is then applied to the electrically insulating layer in such a way that the second opening is filled with the electrically conductive layer in the form of a via. A semiconductor component produced in this way is also provided.

Abstract: According to one embodiment, a solid state imaging device includes a sensor substrate curved such that an upper face having a plurality of pixels formed is recessed and an imaging lens provided on the upper face side.

Abstract: A semiconductor memory includes: a plurality of active regions AAi, AAi?1, . . . , AAn, which extend on a memory cell array along the column length; a plurality of non-uniformly arranged word line patterns WL1, WL2, . . . , extending along the row length; a plurality of select gate line patterns SG1, SG2, . . . , arranged parallel to the plurality of word line patterns; borderless contacts formed near the ends of the word line patterns on the memory cell array, in contact with part of an interconnect extended from the end of the memory cell array, but not in contact with interconnects adjacent to that interconnect; and bit line contacts formed within contact forming regions provided by removing part of the plurality of word line patterns and select gate line patterns through double exposure.

Abstract: A photodiode array PDA1 is provided with a substrate S wherein a plurality of photodetecting channels CH have an n-type semiconductor layer 32. The photodiode array PDA1 is provided with a p? type semiconductor layer 33 formed on the n-type semiconductor layer 32, resistors 24 provided for the respective photodetecting channels CH and each having one end portion connected to a signal conducting wire 23, and an n-type separating portion 40 formed between the plurality of photodetecting channels CH. The p? type semiconductor layer 33 forms pn junctions at an interface to the n-type semiconductor layer 32 and has a plurality of multiplication regions AM for avalanche multiplication of carriers generated with incidence of detection target light, corresponding to the respective photodetecting channels. An irregular asperity 10 is formed in a surface of the n-type semiconductor layer 32 and the surface is optically exposed.

Abstract: A semiconductor device contains a photodiode which has a plurality of p-n junctions disposed in a stack. Two contact structures on the semiconductor device are connected across at least one of the junctions to allow electrical connection to an external detection circuit, so that signal current from incident light on the photodiode which generates electron-hole pairs across the connected junction may be sensed by the external detection circuit. At least one of the junctions is electrically shorted at the semiconductor device, so that signal current from the shorted junction may not be sensed by the external detection circuit.

Abstract: A Geiger-mode avalanche photodiode may include an anode, a cathode, an output pad electrically insulated from the anode and the cathode, a semiconductor layer having resistive anode and cathode regions, and a metal structure in the semiconductor layer and capacitively coupled to a region from the resistive anode and resistive cathode regions and connected to the output pad. The output pad is for detecting spikes correlated to avalanche events.

Abstract: A solid-state imaging apparatus, controlling a potential on a semiconductor substrate for an electronic shutter operation, includes: a first semiconductor region of the first conductivity type for forming a photoelectric conversion region; a second semiconductor region of the first conductivity type, formed separately from the photoelectric conversion region, for accumulating carriers; a third semiconductor region of a second conductivity type arranged under the second semiconductor region, for operating as a potential barrier; a fourth semiconductor region of the second conductivity type extending between the first semiconductor region and the semiconductor substrate, and between the third semiconductor region and the semiconductor substrate; and a first voltage supply portion for supplying a voltage to the third semiconductor region; wherein the first voltage supply portion includes a fifth semiconductor region of the second conductivity type arranged in the pixel region, and a first electrode connected to

Abstract: An image sensor pixel includes a photodiode region having a first polarity doping type disposed in a semiconductor layer. A pinning surface layer having a second polarity doping type is disposed over the photodiode region in the semiconductor layer. The second polarity is opposite from the first polarity. A first polarity charge layer is disposed proximate to the pinning surface layer over the photodiode region. An contact etch stop layer is disposed over the photodiode region proximate to the first polarity charge layer. The first polarity charge layer is disposed between the pinning surface layer and the contact etch stop layer such that first polarity charge layer cancels out charge having a second polarity that is induced in the contact etch stop layer. A passivation layer is also disposed over the photodiode region between the pinning surface layer and the contact etch stop layer.

Abstract: It is an object to provide a novel forming agent for a gate insulating film that not only provides high insulating properties for the gate insulating film but also takes account of the electric characteristics of a thin film transistor element. A forming agent for a gate insulating film of a thin film transistor characterized by comprising an oligomer compound or a polymer compound including a structural unit containing a pyrimidinetrione ring having a hydroxyalkyl-containing group as a substituent on a nitrogen atom; a gate insulating film formed by the forming agent; and a thin film transistor.

Abstract: A solid-state image capture device includes photoelectric conversion elements that perform photoelectric conversion on incident light to obtain signal charges, color filter portions provided at light incident sides of the corresponding photoelectric conversion elements, and an organic photoelectric conversion layer provided at light incident sides of the color filter portions. The organic photoelectric conversion layer contains a pigment that is absorptive of near infrared light.

Abstract: A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are electrically connected to each other in a state in which a first connection surface of the first semiconductor substrate and a second connection surface of the second semiconductor substrate face each other. A concave portion is formed in at least one of the first connection surface and the second connection surface. An electrode, which is electrically connected to a portion of wirings included in a wiring layer provided in the first semiconductor substrate or the second semiconductor substrate in which the concave portion is formed and is capable of being electrically connected to an outside, is formed in an inside of the concave portion.

Abstract: A light receiving region includes a plurality of light detecting sections 10. The light detecting sections 10 has a second contact electrode 4A. The second contact electrode 4A is arranged at a position overlapping a first contact electrode 3A, so as to contact the first contact electrode. Further, a resistive layer 4B is continued to the second contact electrode 4A.

Abstract: A solar cell includes; a substrate; a first electrode disposed on the substrate, and including a first groove formed therein, a semiconductor layer disposed on the first electrode, and including a second groove formed therein, and a second electrode disposed on the semiconductor layer and connected to the first electrode via the second groove, wherein a third groove passing through the first electrode, the semiconductor layer, and the second electrode is formed in a first region, a fourth groove passing through only the semiconductor layer and the second electrode is formed in a second region, and the first region and the second region are alternately disposed along a direction of extension of the third groove.

Abstract: An image sensor is disclosed that includes a solid state semiconductor imager having a metallized catch pad, a collimator having a metallized layer that faces a sensor anode, the metallized layer joined with the metallized catch pad to form a metal bond between the solid state semiconductor imager and the collimator. Methods of making the joined solid state semiconductor imager and collimator assembly are also disclosed.

Abstract: Disclosed herein is a method for producing a solid-state imaging element which has pixels, each including a sensor section that performs photoelectric conversion and a charge transfer section that transfers charges generated by the sensor section. The method includes: forming an impurity region of the first conduction type and a second impurity region of the second conduction type on the impurity region of the first conduction type by ion implantation by using the same mask; forming on the surface of the semiconductor substrate a transfer gate constituting the charge transfer section which extends over the second impurity region of the second conduction type; forming a charge accumulating region of the first conduction type constituting the sensor section by ion implantation; and forming a first impurity region of the second conduction type, which has a higher impurity concentration than the second impurity region of the second conduction type, by ion implantation.

Abstract: According to one embodiment, a flat panel display includes a first mounting portion including a first input pad and a first output pad, a second mounting portion including a second input pad and a second output pad, a first common terminal and a second common terminal, which have a common potential, and a guard ring wiring which is formed in a manner to extend from the first common terminal, to pass between the first input pad and the first output pad of the first mounting portion, to pass between the second input pad and the second output pad of the second mounting portion, and to reach the second common terminal, the guard ring wiring including a first resistor element of a first resistance value and a second resistor element of a second resistance value which is higher than the first resistance value.

Abstract: A monolithically integrated sensor is disclosed in the form of light detector(s), visible light emitter(s) and associated control circuit(s) monolithically integrated on a single silicon microchip. The detector structures consist of p-i-n photodiode structures, both diffused into and deposited on the surface of the silicon substrate. The emitter structures consist of III-V compound semiconductor hetero-epitaxial layers deposited on the surface of the silicon substrate. The control circuits are fabricated using traditional CMOS high volume manufacturing techniques. The sensor assembly is designed to be processed in a traditional CMOS wafer fab. The sensor assembly is further designed to be packaged at the wafer level.

Abstract: On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other. The high-concentration n-type region is formed by diffusing an n-type impurity from the front side of the substrate so as to surround the p-type region as seen from the front side. The p-type region is formed by diffusing a p-type impurity from the front side of the substrate so as to surround the p-type region and high-concentration n-type region as seen from the front side. Formed on the front side of the n-type semiconductor substrate are an electrode electrically connected to the p-type region and an electrode electrically connected to the high-concentration n-type region and the p-type region.

Abstract: An imaging system may include an image sensor package with an image sensor wafer mounted on a carrier wafer, which may be a silicon substrate. A capacitor may be formed in the carrier wafer. Trenches may be etched in a serpentine pattern in the silicon substrate. Conductive plates of the capacitor may be formed at least partially in the trenches. An insulator material may be formed between the capacitor and the silicon substrate. A dielectric layer may be formed between the conductive plates of the capacitor. The image sensor package may be mounted on a printed circuit board via a ball grid array. Conductive vias may electrically couple the capacitor and the image sensor wafer to the printed circuit board.

Abstract: On the front side of an n-type semiconductor substrate, p-type regions are two-dimensionally arranged in an array. A high-concentration n-type region and a p-type region are disposed between the p-type regions adjacent each other. The high-concentration n-type region is formed by diffusing an n-type impurity from the front side of the substrate so as to surround the p-type region as seen from the front side. The p-type region is formed by diffusing a p-type impurity from the front side of the substrate so as to surround the p-type region and high-concentration n-type region as seen from the front side. Formed on the front side of the n-type semiconductor substrate are an electrode electrically connected to the p-type region and an electrode electrically connected to the high-concentration n-type region and the p-type region.

Abstract: An article of manufacture and a method of defining a photodetector element are provided. The article of manufacture includes a photodector element comprising a junction formed by a first III-V semiconductor layer having a first charge type and a second III-V semiconductor layer comprising a second dopant having a second charge type. The second III-V semiconductor layer is disposed between the first III-V semiconductor layer and a wafer. Patterned dopant regions having a third charge type, the third charge type being the same as the first charge type, are disposed in the first III-V semiconductor layer.

Abstract: A hybrid nanostructure array having a substrate and two types of nanostructures, including a set of first nanostructures extending from the substrate and a set of second nanostructures interspersed among the first nanostructures. The first and second nanostructures comprise structures having nanoscale proportions in two dimensions and being elongate in the third dimension. For example, the nanostructures can be nanotubes, nanowires, nanorods, nanocolumns, and/or nanofibers. Also disclosed is a hybrid nanoparticle array using two different types of nanoparticles that have all three dimensions in the nanoscale. The two types of nanostructures or nanoparticles can vary in composition, shape, or size.

Abstract: An imager may include an imaging die that is stacked with an image processing die. The imaging die may generate output signals from received light. The image processing die may process the output signals. Through-silicon vias of the imaging die or solder balls may electrically couple the imaging die to the image processing die and convey the output signals to the image processing die. The imaging die may include a pixel array that generates pixel signals from the received light. The image processing die may generate control signals that control the imaging die and are conveyed to the imaging die over the through-silicon vias or solder balls.

Abstract: A method of fabricating an imaging array includes providing a single crystal silicon substrate and bonding the single crystal silicon substrate to an insulating substrate. One or more portions of an exposed surface of the single-crystal silicon substrate are removed to form a pattern of first areas having a first height measured from the insulating substrate and second areas having a second height measured from the insulating substrate. Photosensitive elements are formed on the first areas and readout elements are formed on the second areas. The single-crystal silicon substrate is treated by hydrogen implantation to form an internal separation boundary and a portion of the single-crystal silicon substrate is removed at the internal separation boundary to form the exposed surface.

Abstract: This invention comprises photodiodes, optionally organized in the form of an array, including p+ deep diffused regions or p+ and n+ deep diffused regions. More specifically, the invention permits one to fabricate thin 4 inch and 6 inch wafer using the physical support provided by a n+ deep diffused layer and/or p+ deep diffused layer. Consequently, the present invention delivers high device performances, such as low crosstalk, low radiation damage, high speed, low leakage dark current, and high speed, using a thin active layer.

Abstract: An organic photoelectric device includes a first electrode, a metal nanolayer contacting one side of the first electrode, an active layer on one side of the metal nanolayer, and a second electrode on one side of the active layer. An image sensor includes the organic photoelectric device.

Abstract: An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.

Abstract: The present invention generally relates to an offset electrode TFT and a method of its manufacture. The offset electrode TFT is a TFT in which one electrode, either the source or the drain, surrounds the other electrode. The gate electrode continues to be below both the source and the drain electrodes. By redesigning the TFT, less voltage is necessary to transfer the voltage from the source to the drain electrode as compared to traditional bottom gate TFTs or top gate TFTs. The offset electrode TFT structure is applicable not only to silicon based TFTs, but also to transparent TFTs that include metal oxides such as zinc oxide or IGZO and metal oxynitrides such as ZnON.