Abstract: An optoelectronic shutter, a method of operating the same, and an optical apparatus including the optoelectronic shutter are provided. The optoelectronic shutter includes a phototransistor which generates an output signal from incident input light and a light emitting diode serially connected to the phototransistor. The light emitting diode outputs output light according to the output signal, and the output signal is gain-modulated according to a modulation of a current gain of the phototransistor.

Abstract: An apparatus includes a semiconductor layer having an array of pixels arranged therein. A passivation layer is disposed proximate to the semiconductor layer over the array of pixels. A segmented etch stop layer including a plurality of etch stop layer segments is disposed proximate to the passivation layer over the array of pixels. Boundaries between each one of the plurality of etch stop layer segments are aligned with boundaries between pixels in the array of pixels.

Abstract: An image sensor pixel that includes a photoelectric conversion unit supported by a substrate and an insulator adjacent to the substrate. The pixel includes a cascaded light guide located within an opening of the insulator. The cascaded light guide may include a color filter having an air gap between adjacent color filters that is sealed from above by a transparent sealing film having a concave surface over the air gap to diverge light crossing into the air gap from the concave surface into adjacent color filters. A portion of a support wall between a pair of color filters may have a larger width above than below to form a necking to hold down the color filters for better retention.

Abstract: A photodetector having a ridge-in-slit geometry is provided, where a semiconductor ridge is laterally sandwiched in a metallic slit. This assembly is disposed on a layer of semiconducting material, which in turn is disposed on an insulating substrate. These structures can provide efficient resonant detectors having the wavelength of peak response set by the ridge width. Thus a lateral feature defines the wavelength of peak responsivity, as opposed to a vertical feature.

Abstract: An embodiment of an array of Geiger-mode avalanche photodiodes, wherein each photodiode is formed by a body of semiconductor material, having a first conductivity type, housing a first cathode region, of the second conductivity type, and facing a surface of the body, an anode region, having the first conductivity type and a higher doping level than the body, extending inside the body, and facing the surface laterally to the first cathode region and at a distance therefrom, and an insulation region extending through the body and insulating an active area from the rest of the body, the active area housing the first cathode region and the anode region. The insulation region is formed by a mirror region of metal material, a channel-stopper region having the second conductivity type, surrounding the mirror region, and a coating region, of dielectric material, arranged between the mirror region and the channel-stopper region.

Abstract: Embodiments relate to photo cell devices. In an embodiment, a photo cell device includes an array of transmission layers having different optical thicknesses and with photo diodes underneath. The transmission layers can include two different materials, such as a nitride and an oxide, that cover each diode with a different proportional area density in a damascene-like manner. Embodiments provide advantages over conventional devices, including that they can be integrated into a standard CMOS process and therefore simpler and less expensive to produce.

Abstract: A solid state imaging device 1 is provided with a photoelectric conversion portion 2 having photosensitive regions 13, and a potential gradient forming portion 3 arranged opposite to the photosensitive regions 13. A planar shape of each photosensitive region 13 is a substantially rectangular shape composed of two long sides and two short sides. The photosensitive regions 13 are juxtaposed in a first direction intersecting with the long sides. The potential gradient forming portion 3 has a first potential gradient forming region to form a potential gradient becoming lower along a second direction from one of the short sides to the other of the short sides, and a second potential gradient forming region to form a potential gradient becoming higher along the second direction. The second potential gradient forming region is arranged next to the first potential gradient forming region in the second direction.

Abstract: A chip device with a number of individually powered parts, such as photoreceptors. A mesh is provided to provide power to the individual photoreceptors. The mesh may be provided for ground and power and/or both. The mesh may be on different layers, so that one portion of the mesh is exactly over the other portion of the mesh. The mesh takes up a portion of real estate on the chip in between the individual photoreceptors, in locations where image sensing parts cannot be located. In an embodiment, the mesh can be intentionally broken at various locations to optimize the path length.

Abstract: An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.

Abstract: In a photodetector 1, a low-resistance Si substrate 3, an insulating layer 4, a high-resistance Si substrate 5, and an Si photodiode 20 construct a hermetically sealed package for an InGaAs photodiode 30 placed within a recess 6, while an electric passage part 8 of the low-resistance Si substrate 3 and a wiring film 15 achieve electric wiring for the Si photodiode 20 and InGaAs photodiode 30. While a p-type region 22 of the Si photodiode 20 is disposed in a part on the rear face 21b side of an Si substrate 21, a p-type region 32 of the InGaAs photodiode 30 is disposed in a part on the front face 31a side of an InGaAs substrate 31.

Abstract: A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.

Abstract: A photo diode array includes: a substrate having a major face and a back face; photo diodes separated from each other and arrayed in parallel on the major face of the substrate and being linear in a plan view facing the major face of the substrate; a buried layer between the photo diodes and including a separating channel having a V-shape cross section; and a first metal mirror on an inclined face of the separating channel, reflecting incident light entering from the back face of the substrate, and leading the incident light to light-absorbing layers of the photo diodes. Band gap energy of the buried layer is wider than band gap energies of the light-absorbing layers.

Abstract: Embodiments may provide a light source with a controlled brightness variation. A first device is provided that includes a substrate and a plurality of OLEDs disposed on the substrate. Each of the OLEDs includes a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. The plurality of OLEDs comprise a first group and a second group where a first current density is supplied to the first group of the plurality of OLEDs and a second current density that is different from the first current density is supplied to the second group of the plurality of OLEDs. Each of the plurality of OLEDs is commonly addressable and at least one of the OLEDs in the first group of OLEDs has substantially the same device structure as at least one of the OLEDs in the second group of OLEDs.

Abstract: In order to collect a plurality of semiconductor elements easily from a semiconductor module where a plurality of rod-like semiconductor elements for power generation or light emission are built in and to reuse or repair them, two split modules 61 are arranged in series in a containing case 62 in a semiconductor module 60. In each split module 61, power generating semiconductor elements 1 arranged in a matrix of a plurality of rows and columns, and a conductive connection mechanism for connecting the plurality of semiconductor elements 1 in each row in series and the plurality of semiconductor elements 1 in each column in parallel are molded with transparent synthetic resin, and a connection conductor 67 is allowed to project at the end. A conductive waved spring 70 and an external terminal 76 are provided on the end side of the containing case 62, and series connection of the two split modules 61 is ensured by mechanical pressing force of the conductive waved spring 70.

Abstract: A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handier with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces.

Abstract: Techniques for providing a pixel cell which exhibits improved doping in a semiconductor substrate. In an embodiment, a first doping is performed through a backside of the semiconductor substrate. After the first doping, the semiconductor substrate is thinned to expose a front side which is opposite of the backside. In another embodiment, a second doping is performed through the exposed front side of the thinned semiconductor substrate to form at least part of a pixel cell structure.

Abstract: A detecting element has an absorbing section where a temperature rises according to an amount of electromagnetic waves which are absorbed and a detecting section where characteristics change according to an amount of heat which is transmitted from the absorbing section. A method for manufacturing the detecting element includes: forming the detecting section on a substrate; forming a protective film which covers the detecting section; forming a hollow space portion in a region which overlaps with the detecting section of the substrate in a planar view after the forming of the protective film; and forming the absorbing section by applying a liquid body, which contains a material constituting the absorbing section, in a region on the protective film on an opposite side from the detection section, which overlaps with the detecting section in a planar view, and solidifying the liquid body after the forming of the hollow space portion.

Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.

Abstract: A method of fabricating epitaxial structures including applying an etch stop to one side of a substrate and then growing at least one epitaxial layer on a first side of said substrate, flipping the substrate, growing a second etch stop and at least one epitaxial layer on a second side of the substrate, applying a carrier medium to the ultimate epitaxial layer on each side, dividing the substrate into two parts generally along an epitaxial plane to create separate epitaxial structures, removing any residual substrate and removing the etch stop.

Abstract: There is provided a solid-state imaging device including a wafer in which a guard ring with conductivity in an insulation film layered on a first conductivity type substrate is formed between an edge portion of at least a first chip, out of the first chip and a second chip of a layered chip, and a scribe line region, at least two second conductivity type layers are formed at an interval within a region corresponding to the guard ring, in the first conductivity type substrate, and the guard ring includes a first guard ring part connected to one of the second conductivity type layers on a chip edge portion side, and a second guard ring part connected to another one of the second conductivity type layers on a scribe line side.

Abstract: An image-sensing module includes a substrate unit, a light-transmitting unit, an image-sensing unit and a lens unit. The substrate unit includes at least one flexible substrate having at least one through opening. The light-transmitting unit includes at least one light-transmitting element disposed on the top surface of the flexible substrate and corresponding to the through opening. The image-sensing unit includes at least one image-sensing element disposed on the bottom surface of the light-transmitting element and embedded in the through opening, and the image-sensing element is electrically connected to the flexible substrate. The lens unit includes an opaque frame disposed on the top surface of the flexible substrate to surround the light-transmitting element and a lens positioned on the opaque frame to correspond to the light-transmitting element.

Abstract: The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region.

Abstract: Certain embodiments provide a method for producing a solid-state imaging device including the steps of forming an interconnection layer, forming a passivation film, forming a resist layer, forming a plurality of protruding portions and an opening, and forming an electrode pad. In the step of forming the interconnection layer, the interconnection layer is formed on the surface of the semiconductor substrate having a photodiode. In the step of forming the resist layer, the resist layer is formed on the passivation film such that the resist layer has a plurality of first openings above the photodiode and has a second opening above the interconnection of the interconnection layer. In the step of forming the plurality of protruding portions and the opening, the plurality of protruding portions and the opening are formed by etching the passivation film via the resist layer.

Abstract: An apparatus for reducing photodiode thermal gain coefficient includes a bulk semiconductor material having a light-illumination side. The bulk semiconductor material includes a minority charge carrier diffusion length property configured to substantially match a predetermined hole diffusion length value and a thickness configured to substantially match a predetermined photodiode layer thickness. The apparatus also includes a dead layer coupled to the light-illumination side of the bulk semiconductor material, the dead layer having a thickness configured to substantially match a predetermined thickness value and wherein an absolute value of a thermal coefficient of gain due to the minority carrier diffusion length property of the bulk semiconductor material is configured to substantially match an absolute value of a thermal coefficient of gain due to the thickness of the dead layer.

Abstract: To provide a semiconductor device in which a defect or fault is not generated and a manufacturing method thereof even if a ZnO semiconductor film is used and a ZnO film to which an n-type or p-type impurity is added is used for a source electrode and a drain electrode. The semiconductor device includes a gate insulating film formed by using a silicon oxide film or a silicon oxynitride film over a gate electrode, an Al film or an Al alloy film over the gate insulating film, a ZnO film to which an n-type or p-type impurity is added over the Al film or the Al alloy film, and a ZnO semiconductor film over the ZnO film to which an n-type or p-type impurity is added and the gate insulating film.

Abstract: A method for manufacturing a backside-illuminated image sensor may include forming an insulating layer having a predetermined depth in an inactive region of a front side of a semiconductor substrate and forming a photodetector in an active region of a front side of the semiconductor substrate having the insulating layer. Further, the method may include stacking a support substrate on and/or over the front side of the semiconductor substrate having the photodetector. Furthermore, the method may include performing back grinding on the rear side of the semiconductor substrate by using the insulating layer as the stop point.

Abstract: A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

Abstract: A signal charge collecting region is disposed inside a charge generating region so as to be surrounded by the charge generating region, and collects signal charges from the charge generating region. An unnecessary charge collecting region is disposed outside the charge generating region so as to surround the charge generating region, and collects unnecessary charges from the charge generating region. A transfer electrode is disposed between the signal charge collecting region and the charge generating region, and causes the signal charges from the charge generating region to flow into the signal charge collecting region in response to an input signal. An unnecessary charge collecting gate electrode is disposed between the unnecessary charge collecting region and the charge generating region, and causes the unnecessary charges from the charge generating region to flow into the unnecessary charge collecting region in response to an input signal.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes an imaging region having a plurality of pixels arranged in a two-dimensional array, in which the imaging region includes an effective pixel and a black reference pixel; and a shape of a floating diffusion portion in the effective pixel is different from that of a floating diffusion portion in the black reference pixel.

Abstract: A CMOS (Complementary Metal Oxide Semiconductor) pixel for sensing at least one selected from a biological, chemical, ionic, electrical, mechanical and magnetic stimulus. The CMOS pixel includes a substrate including a backside, a source coupled with the substrate to generate a background current, and a detection element electrically coupled to measure the background current. The stimulus, which is to be provided to the backside, affects a measurable change in the background current.

Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.

Abstract: A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area.

Abstract: The present disclosure relates to a method of forming a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the method comprises forming a plurality of photodetectors within a front-side of a semiconductor substrate. An implant is performed on the back-side of the semiconductor substrate to form an implantation region having a doping concentration that is greater in the center than at the edges of the semiconductor substrate. The back-side of the workpiece is then exposed to an etchant, having an etch rate that is inversely proportional to the doping concentration, which thins the semiconductor substrate to a thickness that allows for light to pass through the back-side of the substrate to the plurality of photodetectors. By implanting the substrate prior to etching, the etching rate is made uniform over the back- side of the substrate improving total thickness variation between the photodetectors and the back-side of the substrate.

Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Abstract: Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.

Abstract: A semiconductor apparatus including a substrate, a pixel array on the substrate, first and second conductive pads between which the substrate locates is provided. The apparatus also comprises an insulating layer arranged between the substrate and the first conductive pad; a third conductive pad arranged between the substrate and the insulating layer; a first conductive member which passes through the insulating layer and connects the first and third conductive pads to each other; and a second conductive member which passes through the substrate and connects the second and third conductive pads to each other. The pixel array further comprises a conductive line connected to circuit elements included in pixels aligned in a row or column direction. The first conductive pad is connected to the conductive line in an interval between the pixels.

Abstract: According to an aspect of the invention, a solid-state image sensor having a plurality of pixels includes a plurality of lower electrode, a photoelectric conversion layer, an upper electrode, a wiring portion and a plurality of connection portions. The plurality of lower electrodes respectively corresponds to the plurality of pixels. The photoelectric conversion layer is stacked on the lower electrodes. The upper electrode is stacked on the photoelectric conversion layer. The wiring portion supplies, to the upper electrode, a voltage to generate an electric field between the upper electrode and the lower electrode. The plurality of connection portions connects the wiring portion and the upper electrode. The plurality of connection portions are disposed in a circumference region which is a region other than a sensor region in which a plurality of photoelectric conversion elements are arranged. The plurality of connection portions is disposed in a symmetrical arrangement.

Abstract: A method for forming an image sensing device is disclosed. An epitaxy layer having the first conductivity type is formed on a substrate, wherein the epitaxy layer comprises a first pixel area corresponding to a first incident light, a second pixel area corresponding to a second incident light, and a third pixel area corresponding to a third incident light. A first deep well is formed in a lower portion of the epitaxy layer for reducing pixel-to-pixel talk of the image sensing device. A second deep well is formed in a lower portion of the epitaxy layer.

Abstract: There is provided a solid-state imaging device including a pixel array portion in which multiple unit pixels are arranged on a semiconductor substrate, the multiple unit pixels each including a photoelectric conversion portion generating and accumulating a light charge based on a quantity of received light and a charge accumulation portion accumulating the light charge, wherein at least part of an electrode closer to an incidence side on which light enters the unit pixel of the charge accumulation portion, is formed with a metal film functioning as a light blocking film.

Abstract: An optoelectronic module includes a layer structure having a plurality of semiconductor layers including a substrate layer, a first layer arrangement and a second layer arrangement, wherein 1) the first layer arrangement has a light-emitting layer arranged on the substrate layer, 2) the second layer arrangement contains at least one circuit that controls an operating state of the light-emitting layer, and 3) the second layer arrangement is arranged on the substrate layer and/or surrounded by the substrate layer.

Abstract: A manufacturing method for a solid-state image sensor, the method comprises the steps of: forming a charge storage region in a photoelectric converting unit by implanting a semiconductor substrate with ions of an impurity of a first conductivity type, using a first mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); forming a surface region of the charge storage region by implanting the semiconductor substrate with ions of an impurity of a second conductivity type, using a second a mask; heating the semiconductor substrate at a temperature of no less than 800° C. and no more than 1200° C. through RTA (Rapid Thermal Annealing); and forming an antireflection film that covers the photoelectric converting unit at a temperature of less than 800° C., after the step of forming the surface region, in this order.

Abstract: Disclosed herein is a solid-state imaging element including: a semiconductor layer; a plurality of photoelectric conversion sections arranged within the semiconductor layer; and a pixel separating section disposed in a shape of a same width from a light receiving surface of the semiconductor layer to an opposite surface of the semiconductor layer from the light receiving surface in a position of separating the photoelectric conversion sections from each other for each pixel, the pixel separating section being formed by a material including an impurity.

Abstract: A semiconductor apparatus and a method of fabricating the same are provided. The semiconductor apparatus includes a body part having a first surface and a second surface facing each other, a first trench formed into the first surface of the body part, a second trench formed into the second surface of the body part, an opening connecting the first trench and the second trench to each other, a first adhesion enhancer, such as a rough surface, formed on a bottom surface of the first trench, and a second adhesion enhancer, such as a rough surface, formed on the second surface of the body part.

Abstract: A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.

Abstract: An image sensor array includes a substrate layer, a metal layer, an epitaxial layer, a plurality of imaging pixels, and a contact dummy pixel. The metal layer is disposed above the substrate layer. The epitaxial layer is disposed between the substrate layer and the metal layer. The imaging pixels are disposed within the epitaxial layer and each include a photosensitive element for collecting an image signal. The contact dummy pixel is dispose within the epitaxial layer and includes an electrical conducting path through the epitaxial layer. The electrical conducting path couples to the metal layer above the epitaxial layer.

Abstract: An interface circuit for a sensor array is provided. The interface circuit may be made up of an integrated circuit package that provides a first region and a second region. The first region may be spaced apart and opposite to the second region of the package. The first region of the package may provide a plurality of interfaces for interconnecting to an integrated circuit in the package a plurality of signals from the sensor array and having a first electrical characteristic, such as analog and test signals. The second region of the package may provide a plurality of interfaces for interconnecting to the integrated circuit a plurality of signals having at least one electrical characteristic different than the first characteristic, such as power and operational digital signals.

Abstract: A solid-state imaging device is a solid-state imaging device in which a first substrate formed on a first semiconductor wafer and a second substrate formed on a second semiconductor wafer are bonded via connect that electrically connects the substrates, wherein the first substrate includes photoelectric conversion units, the second substrate includes an output circuit that acquires a signal generated by the photoelectric conversion unit via the connector and outputs the signal, and dummy connectors that support the first and second bonded substrates are further arranged in a substrate region in which the connectors are not arranged in a substrate region of at least one of the first substrate and the second substrate.

Abstract: A cell for a silicon-based photoelectric multiplier may comprise a first layer of a first conductivity type and a second layer of a second conductivity type formed on the first layer. The first layer and the second layer may form a first p-n junction. The cell may be processed by an ion implantation act wherein parameters of the ion implantation are selected such that due to an implantation-induced damage of the crystal lattice, an absorption length of infrared light of a wavelength in a range of ?800 nm to 1000 nm is decreased.

Abstract: An image sensor includes a substrate having opposite first and second sides, a multilayer structure on the first side of the substrate, and a photo-sensitive element on the second side of the substrate. The photo-sensitive element is configured to receive light that is incident upon the first side and transmitted through the multilayer structure and the substrate. The multilayer structure includes first and second light transmitting layers. The first light transmitting layer is sandwiched between the substrate and the second light transmitting layer. The first light transmitting layer has a refractive index that is from 60% to 90% of a refractive index of the substrate. The second light transmitting layer has a refractive index that is lower than the refractive index of the first light transmitting layer and is from 40% to 70% of the refractive index of the substrate.

Abstract: A composite focal plane assembly with an expandable architecture has a multi-layer, double-sided aluminum nitride (AlN) substrate and vertical architecture to achieve the dual function of focal plane and electronics backplane. Imaging dice and other electrical components are mounted and wire bonded to one surface and then direct backplane connectivity is provided on the opposing surface through a matrix of electrical contacts. In one embodiment, a flexible connector is sandwiched between the AlN focal plane and a FR-4 backplane is used to compensate for differences in coefficient of thermal expansion (CTE) between the AlN and commercially available high density circuit card connectors that are commonly manufactured from materials with CTE properties more closely approximating FR-4. In an alternate embodiment, the FR-4 and flexible connectors are eliminated by using high density circuit card connectors that are fabricated out of materials more closely matching the CTE of AlN.