Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: The present invention provides a semiconductor device which is excellent in voltage sense characteristic and simple in manufacturing process. P diffusion regions 12 and 13 are selectively formed on a first major surface of an N.sup.- substrate 11, an electrode 31 is formed on the P diffusion region, a sense electrode 32 is formed on the P diffusion region 13, and an electrode 33 is formed on a second major surface of the N.sup.- substrate. Then, the electrode 31 is set at 0 V, constant current is led to the sense electrode 32, and the electrode 33 is positively biased. Thus, the voltage applied to the electrode 33 is sensed from a potential obtained at the sense electrode 32. A distance between the P diffusion regions 12 and 13 which determines a voltage sense characteristic can be accurately controlled, and a good voltage sense characteristic can be obtained. Moreover, a manufacturing process is relatively simple.

Abstract: Disclosed is a method of manufacturing semiconductor devices in which a desired pattern having an area size larger than the field size that can be obtained in one exposure process step of an exposure device is formed. The manufacturing method includes the steps of dividing the desired pattern into a plurality of portions, and conducting exposure on the dividing patterns in a joined fashion.

Abstract: The transistor comprises a buried base P region, a buried emitter N+ region with elongate portions (fingers), deep contact P+ base regions, emitter N+ interconnection regions serving balancing resistor functions, and base, emitter, and collector surface contact electrodes. To provide a higher current gain and a larger safe operation area, with each emitter "finger" there are associated a screening P region interposed between the "finger" and a part of the respective N+ interconnection region, and a contact N+ region which extends to the "finger" and is surface connected to the screening P region by a dedicated electrode.

Abstract: The electronic component comprises, topologically integrated within the same semiconductor structure (1), a first semiconductor area (12, 13, 3, 4, 20) capable of forming an insulated-gate field-effect transistor, and a second semiconductor area (12, 20, 18, 19, 11) capable of forming a lateral bipolar transistor, the two areas having a common semiconductor layer (20) in which the channel of the field-effect transistor is capable of being formed and/or the base current of the bipolar transistor is capable of flowing, the two areas being capable together of forming a structure capable of negative dynamic resistance.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.

Abstract: A structure of an electronic device having a predetermined unidirectional conduction threshold is formed on a chip of an N-type semiconductor material and includes a plurality of isolated N-type regions. Each isolated N-type region is bounded laterally by an isolating region and at the bottom by buried P-type and N-type regions which form in combination a junction with a predetermined reverse conduction threshold and means of connecting the junctions of the various isolated regions serially together. The buried N-type region of the first junction in the series is connected to a common electrode, which also is one terminal of the device, over an internal path of the N-type material of the chip, and the buried P-type region of the last junction in the series contains an additional buried N-type region which is connected electrically to a second terminal of the device.

Abstract: A power transistor device is provided which has a function of clamping the collector voltage to a stable level for a wide range of temperature variations. In the power transistor device, a plurality of pn junctions are formed to fabricate Zener diodes in the polycrystalline silicon film in the form of rings. The ring configuration of the Zener diodes eliminates an end at the pn junction and prevents the junction surface from being exposed, making it possible to use as a stable Zener voltage the dielectric strength characteristic of the pn junction having a very small temperature coefficient.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: A spiral resistor being of a type formed on a semiconductor substrate to withstand high voltages, comprises at least one thin field-plate layer covering said substrate between adjacent turns of the resistor. This prevents the well-known phenomenon of the "phantom gate" from occurring which would result in the characteristics of spiral resistors deteriorating over time.

Abstract: An ESD protection circuit which provides protection for CMOS devices against ESD potentials of up to about 10 kV is provided. The ESD protection circuit is able to provide protection against both positive-going and negative-going high energy electrical transients, and is able to maintain a high impedance state when driven to a voltage beyond the supply rails of CMOS integrated circuit, but less than tile breakdown voltage of the ESD protection circuit. The ESD protection circuit routes currents associated with ESD potentials to a predetermined arbitrary point which may be selected during the fabrication process to meet the needs of a particular application. The structure of the ESD protection circuit permits the holding current to be adjusted to accommodate the current capacity of various external circuits.

Abstract: A bipolar integrated circuit with N-type wells (2) formed in a P-type substrate (1) includes in first wells, first transistors (EBC), the well of which constitutes the collector. P-type base region (7a) is formed in the first well with an N+ emitter region (8) formed in the base region. In at least a second well forming a collector, a composite second transistor (E'B'C') is constituted by an elemental third transistor (E.sub.1 B.sub.1 C') comprising regions of the same doping level as the first transistor and an elemental fourth transistor (E.sub.2 B.sub.2 C') having a base region (11) with a high doping level with respect to that of the bases of the first transistor. Emitter regions (8b, 12) of the elemental transistors are of the same doping level as that of the first transistors. The emitters and bases of the third and fourth elementary transistors are interconnected and constitute the emitter and the base of the composite second transistor.

Abstract: Compatibility of high sensitivity with low remaining images, and low crosstalk can be achieved by a laminated solid-state image pickup device, which includes accumulating portions for accumulating electric signals, reading units for reading the electric signals, connecting members formed in contact with the accumulating portions, and a photoconductive film, and by a method for manufacturing the device. The photoconductive film is made of a non-crystalline semiconductor, and is configured by laminating a carrier multiplication layer, a light absorbing layer, a charge injection inhibiting layer of a second conduction type. Each of the connecting members is made of a semiconductor layer of a first conduction type, intrinsic or having a low impurity density, surrounded by a semiconductor layer of the second conduction type or a conductive material.

Abstract: The invention relates to a monolithically integrated semiconductor arrangement, where from the first main surface a first zone (p) and a second zone (n.sup.+) are diffused into a substrate (2), which is weakly doped (substrate region n.sup.-) under a first main surface (3) and is more strongly doped (substrate region n.sup.+) under a second main surface (4). An insulating passivation layer is attached to the first main surface (3), on top of which a metallic cover electrode (D) is located, which covers adjacent substrate regions (n.sup.-) and the edge areas of the first zone (p) and the second zone (n.sup.+). In accordance with the invention, at least one additional zone (.nu.) of the same type of conductivity as the associated zone (n.sup.+), but with weaker doping, is diffused in for increasing the break-through voltage, and is connected to the zone (n.sup.+), does not contact the other zone (p) and prevents the zone (n.sup.+) from directly bordering the substrate (n.sup.

Abstract: An insulated-gate bipolar transistor (IGBT) is connected in reverse-parallel with a current-regenerative diode which, for economy of manufacture, is integrated with the IGBT. Such a diode may extend laterally on an IGBT chip, with two conductivity regions forming the diode respectively connected to emitter and collector electrodes of the IGBT. Alternatively, the diode may be formed by short-circuiting a buffer layer and a collector layer. By such integration, greater device packing density can be realized.

Abstract: An opto-electronic integrated circuit is arranged to comprise a photodetector and a tunnel emitter bipolar transistor for first-stage amplification of a current generated in the photodetector, as formed on a substrate. The tunnel emitter bipolar transistor can be operated at high speed and has a high amplification factor, so that noise due to the base current can be reduced upon amplification of the current generated in the photodetector by light detection.

Abstract: A semiconductor device having an electrostatic discharge protection device, in which the electrostatic discharge protection device comprises a vertical type bipolar transistor including, a semiconductor substrate, an epitaxial layer laminated on the semiconductor substrate, a buried collector of a first conductive type which is formed of the semiconductor substrate or which is formed from the surface of the semiconductor substrate to the epitaxial layer, a base of a second conductive type which is a lightly doped well and formed on the epitaxial layer, and an emitter of the first conductive type and formed on the surface layer of the base of the second conductive type; and in which the depth of the diffusion of the base being in the range from 0.8 to 2.3 microns, and the base and the emitter being shorted with each other.

Abstract: A semiconductor device, comprising a transistor, a constant voltage diode having a first end of a first conductivity type connected to an emitter of the transistor and a second end of a second conductivity type, a reverse current preventive diode having a first end of the first conductivity type connected to a collector of the transistor and a second end of the second conductivity type connected to the second end of the constant voltage diode, and a high speed diode reverse-bias connected between the transistor collector and the emitter of the transistor.

Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.

Abstract: A semiconductor device for influencing the breakdown voltage of a transistor with a surface electrode arranged over a space charge region, separated from the same by an oxide layer. The surface electrode is at a potential, as determined by a voltage divider, between the potentials of the base and collector of the transistor. The surface electrode includes two electrode plates insulated from one another, with the first electrode plate extending over a junction between a highly doped n.sup.+ collector region and a lightly doped n.sup.- collector region, and a junction between the lightly doped n.sup.- collector region and a p-type base region. The second electrode plate is bonded partly over the oxide layer and partly with the highly doped n.sup.+ collector region.

Abstract: A semiconductor device includes on a semiconductor substrate an output transistor which is composed of a collector region, a first base region and a first emitter region, and a temperature detection transistor composed of the collector region, a second base region and a second emitter region. The output transistor is provided at a center of the collector region of the semiconductor substrate. A vacant region is formed on a center of the output transistor, and the temperature detection transistor is provided in the vacant region.

Abstract: An integrated bridge device includes at least two arms, each of which is formed of a first and second diode connected transistor in series. The device is formed in an N+ substrate, which forms a positive output terminal. N- and N type epitaxial layers are formed over the substrate, and P and P+ regions are formed therein for each of the aforesaid arms. An N type region is contained within the P and P+ regions, and in turn contains a P type region forming a negative potential output terminal. Also included in the N type region are N++ regions capable of minimizing the current gain of parasitic transistors formed within the device.

Abstract: The ballast resistance of a semiconductor device is increased without decreasing the figure of merit of the device. The semiconductor device includes an emitter feeder, a first contact coupled to the emitter feeder, a second contact, a resistive medium connected between the first contact and the second contact, an emitter, and a further resistive medium connected between the second contact and the emitter. The ballast resistance of the semiconductor device is increased without decreasing the figure of merit of the device by increasing the distance between the first contact and the second contact.

Abstract: A semiconductor device comprises a half-bridge circuit, one of the two arms or elements of which is a thyrister, and the other is a bi-polar transistor. It is structured vertically as a single semiconductor chip with a primary conductor type cathode area of the thyrister and a primary conductor type collector area of the bi-polar transistor shared as common areas. A first isolation area is formed between a intermediate layer of the thyrister and the above described common area. A second isolation area is formed in the first isolation area provided between the intermediate layer of the thyrister and the base area of the bi-polar transistor. Because the upper and lower arms of the half-bridge are vertically structured, the circuit provides for excellent area efficiency, current amplification factor, and current capacity. No specific isolation layers are required to isolate the upper arm from the lower arm.

Abstract: A semiconductor device functioning as a diode, includes an insulated-gate field effect transistor for determining a breakdown voltage, and a bipolar transistor connected to the field effect transistor for amplifying a drain current of the field effect transistor. The field effect transistor and the bipolar transistor are formed in the same semiconductor substrate.

Abstract: A vertical fuse structure including a lightly-doped shallow emitter 30 provides improved fusing characteristics. The structure includes a buried collector 14, an overlying base 30, and an emitter 44 above the base 30. In one preferred embodiment, the emitter 44 extends about 0.2 microns from the upper surface and has a dopant concentration of about 8.times.1019 atoms of arsenic per cubic centimeter at the surface. A lightly doped base region 30 extends for about 0.46 microns below the emitter 44 to the collector 14. The upper surface of emitter 44 includes a metal contact 60. Heating the metal 60/emitter 44 interface to its eutectic melting point using a current or voltage pulse causes the aluminum to short through the emitter 44 to the base 30. Shorting the emitter programs the fuse. A second preferred embodiment uses polysilicon as an interconnecting medium.

Abstract: A high voltage MIS transistor includes a well region of a second conduction type formed by a step of injecting ions from the surface side of a semiconductor substrate of a first conduction type and a thermal diffusion step after the ion injecting step; an MIS part including a base layer of a first conduction type formed in one end portion of the well region, a base contact layer of a first conduction type which is formed in the base layer of a first conduction type and to which an emitter potential is applied, and a gate electrode provided so as to extend from an emitter layer of a second conduction type to the well region through an insulation gate film; and, a collector part including a base layer of a second conduction type formed in the other end portion of the well region, a collector layer of a first conduction type formed in the base layer of a second conduction type, and a high concentration contact layer of a first conduction type which is formed in the collector layer and to which a collector potent

Abstract: A semiconductor diode characterized by an anode electrode structure connected to a double diffusion of P-type impurities in a major surface of an N.sup.- semiconductor. The first diffusion forming a first plurality of P.sup.- well regions and the second diffusion selectively forming a second plurality of P.sup.+ well regions within the first well region.

Abstract: A process is disclosed which simultaneously forms high quality complementary bipolar transistors, relatively high voltage CMOS transistors, relatively low voltage CMOS transistors, DMOS transistors, zener diodes and thin-film resistors, or any desired combination of these, all on the same integrated circuit chip. The process uses a small number of masking steps, forms high performance transistor structures, and results in a high yield of functioning die. Isolation structures, bipolar transistor structures, CMOS transistor structures, DMOS transistor structures, zener diode structures, and thin-film resistor structures are also disclosed.

Abstract: An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element is provided which detects when the second parasitic element becomes active or which prevents increase of the collector-to-emitter voltage of the desired bipolar transistor in response to current flowing through the second parasitic transistor. This element may be a semiconductor region formed in the semiconductor layer. The transistor may be an npn or pnp type transistor manufactured according to a complementary bipolar process or other process which results in a transistor with first and second parasitic elements. The present invention is also well-suited for use in the output stage of an operational amplifier.

Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.

Abstract: Apparatus including a diamond semiconductor material bipolar transistor having associated therewith a distally disposed iso-collector. The iso-collector, when operated with a suitable voltage, provides a communicating electric field to the bipolar transistor collector which, in concert with a voltage coupled to the transistor base places the apparatus in an ON mode to induce electrons to be emitted from the collector and to be subsequently collected at the iso-collector. An iso-base is optionally, distally disposed relative to the base of the bipolar transistor.

Abstract: A sidewall construction is utilized in the fabrication of semiconductor devices comprising planar type bipolar transistors wherein the width of the sidewall construction can be accuracy controlled which, in turn, controls accuracy the channel length of the base of the planar type bipolar transistors. This technique provides ways of preventing short circuiting between the formed transistor collector and emitter regions of the planar type bipolar transistors. The sidewall construction can also be employed in fabrication combination planar type bipolar/MIS type transistors resulting in higher density of these structures over the prior art laterally positioned structures.

Abstract: In a transistor where collector is connected to an inductive load and switching current flows, a Zener diode comprising structure of plural pn-junctions constituted in series form to a polysilicon is provided between collector and base. Further MOSFET is switch-controlled by control voltage formed based on Zener current flowing through the Zener diode, and current path in parallel form to the Zener diode is constituted. Since temperature characteristic coefficient of a Zener diode formed in a polysilicon film is very small, the reverse voltage generated in the inductive load can be set to stable voltage in spite of the temperature variation. Further the MOSFET is provided in parallel form, thereby relatively large ON-resistance value of the Zener diode can be decreased.

Abstract: A logic circuit comprising an active-pull-down circuit in which electrodes of an active capacitor are formed of a conductive layer in common with one of contact electrodes of neighboring transistors is disclosed. The area for the capacitor is reduced, so that the element-occupied area is minimum even when the absorbing capability of the active-pull-down circuit is designed to be high for reducing a transient duration of an output signal. Besides, capacitor insulation film is used as a mask during a process, so that the process for fabrication of the integrated circuit is simplified.

Abstract: Disclosed is an improved bipolar-and-complementary MOS transistor coexisting semiconductor device and a method of making the same. A collector-and-base separator is formed on the site allotted to a bipolar transistor along with a source-and-drain separator on each site allotted to PMOS and NMOS transistors. The superficial collector-and-base separator coating causes no stress to the lattice of the underlying region in the epitaxy of the semiconductor substrate, and therefore there can be no lattice defect which may appear in a conventional composite type semiconductor device structure as a result of selective oxidization of the epitaxial layer to separate the base and collector region of the bipolar transistor. Such a superficial collector-and-base separator according to the present invention assures that the bipolar transistor each of such composite type semiconductor devices is free from the lowering of the breakdown voltage at its collector-and-base junction.

Abstract: A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., three sides) available for current flow, which allows obtaining a low base resistance, a low emitter resistance, a low collector resistance, a low base-collector capacitance, and a small size.

Abstract: Disclosed is an integrated transistor structure having increased conductance and operating speed including a complementary insulated gate field-effect transistor pair, each including a source and drain region with a gate contact positioned therebetween, ohmic contacts to the source and drain regions, and a p-n junction contact to each of the drain regions. The gates of the two transistors are interconnected and function as the input terminal, and the two p-n junction contacts are interconnected as the output of the device. The operation of the device is such that the lightly-doped drain regions act as bases of bipolar transistors, with the emitters formed by the p-n junction diodes. Minority carriers injected by the diodes modulate the channel regions, thereby lowering their resistivity and increasing the transconductance of the device without increasing the physical size or the capacitance of the device and thereby improving the speed of the device.

Abstract: An MIS capacitor for bipolar integrated circuits includes an island region of one conductivity type, a first semiconductor layer of one conductivity type formed in the island region, an insulating layer provided on the first semiconductor layer, a capacitor electrode provided on the insulating layer to provide an MIS capacitor element, and a second semiconductor layer of an opposite conductivity type for providing a PN junction with the first semiconductor layer. When the MIS capacitor element is reverse biased, majority carriers of the second semiconductor layer are supplied to a depletion layer generated in the first semiconductor layer, thereby providing an MIS capacitor having an approximately constant capacitance even if it is biased in a forward or reverse direction.

Abstract: A method is provided for forming multi-valued linear resistors for an integrated circuit using a single mask level. A plurality of trenches are defined in a substrate. Each trench has contact regions of a specific lateral dimension and a narrower portion extending therebetween. Successive conformal layers of a first dielectric layer, a first conductive layer of high resistivity and a second conductive layer of lower resistivity are provided to fill the trench. The amount of the second conductive layer which fills the trench depends on the width of the trench. The resulting structure is planarized, preferably by chemical-mechanical polishing to provide fully planarized topography. Advantageously when the first and second conductive layers are provided from layers of undoped and doped polysilicon respectively, the trench dimensions control the amount of dopant incorporated in each region of the trench.

Abstract: A power semiconductor device which is integrable in an integrated circuit includes a semiconductor body having first and second major opposing surfaces with a first doped region of a first conductivity type therebetween, second and third doped regions of a second conductivity type formed in the first doped region, the second and third doped regions being spaced apart and abutting the first surface, and fourth and fifth doped regions of the first conductivity type respectively formed in the second and third doped regions and abutting the first surface. Sixth and seventh doped regions extend from the first surface into the first region, the sixth region being adjacent to the second and fourth regions and spaced therefrom by an electrically insulative layer, the seventh region being adjacent to the third and fifth regions and spaced therefrom by an insulative layer.

Abstract: A bipolar power device and a fast diode are formed in a single chip of semiconductor material. The chip contains a first area having high minority carrier lifetimes in which the bipolar power device is formed. The bipolar power device is therefore capable of handling high current densities. At least one second area of the device is formed with reduced minority carrier lifetimes, with a fast diode being formed in this region.

Abstract: In a bipolar static induction transistor (BSIT) with increased input impedance, gate-voltage control is used for switching operations. The BSIT includes a collector region, a base region, an emitter region, and a source region in the base region. For enhanced turn-off, an auxiliary base region is included; alternatively, a drain region is provided in the base region.

Abstract: When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.

Abstract: A variety of field emission devices and structures which employ non-substrate layers of single-crystal silicon. By employing non-substrate layers of single-crystal silicon, improved emission control is achieved and improved performance controlling devices are formed within the device structure.

Abstract: A monolithic integrated circuit provides RF and DC coupling for a unit cell of a high power quasi-optic grid amplifier. The monolithic chip includes two heterojunction bipolar transistors (HBTs) connected in a differential pair configuration with a common emitter and integrated collector-base and emitter bias resistors. Each of the plurality of unit cells comprising the quasi-optic grid amplifier includes an emitter-coupled HBT differential pair chip at the center, an input antenna that extends horizontally in both directions from the two base leads, an output antenna that extends vertically in both directions from the two collector leads, and high inductance bias lines for the emitter and collectors. The grid amplifier, which functions as a high frequency, high gain, wide bandwidth, free-space beam amplifier, comprises a plurality of unit cells arranged in a repeating pattern of input and output dipole antennas.

Abstract: A semiconductor device including a semiconductor substrate, first and second bipolar transistors formed at the major surface of the semiconductor substrate, a Schottky-barrier diode formed on a predetermined area of each of the first and second bipolar transistors, a capacitor formed on each of the first and second bipolar transistors, each capacitor including an insulating layer covering a surface of a respective one of the first and second bipolar transistors, a polysilicon layer formed on the insulating layer in a pattern that extends around the predetermined area, a dielectric film formed covering the polysilicon layer, and a conductive film covering the dielectric film.

Abstract: A semiconductor integrated circuit is provided which can have a high holding current without the penalty of a high gate current. Such a circuit includes a PNPN device and junction bipolar transistor in which a further doped region of the same conductivity type as the transistor collector region and more heavily doped than the collector region prevents the devices affecting each other. The junction bipolar transistor has a current gain of at least 10 and base-collector and base-emitter junctions with reverse breakdown voltages of at least 50 volts. A PN diode can also be used in the circuit.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.