Abstract: An avalanche diode is formed in an N layer (20) of a bipolar integrated circuit. The diode comprises a first (P) region (22) and N region (21) disposed inside the first region. The portion of the first region which resides under the N region and close to the interface with the latter has a first doping level. A second (P) region (23) extends under the N region with a second doping level higher than the first close to the junction. A third P region (30) is disposed under the N region and overlaps the second P region. The third region has, at its interface with the N region, a doping level intermediate the first and second doping levels.

Abstract: A semiconductor switching device that is suitable for use as a remote isolation device (RID) in telephone networks. The semiconductor switching device is a two-terminal voltage sensitive device that switches from an open-circuit condition to a short-circuit condition at a fixed breakover voltage, appears as an open-circuit below the breakover voltage, and appears as a short-circuit above the breakover voltage. When semiconductor switching devices are installed in a telephone network, they are held in their short-circuit condition by the network voltage supply and do not affect the normal operation of the network but will switch to their open-circuit condition if the network voltage supply is reduced to below the breakover voltage, and therefore, parts of the network may be isolated from each other by reducing the voltage supply. Isolation of the parts of the network from each other facilitates testing for maintenance purposes.

Abstract: A low breakdown voltage device for protecting an integrated circuit from transient energy is disclosed. This device provides an SCR having a reduced "snap-back" trigger voltage compatible with submicron integrated circuit fabrication processes. A low breakdown voltage SCR protection circuit is also disclosed.

Abstract: A semiconductor chip has at least one electrical resistor means, at least one semiconductor component arranged in the semiconductor chip, and at least one metallization for the semiconductor component on the semiconductor chip. At least one resistor means is at least partially arranged under the metallization. This permits a space requirement for the resistor means on the semiconductor chip to be reduced.

Abstract: A bipolar DRAM comprises a switching transistor, a storage capacitor and a substrate. The switching transistor and the storage capacitor are vertically stacked with each other. The switching transistor is preferably an NPN bipolar transistor. The switching transistor preferably comprises P.sup.- base region, an N.sup.+ emitter region of the substrate, a N.sup.+ collector region, with a lower epitaxial layer between the N.sup.+ emitter region and P.sup.- base region, and an upper epitaxial layer between the P.sup.- base region and N.sup.+ collector region. The storage capacitor comprises a storage electrode formed on the N.sup.+ collector region, a dielectric layer and a plate electrode. The dielectric layer and the plate electrode are vertically and sequentially stacked on the storage electrode. A bit line is formed on the plate electrode, and a word line is formed on the side surface of the P.sup.+ base region.

Abstract: The base-collector capacitance in a heterojunction bipolar transistor (HBT) (50) is reduced, thereby providing increased cutoff frequency and power gain, by eliminating a portion of a collector contact layer (54) which normally underlies a base electrode (66). A similar effect may be produced by forming the collector contact layer (54) such that it initially extends into the area (54c) under the base electrode (66), and subsequently rendering the collector contact layer (54) in this area (54c) semiinsulative by proton bombardment. A ballast resistor layer (70) is formed between an emitter layer (62) and an overlying emitter electrode (68) to prevent thermal runaway and hot spot formation. A plurality of the HBTs (50) may be arranged in a distributed amplifier configuration (80) including contact electrode bus lines (84,88) having a geometry designed to provide high thermal efficiency, and input and output circuit matching characteristics.

Abstract: An integrated circuit has an input, a terminal for a reference potential, and a semiconductor substrate. An input protection structure for the integrated circuit is disposed in the semiconductor substrate and is connected between the input and the terminal for a reference potential. The input protection structure includes at least one transistor and an integrated diode. The at least one transistor has a collector in the form of a buried zone connected to the input, an emitter in the form of at least one doped zone to be connected to the reference potential, the collector and emitter defining a collector-to-emitter path, and a base in the form of at least one doped zone being insulated except for electrical contact with the emitter and the collector. The integrated diode is formed by at least the buried zone and the semiconductor substrate and is connected parallel to the collector-to-emitter path of the transistor.

Abstract: A BiMOS integrated circuit device comprises a bipolar transistor and at least one MOSFET. The collector and emitter of the bipolar transistor are connected to a high potential source and a low potential source, respectively. The MOSFET has two gate electrodes, a source, and a drain. The source is connected to the high potential source, and the drain is the base of the bipolar transistor by a diffusion layer. The diffusion layer is located between the gate electrodes, and serves as both the base of the bipolar transistor and the drain of the MOSFET. Therefore, the MOSFET has a great channel width, and a large current can be supplied to the base of the bipolar transistor. In other words, the MOSFET has a great driving capability, and the bipolar transistor has a high amplification factor.

Abstract: A base resistance controlled thyristor with integrated single-polarity gate control includes a thyristor having an anode region, a first base region, a second base region on the first base region and a cathode region contacting the second base region and defining a P-N junction therewith. For providing gated turn-off control, a depletion-mode field effect transistor is provided on the second base region and is separated therefrom by an insulating region. In particular, an insulating region, such as a buried dielectric layer, is provided on the second base region and the depletion-mode field effect transistor is formed thereon. The depletion-mode field effect transistor is electrically connected between the cathode contact and the second base region and provides a direct electrical connection therebetween in response to a turn-off bias signal which is preferably a zero or near zero bias.

Abstract: A lateral PNP transistor having either of the collector or the emitter diffusion layers layered with an n.sup.+ type diffusion layer, is shown. The added layer serves to increase the static electricity withstand stress along a transistor discharging path. A low withstand stress contributes to transistor damage at high breakdown voltages. When an n.sup.+ diffusion layer is formed within a diffusion layer in a lateral PNP transistor the transistor behaves as a combination of two transistors, PNP and NPN, selectively configured.

Abstract: This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is a (111) plane is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of <110> axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.

Abstract: A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer.

Abstract: A semiconductor device comprises a substrate of a first conduction type defined by a major surface, a pair of conductive regions of a second conduction type formed in the substrate along the major surface, an intervening region of the first conduction type formed in the substrate between the pair of conductive regions so as to separate the pair of conductive regions from each other, a first insulator film provided on the substrate so as to cover the major surface thereof including the pair of conductive regions and the intervening region located therebetween, a first conductor layer provided so as to extend generally parallel to the major surface of the substrate with a separation from the first insulator film, the first conductor layer crossing a part of the intervening region at a level separated therefrom, a second conductor layer provided on the first insulator film at a level below the first conductor layer so as to cover at least the part of the intervening region which is crossed by the first conductor

Abstract: A semiconductor device in which on-operation by a low voltage can be realized, the discontinuity of a current-to-voltage characteristic can be solved, and current concentration in the device configuration is reduced to prevent device break.

Abstract: A MOS type semiconductor device comprising a plurality of second conductivity type channel regions having a predetermined impurity density selectively formed in the surface of a first conductivity type semiconductor layer. A channel in the semiconductor layer is formed between adjacent ones of the channel regions, and source regions of the first conductivity type are selectively formed in a surface of each one of the channel regions. A well region of the second conductivity type is formed with a predetermined depth in a middle portion of each one of the plurality of channel regions and has an impurity density higher than that of the channel regions. An insulating layer is formed on the surface of the semiconductor layer, gate electrodes are formed on the insulating layer and overlaying the channel in the first conductivity type semiconductor layer, and a main electrode is formed in contact with at least one of the source region and the well region.

Abstract: An input protection structure for integrated circuits to be connected between an input and a reference potential includes a resistor. At least one transistor has a collector connected to the input, a base connected through the resistor to the reference potential, and an emitter connected to the reference potential. A semiconductor substrate has a first conduction type. The collector is in the form of a buried collector of a second conduction type in the semiconductor substrate. The base is in the form of at least one doped zone of the first conduction type having a base connection. The emitter is in the form of a doped zone of the second conduction type having an emitter connection. The resistor is in the form of at least one further doped zone of the first conduction type being connected to the emitter exclusively through the emitter connection and being connected to the base exclusively through the base connection.

Abstract: An integrated circuit die contains a total of at least 10,000 bipolar logica cells that dissipate at least 75 watts of power. To supply such a large amount of power to the logic cells, thin sputtered power busses of 3 .mu.m thickness overlie the logic cells; an insulating layer surrounds the power busses; openings in the insulating layer defined plating regions on the power busses; an electroplating base film lies throughout the plating regions; and, a thick plated conductor, of at least 16 .mu.m thickness, lies on the electroplating base film. By supplying power to the bipolar logic cells via the composite structure of the thin power busses and thick plated conductors, a noise margin problem in the logic cell output signals is avoided. With 16 .mu.m thick plated conductors, the total number of logic cells on the die can be increased until their total power dissipation reaches 75 watts. With 21 .mu.m thick plated conductors, total die power can be increased to 100 watts.

Abstract: A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.

Abstract: A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.

Abstract: An integral Bi-CMOS logic circuit includes a pair of first transistors and a pair of second transistors. The pair of the first transistors includes a P-type MOS transistor receiving an input signal through its gate, and an NPN-type bipolar transistor with its base connected to the drain of the P-type MOS transistor outputting a first output signal. The pair of the second transistors includes an N-type MOS transistor receiving the input signal through its gate, and a PNP bipolar transistor with its base connected to the drain of the N-type MOS transistor outputting the first output signal. A final output signal is outputted through a common emitter of the bipolar transistors.