Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

Abstract: A semiconductor device comprises a semiconductor chip having a plurality of electrode pads; an insulation layer having one or more apertures which expose at least a part of the plurality of electrode pads respectively on the semiconductor chip; and a plurality of wires which are electrically connected to the exposed plurality of electrode pads.

Abstract: A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step.

Abstract: A substrate for a semiconductor package includes: a first dielectric having a first surface and a second surface which faces away from the first surface and possesses waveform shaped portions, and formed with first holes penetrating the first and second surfaces; and circuit traces formed over the second surface of the first dielectric and having waveform shaped portions disposed over the waveform shaped portions of the second surface of the first dielectric. The waveform shaped portions of the second surface of the first dielectric and the waveform shaped portions of the circuit traces form a stress-resistant structure.

Abstract: A semiconductor device includes a first extended semiconductor chip including a first semiconductor chip and an extension extending outwardly from a side surface of the first semiconductor chip. The semiconductor device also includes a second semiconductor chip mounted above the first extended semiconductor chip and electrically connected with the first semiconductor chip. The first extended semiconductor chip includes a first extension electrode pad provided above the extension and electrically connected with an electrode of the first semiconductor chip.

Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.

Abstract: In a QFN that includes a die pad, a semiconductor chip mounted on the die pad, a plurality of leads arranged around the semiconductor chip, a plurality of wires that electrically connect the plurality of electrode pads of the semiconductor chip with the plurality of leads, respectively, and a sealing member sealing the semiconductor chip and the plurality of wires, first and second step portions are formed at shifted positions on the left and right sides of each of the leads to make the positions of the first and second step portions shifted between the adjacent leads. As a result, the gap between the leads is narrowed, thereby achieving the miniaturization or the increase in the number of pins of the QFN.

Abstract: A semiconductor device configured to enable efficient cooling of an element and downsizing of the device. The semiconductor device including an element unit connected to a surface of a cooler. A support member that has a condenser housing chamber that houses the condenser. The condenser has two parallel planar surfaces that are parallel with each other. The condenser housing chamber has a parallel opposing surface that is arranged in parallel with the element unit arrangement surface and faces the element unit arrangement surface, and houses the condenser in a state where the two parallel planar surfaces are arranged in parallel with the parallel opposing surface. The support member is fixed to the cooler in a state where the parallel opposing surface presses the element unit toward the cooler.

Abstract: Provided is a technique for packaging a sensor structure having a contact sensing surface and a signal processing LSI that processes a sensor signal. The sensor structure has the contact sensing surface and sensor electrodes. The signal processing integrated circuit is embedded in a semiconductor substrate. The sensor structure and the semiconductor substrate are bonded by a bonding layer, forming a sensor device as a single chip. The sensor electrodes and the integrated circuit are sealed inside the sensor device, and the sensor electrodes and external terminals of the integrated circuit are led out to the back surface of the semiconductor substrate through a side surface of the semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor chip, multiple terminals arranged in a first direction, a resin portion sealing the semiconductor chip and the terminals. The terminals are projected from a side surface of the resin portion in a second direction, and include at least one subject terminal having a first portion and a second portion. In the subject terminal, a first longitudinal end of the first portion is positioned inside of the resin portion and a second longitudinal end of the first portion is positioned outside of the resin portion, and the second portion is arranged adjacent to the first portion. Further, a length of the first portion is greater than a length of the second portion in the third direction, and a length of the first portion is smaller than a length of the second portion in the first direction.

Abstract: A MEMS device (20) with stress isolation includes elements (28, 30, 32) formed in a first structural layer (24) and elements (68, 70) formed in a second structural layer (26), with the layer (26) being spaced apart from the first structural layer (24). Fabrication methodology (80) entails forming (92, 94, 104) junctions (72, 74) between the layers (24, 26). The junctions (72, 74) connect corresponding elements (30, 32) of the first layer (24) with elements (68, 70) of the second layer (26). The fabrication methodology (80) further entails releasing the structural layers (24, 26) from an underlying substrate (22) so that all of the elements (30, 32, 68, 70) are suspended above the substrate (22) of the MEMS device (20), wherein attachment of the elements (30, 32, 68, 70) with the substrate (22) occurs only at a central area (46) of the substrate (22).

Abstract: A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by disposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls.

Abstract: According to an exemplary embodiment, a power semiconductor package includes a power module having a plurality of power devices. Each of the plurality of power devices can be a power switch. The power semiconductor package also includes a double-sided heat sink with a top side in contact with a plurality of power device top surfaces and a bottom side in contact with a bottom surface of the power module. The power semiconductor package can include at least one fastening clamp pressing the top side and the bottom side of the double-sided heat sink into the power module. The double-sided heat sink can also include a water-cooling element.

Abstract: A package includes a body that encapsulates a semiconductor die, the body having a first pair of opposing lateral sides, a second pair of opposing lateral sides, a top, and a bottom. The bottom has a primary surface and a plurality of protrusions that extend outward from the primary surface. When the package is mounted to a printed circuit board (PCB) the protrusions contact the PCB and the primary surface is disposed a first distance away from the PCB. The package further includes a plurality of leads that extend outward from the first pair of opposing lateral sides.

Abstract: An apparatus for a semiconductor-package includes a semiconductor device having a radio frequency (RF) input or output, an antenna pad, and a package structured to house the semiconductor device and the antenna pad. The antenna pad may be coupled to the radio frequency (RF) input or output, and the antenna pad is structured to reduce the inductance of the package. The antenna pad may include a pad disposed above the semiconductor device, a pad disposed to a side of the semiconductor device, or an antenna chip. An antenna may be coupled to the antenna pad. The antenna may include a trace antenna, a staggered antenna, or a helical antenna.

Abstract: An illumination unit includes one or more light sources each including a solid-state light-emitting device configured to emit light from a light emission region including a single or a plurality of light-emitting spots. The solid-state light-emitting device includes a single chip or a plurality of chips each emitting a light beam. Three or more of the light-emitting spots are provided within the whole of one or more light sources, to allow the whole of one or more light sources to emit light beams in two or more wavelength bands different from one another, and the solid-state light emitting device in a first light source which is at least one of the one or more light sources, has a plurality of light-emitting spots which emit light in the same wavelength band.

Abstract: According to an embodiment, a semiconductor device includes a silicon substrate, an insulation film, and a plurality of chip-side connection terminals. The silicon substrate is internally provided with a first wire layer. The insulation film is stacked on a first surface of surfaces of the silicon substrate, the first surface being approximately parallel to the first wire layer. The chip-side connection terminals are electrically connected to the wire layer. Moreover, the chip-side connection terminals are exposed on a second surface side, the second surface being continuous from the first surface in an approximately perpendicular manner.

Abstract: Disclosed herein are chip packaging structures for packaging multiple assemblies therein. In one embodiment, a chip packaging structure can include: (i) a first assembly located at a bottom layer of the chip packaging structure; (ii) at least one second assembly located above the first assembly, where the second assembly is electrically connected to the first assembly by a plurality of first protruding structures located under the second assembly; (iii) at least one third assembly located above the second assembly, where the third assembly is electrically connected to the first assembly by a plurality of second protruding structures located outside of the second assembly; and (iv) where a first portion of the third assembly and the plurality of second protruding structures form a bent structure substantially perpendicular to a second portion of the third assembly.

Abstract: Disclosed herein are various chip packaging structures and arrangements. In one embodiment, a multiple-component chip packaging structure can include: (i) a first component arranged on a bottom layer; (ii) at least one second component arranged on the first component, where the at least one the second component is electrically connected to the first component by a plurality of protruding structures; (iii) at least one third component on the at least one second component; (iv) at least one extension structure arranged on at least one side of the at least one third component, where the at least one extension structure is configured to lead out electric polarities of the at least one third component; and (v) a plurality of bonding wires that electrically connect the at least one extension structure to the first component.

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.

Abstract: Some embodiments of the present disclosure provide the design and manufacture of an ultra-small chip assembly. The ultra-small chip assembly comprises a die, a plate-like back electrode disposed on the back-side of the die, and one or more plate-like positive electrodes disposed on the front-side of the die. The ultra-small chip assembly is configured such that one end of the plate-like back electrode extends beyond a first side of the die, and each of the one or more plate-like positive electrodes includes an end which extends beyond a second side of the die. By attaching both the plate-like back electrode and the plate-like positive electrodes on the surfaces of the die, and directly using the exposed ends of the plate-like electrodes as the lead-out electrodes for the chip assembly, the electrical connections outside of the die only occupy a very small volume.

Abstract: A manufacturing method of a lead frame substrate includes: applying a photosensitive resist or a dry film to first and second surfaces of a metal plate; pattern-exposing the photosensitive resist or the dry film, and then developing the first surface and the second surface to form on the first surface a first resist pattern for forming a connection post and to form on the second surface a second resist pattern for forming a wiring pattern; etching the first surface partway down the metal plate to form the connection post; filling the first surface with a pre-molding resin to a thickness with which the etched surface is buried; removing the pre-molding resin uniformly in a thickness direction of the pre-molding resin until a bottom surface of the connection post is exposed; and etching the second surface to form a wiring pattern.

Abstract: A sensor device has a ceramic carrier substrate. At least two conductor tracks are arranged on the carrier substrate. The sensor device has at least one ceramic component that is in the form of a chip and is connected to the conductor tracks in an electrically conductive manner. The at least one ceramic component is mechanically connected to the conductor tracks by means of a screen printing paste which has been burnt in.

Abstract: There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal.

Abstract: A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: An integrated circuit includes a main body, a number of connection tabs molded on the main body, and a number of pins respectively connected to the connection tabs. The connection tabs and the pins are made of metal. The connection tabs are electrically connected to a logic circuit in the main body.

Abstract: In accordance with the present invention, there is provided a semiconductor package or device including a uniquely configured leadframe sized and configured to maximize the available number of exposed lands in the semiconductor device. More particularly, the semiconductor device of the present invention includes a die pad (or die paddle) defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads and lands which are provided in a prescribed arrangement. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads and lands. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the lands being exposed in a common exterior surface of the package body.

Abstract: A semiconductor module system includes a substrate, at least one semiconductor chip, and a number of at least two electrically conductive first connecting elements. The substrate has a bottom side and a top side spaced apart from the bottom side in a vertical direction. The at least one semiconductor chip is arranged on the top side. Each one of the first connecting elements has a first end which protrudes away from an insulation carrier of the substrate in a direction perpendicular to the vertical direction. The semiconductor system further includes a connecting system with a number of N?1 connectors. A first one of the connectors includes at least two electrically conductive second connecting elements. Each one of the second connecting elements has a first end. The first end of each one of the first connecting elements is electrically conductively connectable to the first end of one of the second connecting elements.

Abstract: Reliable electrical contact is made with electronic components and effective electrical isolation is produced between the top and bottom of the electronic components. An electronic component is arranged inside a window in a first layer on a substrate. Next, a second layer is put on such that contact areas on the component and contact points on the first layer are freely accessible. Electrical contacts and electrical connecting lines are produced by electrodeposition. The second layer is used to produce bridges over an interval range between the electronic component and the first layer. The bridges have connecting lines formed on them. The second layer can be removed again. Radio-frequency modules can be produced in compact fashion and can be combined with audio-frequency components.

Abstract: An LED includes a base, a first lead and a second lead mounted to the base, a light emitting chip electrically connected to the first lead and the second lead, and an encapsulant sealing the chip. The first lead and the second lead each include a first beam and a second beam connected to each other. Each of the first beam and the second beam has two opposite ends protruding beyond two opposite lateral faces of the base, respectively, for electrically connecting with a circuit board.

Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: A semiconductor apparatus comprising an integrated semiconductor circuit device having pluralities of electrode pads, pluralities of first external terminals connected to the electrode pads of the integrated semiconductor circuit device, an inductor disposed in a region surrounded by the first external terminals, and a resin portion sealing them, the integrated semiconductor circuit device being arranged on an upper surface of the inductor, and the inductor being exposed from a lower surface of the resin portion together with the first external terminals.

Abstract: A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region overlying the surface region. Each of the integrated micro electro-mechanical systems and electronic devices has one or more contact regions. The first region has a first surface region. One or more trench structures are disposed within one or more portions of the first region. A passivation material overlies the first region and the one or more trench structures. A conduction material overlies the passivation material, the one or more trench structures, and one or more of the contact regions. The device also has one or more edge bond pad structures within a vicinity of the one or more bond pad structures, which are formed by a singulation process within a vicinity of the one or more bond pad structures.

Abstract: An LED light module free of jumper wires has a substrate and multiple LED chips. The substrate has a positive side circuit, a negative side circuit, multiple first chip connection portions and multiple second connection portions. The first and second chip connection portions are respectively connected to the positive and negative side circuits, and are juxtaposedly and alternately arranged on the substrate so that a width between each first chip connection portion and a corresponding second chip connection portion is smaller than a width of each LED chip. Each LED chip can be directly mounted on corresponding first and second chip connection portions to electrically connect to the positive and negative side circuits. Accordingly, jumper wires for connecting the LED chips and the positive and negative side circuits can be removed to avoid broken jumper wires occurring when the LED light module is shipped or assembled.

Abstract: Provided is a light emitting device package. The light emitting device package comprises a housing, first and second lead frames, and a light emitting device. The housing comprises a front opening and side openings. The first and second lead frames pass through the housing to extend to an outside. A portion of each lead frame being exposed through the front opening. The light emitting device is in the front opening and electrically connected to the first and second lead frames. A protrusion protruding in a direction of the side opening is formed on an inner surface of the side opening.

Abstract: A connection element is arranged on a connection area of a semiconductor component. The connection element includes at least one bonding wire portion fixed on the connection area. The connection area is covered by an electrically conductive material, the fixed bonding wire portion being surrounded or embedded by the electrically conductive material.

Abstract: A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

Abstract: A lead frame substrate, including: a metal plate with a first surface and a second surface; a connection post formed on the first surface; wiring formed on the second surface; and a pre-molding resin layer, in which a thickness of the pre-molding resin layer is the same as a height of the connection post.

Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A mounting board includes two or more metal layers including the outermost metal layer, and a plurality of metal portions, both of which are formed on a substrate. The plurality of metal portions are formed between a first metal layer of the two or more metal layers and a second metal layer of the two or more metal layers, the first metal layer being the outermost metal layer and the second metal layer being different from the outermost metal layer. The second metal layer includes a plurality of first wiring layers extending in a first direction in a plane. The first metal layer is arranged in zigzags in a second direction intersecting with the first direction and includes a plurality of contact pads connected correspondingly to the plurality of first wiring layers through the metal portions.

Abstract: A power semiconductor module (100) includes: an electrode plate (2) in which a body portion (2a) and an external connection terminal portion (2b) are integrally formed, and the body portion (2a) is arranged on the same flat surface; a semiconductor chip (1) mounted on one surface (mounting surface) (2c) of the body portion (2a); and a resin package (3) in which the other surface (heat dissipation surface) (2d) of the body portion (2a) is exposed, and the body portion (2a) of the electrode plate (2) and the semiconductor chip (1) are sealed with resin. The heat dissipation surface (2d) is the same surface as the bottom (3a) of the resin package (3); and consequently, heat dissipation properties and reliability are improved and a reduction in size can be achieved.

Abstract: A semiconductor integrated circuit device includes a semiconductor chip having a memory cell array region surrounded with a peripheral circuit region and includes a plurality of bonding pads disposed at least in one row on only one side of the semiconductor chip. The circuit device may include first leads group disposed adjacent to the bonding pad side and a second leads group disposed opposite the first leads group. The second leads group may be formed over a portion of the semiconductor chip (lead-on-chip structure). A plurality of bonding wires connect the first and second leads group with the plurality of bonding pads respectively.