Abstract: A chip package transmitting slow speed signals via edge connectors and high speed signals by means of through-silicon-vias. The edge connectors are formed in recesses formed in the sidewalls of the package.

Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.

Abstract: In an arrangement having at least one substrate, at least one electrical component is disposed on a surface section of the substrate and is provided with an electrical contact area, and at least one electrical contact lug has an electrical connecting area electrically contacting the contact area of the component. The connecting area of the contact lug and the contact area of the component are interconnected so that at least one zone of the contact lug protrudes beyond the area of the component. The contact lug is provided with at least one electrically conducting film while the electrically conducting film is provided with the electrical connecting area of the contact lug. The arrangement is particularly useful for large-area, low-inductive contacting of power semiconductor chips, as it allows for high current density.

Abstract: Packaged semiconductor devices and assemblies including interconnects and methods for forming such interconnects are disclosed herein. One embodiment of a packaged semiconductor assembly includes a die attached to a support layer. A plurality of interconnects are embedded in and project from the support layer, such that the support layer at least partially retains the interconnects in a predetermined array. An encapsulant is molded around each of the interconnects and encases at least a portion of the die, support layer and interconnects.

Abstract: A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of thermal expansion of the die, the conductive metal bond layer and the substrate. An additional coating of conductive metal may be flowed over the bond lines to reinforce the bonds.

Abstract: The semiconductor apparatus includes a semiconductor chip, and a source electrode and a gate electrode which are formed on the semiconductor chip and electrically connected with a lead frame. The source electrode is electrically connected with the lead frame by being laser-welded with a thin-film shaped connecting portion formed at an end of the lead frame. This enables the provision of a semiconductor apparatus with enhanced productivity and yields which exhibits high electrical operability and reliability.

Abstract: A semiconductor chip package including a film substrate and a semiconductor chip loaded on the semiconductor chip is provided. The semiconductor chip includes a plurality of input pads and a plurality of output pads. A power supply input pad of the input pads is formed at a different edge from an edge of the semiconductor chip where other input pads are formed. The film substrate includes input lines and output lines. The input lines of the film substrate are connected to the corresponding input pads of the semiconductor chip, and the output lines thereof are connected to the corresponding output pads of the semiconductor chip.

Abstract: A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

Abstract: Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups.

Abstract: An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.

Abstract: A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections.

Abstract: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric film or other circuit panel material.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die.

Abstract: An integrated circuit substrate includes an integrated circuit chip having a plurality of electrically conductive pads on a surface thereof and a printed circuit board mounted to the integrated circuit chip. The printed circuit board includes an alternating arrangement of first and second electrically conductive bond fingers. These first and second bond fingers are elevated at first and second different heights, respectively, relative to the plurality of electrically conductive pads. The printed circuit board also includes a first plurality of electrically insulating pedestals supporting respective ones of the first electrically conductive bond fingers at elevated heights relative to the second electrically conductive bond fingers. First and second pluralities of electrical interconnects (e.g., wires, beam leads) are also provided.

Abstract: Provided is a semiconductor package including multiple semiconductor chips, and separate groups of leads connected to the semiconductor chips. The leads are exposed to the outside of the semiconductor package. The plurality of leads may include a first lead group for a first chip group and a second lead group for a second chip group. The first and second chip groups are part of the package.

Abstract: An electrical connection inside a semiconductor device is established by lead frames formed of plural conductor plates. The lead frames are disposed three-dimensionally so that the respective weld parts thereof are exposed toward a laser light source used in the laser welding. The laser welding is then performed by irradiating a laser beam. According to the above, welding can be performed readily in a reliable manner. The productivity of the semiconductor device and the manufacturing method of the semiconductor device can be thus enhanced. In addition, because the lead frames have the cooling effect, they have the capability of a heat spreader. It is thus possible to provide a semiconductor device and a manufacturing method of the semiconductor device with high productivity.

Abstract: A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation portion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

Abstract: An electronic device comprises a substrate and at least a warped spring connector. The substrate has a signal bonding pad and a ground plane. The warped spring connector is disposed on the substrate and is connected to the bonding pad. The warped spring connector includes at least a ground lead electrically connected to the ground plane, a dielectric layer on the ground lead, and a transmitting lead on the dielectric layer. The transmitting lead is bonded to the bonding pad. The ground lead is isolated from and close to the transmitting lead to solve cross-talk and noise problem. Furthermore, the coefficient of thermal expansion of the transmitting lead is different from that of the dielectric layer or the ground lead such that the warped spring connector has a suspending end suspending away from the substrate.

Abstract: The present invention provides a diode that does not deteriorate its function even if it is used in an environment where the temperature change is considerable, such as in a terminal box for solar cell panel that is placed outdoors. A diode of twin-chip-mounting type in which each chip has a lead foot for being joined to a common terminal plate, wherein said lead feet are electrically connected with each other in a region of each lead foot from each chip to a portion wherein each lead foot is joined. The electrical connection of the lead feet is preferably formed by integral molding with each lead foot.

Abstract: A reliable semiconductor device including support bumps so as to adequately seal the region between the chips is to be provided. The semiconductor device includes a semiconductor chip; a bump formed on an upper face of the semiconductor chip; and a plurality of support bumps formed along a circumference of the region where the bump is provided, formed on the upper face of the semiconductor chip; and a flow path for a sealing resin is provided between the plurality of support bumps, so as to connect the region where the bump is provided and a periphery region of the semiconductor chip.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead.

Abstract: A semiconductor package includes a leadframe having first and second level downset lead extensions, a quad flat nonleaded package (QFN) attached to the first level downset lead extension, and a flip chip die attached to the second level downset lead extension. Another embodiment of a semiconductor package includes a leadframe having a lead, a first quad flat nonleaded package (QFN) connected to the lead, and a second quad flat nonleaded package invertly connected to a top surface of the first quad flat nonleaded package, wherein the second quad flat nonleaded package is wirebonded to the lead. A third embodiment of a semiconductor package includes a leadframe having a lead with a first level downset lead extension, a quad flat nonleaded package (QFN) connected to the first level downset lead extension, and a first wirebondable die attached to a top or bottom surface of the quad flat nonleaded package.

Abstract: An image sensor power distribution arrangement includes a sensing portion having a first contact at a first edge thereof and a second contact at a second edge thereof, and a control portion. A first power supply supplies power to the sensing portion via the first contact. A second power supply supplies power to the sensing portion via the second contact, and to the control portion.

Abstract: A power semiconductor device (1; 37) has a leadframe (4), at least one vertical power semiconductor component (2) and at least one further electronic device (3) which is arranged on the power semiconductor component (2). The chip carrier (5) of the leadframe (4) has at least two separate parts (7, 8) on which the power semiconductor component (2) is arranged. The power semiconductor component (2) is embodied such that the lower surface (28) of the first part (7) of the chip carrier (5) provides a ground contact area (36) of the power semiconductor component (2).

Abstract: A method of making a semiconductor device is provided. The method includes the following steps. First, a semiconductor chip is mounted on a lower conductor, with first solder material applied between the chip and the lower conductor. Then, an upper conductor is placed on the chip, with second solder material applied between the chip and the upper conductor. Then, the first and the second solder materials are heated up beyond their respective melting points. Finally, the first and the second solder materials are allowed to cool down, so that the first solder material solidifies earlier than the second solder material.

Abstract: Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: A semiconductor package is disclosed including a plurality semiconductor die mounted on stacked and bonded layers of substrate, for example polyimide tape used in tape automated bonding processes. The tape may have a plurality of repeating patterns of traces and contact pads formed thereon. The traces each include aligned interconnect pads on the respective top and bottom surfaces of the substrate for bonding the traces of one pattern to the traces of another pattern after the patterns have been singulated from the substrate, aligned and stacked. Semiconductor die such as flash memory and a controller die are mounted on the traces of the respective patterns on the substrate. In order for the controller die to uniquely address a specific flash memory die in the stack, a group of traces on each substrate supporting the memory die are used as address pins and punched in a unique layout relative to the layout of the traces other substrates.

Abstract: A vertical power semiconductor component (1) having a top side (3) and a rear side (4) is provided. The top side (3) has at least one first electrode contact area (8) and at least one control electrode area (9) and the rear side (4) has a second electrode contact area (7). A first metallization (10) having a thickness a is arranged on the first electrode contact area (8). A second metallization (11) having a thickness b is arranged on the control electrode area (9). A third metallization (6) having a thickness c is arranged on the second electrode contact area (7). The thickness a of the first metallization (10) is at least 10 times thicker than the thickness b of the second metallization (11).

Abstract: A device includes a first semiconductor die having a first surface and a second surface. The first semiconductor die is configured to communicate by capacitive coupling using one or more of a plurality of proximity connectors proximate to the first surface. The first semiconductor die is configured to have a flexibility compliance greater than a first pre-determined value in a direction substantially perpendicular to a plane including the plurality of proximity connectors in order to reduce misalignment in the direction between the plurality of proximity connectors and additional proximity connectors on another device.

Abstract: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.

Abstract: An IC package to enhance the bondibility of embedded bumps, primarily includes a substrate having a plurality of bump-accommodating holes, a bumped chip, an encapsulant, and a plurality of external terminals. The substrate further has a plurality of inner pads at one ends of the bump-accommodating holes respectively. The inner pads may be meshed or a soldering layer is disposed thereon for improving bump connection. The chip is attached to the substrate with the bumps aligned and embedded in the corresponding bump-accommodating holes. The encapsulant is at least formed on a lower surface of the substrate to encapsulate the meshes or the soldering layer. By the suspended meshes or/and the soldering layer, the bumps can be easily bonded at lower temperatures to simplify the manufacturing process with shorter electrical conductive paths and thinner package profiles without wire sweeping.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

Abstract: An electronic component has at least one semiconductor power switch with at least one anode and at least one control electrode positioned on a first surface and at least one cathode positioned on a second surface and a heat sink with a die attach region with an upper surface. The electronic component also comprises a plurality of leads. A control lead has an upper surface which lies in a plane generally coplanar with the upper surface of the die attach region in its inner portion and above the upper surface of the inner portion in its centre portion. The anode of the semiconductor power switch is mounted on the die attach region of the heat sink and at least one control electrode is mounted on the upper surface of the inner portion of the control lead.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

Abstract: An electronic device and manufacturing thereof. One embodiment provides a semiconductor chip having a control electrode and a first load electrode on a first surface and a second load electrode on a second surface. A first lead is electrically coupled to the control electrode. A second lead is electrically coupled to the first load electrode. A third lead is electrically coupled to the first load electrode, the third lead being separate from the second lead. A fourth lead is electrically coupled to the second load electrode, the second and third leads being arranged between the first and fourth leads.

Abstract: In a semiconductor integrated circuit device including a semiconductor integrated circuit board having a mask ROM area and an internal bus and a programmable ROM which is mounted on the semiconductor integrated circuit board and which has a plurality of ROM connecting terminals, the ROM connecting terminals are electrically connected to a plurality of bus connecting terminals connected to the internal bus, respectively. The bus connecting terminals may be disposed around periphery of the semiconductor integrated circuit board, may be formed on the mask ROM area, and may be disposed on the internal bus. In this event, the ROM connecting terminals and the bus connecting terminals are electrically connected to each other using wire bonding technique.

Abstract: A package may include a semiconductor chip mounted on a film substrate. A method of manufacturing the same may involve providing a semiconductor chip. The semiconductor chip may include recesses and bumps. A film substrate including a through hole may be provided. The semiconductor chip may be inserted into the through hole of the film substrate. Circuit wires may be formed on the film substrate to contact the bumps of the semiconductor chip.

Abstract: A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to have a tailored stress differential along its cross-section. A lower microspring may be made to push up against an upper microspring to provide increased contact force, or push down against a substrate to ensure release during manufacture. The microsprings may be provided with similar stress differentials or opposite stress differentials to obtain desired microspring profiles and functionality. Microsprings may also be physically connected at their distal ends for increased contact force. The microsprings may be formed of electrically conductive material or coated with electrically conductive material for probe card and similar applications.

Abstract: A semiconductor device which uses a semiconductor element having main current input/output electrodes, one and the other of which are extended up to a one surface and a remaining surface of a semiconductor chip respectively for causing one of the input/output electrodes to be contacted with a conductive layer of a insulating substrate, whereby the semiconductor element is supported on or above the insulating substrate. A conductive strip which is made of a composite material of carbon and aluminum or a composite material of carbon and copper is used for connection between the remaining input/output electrode of the semiconductor chip and the conductive layer of the insulating substrate.

Abstract: A semiconductor device package incorporating a connector that reduces manufacturing operations and enables efficient manufacturing. The semiconductor device package includes a primary molded product and a secondary molded product. The primary molded product includes a semiconductor device, a lead connected to the semiconductor device, and a plug terminal formed by at least part of the lead. The primary molded product envelops the semiconductor device and part of the lead in a first resin material. The secondary molded product envelops the primary molded product in a second resin material and includes a connector guide surrounding the plug terminal and used to guide insertion of a holder holding a socket terminal connectable to the plug terminal.

Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which a pad is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; a metal layer formed on the pad, the metal layer being less oxidizable than the pad; an insulating section formed of resin adjacent to the chip component; and an interconnect which is formed to extend from above the metal layer, over the insulating section and to above the interconnect pattern.

Abstract: A semiconductor apparatus (1) includes a semiconductor device (2), a first lead (3) having an electrode for connection with a source electrode (S) of the semiconductor device (2), a second lead (4) having an electrode for connection with a gate electrode (G) of the semiconductor device (2), a third lead (5) having an electrode for connection with a drain electrode (D) of the semiconductor device (2), and a strap member (6) covered with a metallic film for electrical interconnection between the drain electrode (D) of the semiconductor device (2) and the electrode of the third lead (5).

Abstract: A connector layout for arranging a plurality of parallel electrical connectors between two electronic devices. In one device, each connector has a strip connected to a bump pad. The bump pad is superimposed on and electrically connected to a bump pad on the other device. Each strip has a certain required strip width and each bump pad has a certain required pad width. The connectors are grouped into a group of three or more. Within each group, a strip is connected to a bump pad along one side edge thereof, and the bump pads are offset in two directions such that after the bump pads are superimposed, the pattern of the connected connectors in each group of connectors resembles a plurality of zigzag paths offset to maintain a constant gap between two strips. As such, the gap between two connectors can be minimized.

Abstract: A manufacturing method for a semiconductor device includes a hole portion formation step for forming hole portions whose entire width is substantially identical to the width of the opening portion in a part of the active surface side of the substrate on which electronic components are formed, a curved surface formation step for curving the bottom surface of the hole portion while maintaining the width of the bottom surface in the hole portions substantially identical to the width of the opening portion, a connecting terminal formation step for forming connecting terminals that serve as the external electrodes of the electronic circuits by burying metal in the hole portions, and an exposure step for exposing a part of the connecting terminals by carrying out processing on the back surface of the substrate.

Abstract: A hybrid integrated circuit device of the present invention includes: a circuit board having a front surface subjected to an insulation process; a conductive pattern formed on the front surface of the circuit board; a circuit element placed at a desired position on the conductive pattern and electrically connected to the conductive pattern; and a plurality of leads fixed to the conductive pattern and led to the outside. End portions of the leads which are led to the outside extend approximately parallel to the circuit board in a plane different from that of the front surface of the circuit board.

Abstract: A thin-film device incorporates: a substrate; an insulating layer, a lower conductor layer, a dielectric film, an insulating layer, an upper conductor layer and a protection film that are stacked in this order on the substrate; and four terminal electrodes. The four terminal electrodes touch part of end faces of the upper conductor layer, and part of the top surface of the upper conductor layer contiguous to the end faces. The protection film has four concave portions, each of which has a shape that is recessed inward from the edge of the protection film except portions thereof corresponding to these concave portions. The four concave portions expose respective portions of the top surface of the upper conductor layer that touch the four terminal electrodes. The four concave portions accommodate respective portions of the four terminal electrodes.