Abstract: A device with a beam structure includes a substrate, an anchor and a cavity which are provided on and over the substrate, respectively, and a beam structure which is provided on the anchor and over the cavity, extends in a first direction and includes a plurality of convex portions and a plurality of concave portions, each of the convex portions having such a stress gradient as to provide a convex warp, and each of the concave portions having such a stress gradient as to provide a concave warp. The convex portions and the concave portions are alternately repeatedly arranged.

Abstract: Methods of manufacturing an IC chip in portions for later combining and a related structure are disclosed. In one embodiment, the method includes: fabricating a first portion of the IC chip, the first portion including a structure from a selected level of back-end-of-line (BEOL) processing up to an end of the BEOL processing, the first portion providing a specific functionality when combined with a second portion of the IC chip, fabricating the second portion of the IC chip, the second portion including a structure from a device level of the IC chip up to the selected level of the BEOL processing, the second portion having structure providing generic IC chip functionality. The fabrication of the portions may occur at a single location or different locations, and the combining may occur at the same location or different location as one or more of the fabrication processes.

Abstract: A signal transfer film includes a base film, a lead line formed on the base film and a passivation layer protecting the lead line. The passivation layer includes a nonlinear edge portion formed at a boundary region between the lead line and the passivation layer. The nonlinear edge portion of the passivation layer disperses a stress concentrated to the boundary region in various directions when the base film is bent. Thus, the signal transfer film may prevent breaking of the lead line, thereby enhancing yield thereof.

Abstract: Stackable integrated circuit devices include an integrated circuit die having interconnect pads on an active (front) side, the die having a front side edge at the conjunction of the front side of the die and a sidewall of the die, and a back side edge at the conjunction of back side of the die and the sidewall; the die further includes a conductive trace which is electrically connected to an interconnect pad and which extends over the front side edge of the die. In some embodiments the conductive trace further extends over the sidewall, and, in some such embodiments the conductive trace further extends over the back side edge of the die, and in some such embodiments the conductive trace further extends over the back side of the die. One or both of the die edges may be chamfered. Also, methods for making such a device. Also, assemblies including such a device electrically interconnected to underlying circuitry (e.g.

Abstract: Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups.

Abstract: Provided is a semiconductor device which is small in size and in which the deformation of leads is prevented at the time of wire-bonding. The semiconductor device includes: an island; a semiconductor element mounted on the bottom surface of the island; leads provided close to the island; and a sealing resin for integrally sealing these constituents. Moreover, in the semiconductor device according to the present invention, electrodes on the semiconductor element are bonded to the leads provided adjacent to a side of the island, the side not provided with leads which extends continuously from the island.

Abstract: The present invention provides an electronic packaging process. The surface of the chip carrier includes at least a chip attachment region and a film attachment region adjacent to the chip attachment region. At least a baffle is formed on the surface of the chip carrier, between the chip attachment region and the film attachment region. After attaching the thin film to the film attachment region of the chip carrier through an affixture layer, the chip is electrically and physically connected to the chip attachment region of the chip carrier through an adhesive layer. The baffle can effectively prevent the gas that is released from the adhesive layer from damaging the bonding between the thin film and the affixture layer. Therefore, almost no bubbles are formed and good electrical connection between the thin film and the affixture layer is maintained.

Abstract: In certain embodiments, a leadframe structure for forming one or more integrated circuit packages includes a number of adjacent substantially parallel lead bars adapted to receive a die associated with an integrated circuit at one or more of the lead bars such that the one or more lead bars extend from opposite sides of the die. The leadframe structure also includes one or more support structures (e.g. lead support bars 26) adapted to help hold the lead bars together.

Abstract: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, at least two leads, and at least two bond wires. Each of the leads may have a reduced-thickness inner length adjacent terminals of the microelectronic component and a body having an outer surface spaced farther from the microelectronic component than a bond surface of the inner length. Each of the bond wires couples the microelectronic component to one of the leads and has a maximum height outwardly from the microelectronic component that is no greater than the height of the outer surface of the lead.

Abstract: A planarizing method performed on a non-planar wafer involves forming electrically conductive posts extending through a removable material, each of the posts having a length such that a top of each post is located above a plane defining a point of maximum deviation for the wafer, concurrently smoothing the material and posts so as to form a substantially planar surface, and removing the material. An apparatus includes a non planar wafer having contacts thereon, the wafer having a deviation from planar by an amount that is greater than a height of at least one contact on the wafer, and a set of electrically conductive posts extending away from a surface of the wafer, the posts each having a distal end, the distal ends of the posts collectively defining a substantially flat plane.

Abstract: A semiconductor package assembly and method for electrically isolating modules, having a capacitor within the semiconductor package assembly. The package assembly and method are suitable for electrically isolating modules according to IEEE 1394.

Abstract: The present invention provides a printed circuit board having an area of non-resist portion, where each non-resist portion expands gradually toward the back end of a land array in the dipping direction A. Thus the area of solder deposition also expands in the region of the land array, thereby excessive solder does not remain up to the back end of the land array, and resultantly the amount of solder buildup at the backside in the dipping direction A can be reduced. Further, the present invention makes it unnecessary to dispose a dummy land for the prevention of solder buildup at the backmost portion of the land array, and thus the space used for a dummy land can be utilized effectively.

Abstract: A semiconductor package includes a semiconductor chip electrically connected to a plurality of leads arranged at the periphery of the semiconductor chip wherein each of the leads is bent to have a first portion exposed from the upper surface of the semiconductor package and a second portion exposed from the lower surface of the semiconductor package. Both of the first portion and the second portion of each lead can be utilized for making external electrical connection.

Abstract: A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions.

Abstract: A method of fabricating a MEMS element includes forming a MEMS element by forming a circuit layer on an element layer of an SOI substrate that is formed by laminating on a substrate, a first insulation layer and the element layer, and forming a second insulation layer including a conductive beam electrically connected to the circuit layer on the element layer on which the circuit layer is not formed; first removing a part of the second insulation layer and a part of the element layer by anisotropic etching; second removing by forming an opening reaching to the element layer in the second insulation layer, and removing the element layer located below the conductive beam through the opening by isotropic etching; and third removing by removing the second insulation layer to expose the conductive beam, and removing the first insulation layer located below the conductive beam.

Abstract: A semiconductor device, wherein a first metallic member is bonded to a first electrode of a semiconductor element via a first metallic body containing a first precious metal, and a second metallic member is bonded to a second electrode via a second metallic body containing a second precious metal.

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract: A heating apparatus and method for heating a semiconductor device during bonding of electrical contacts onto the device is provided, which includes a heating plate that is provided for heating the semiconductor device and a layer of compliant material extending over at least a portion of the heating plate for mounting the semiconductor device. A holding mechanism secures the semiconductor device on the layer of compliant material during bonding of electrical contacts onto the semiconductor device while it is being heated by the heating plate.

Abstract: In a method according to the present invention, a substrate thinning process is performed on a bumped substrate prior to the ultimate solder reflow process to heal bump defects caused by the substrate thinning process. Concurrently, the risk of substrate breakage is reduced compared to the prior art process since the number of process steps, requiring handling of thinned substrates, is reduced.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: An assembly includes a structure, a plurality of terminals and a plurality of compliant pads disposed between said terminals and said structure. The terminals are aligned with at least some of said pads, with the pads providing a standoff between the structure and the terminals. The compliant pads are preferably made of a non-conductive material such as a silicone elastomer.

Abstract: A process includes annealing one or more plated conductive leads at a predetermined temperature. The one or more plated conductive leads are plated with one or more layers, where each layer comprises a material. The predetermined temperature is greater than or equal to approximately a melting point of one of the materials. The annealing can reduce growth formations, such as whiskers, on the one or more conductive leads. Lead frames and other devices having plated conductive leads may be subjected to the process, and the resultant plated conductive leads will have fewer growth formations than plated conductive leads not subjected to the process. The plated conductive leads may be trimmed and formed prior to or after the anneal.

Abstract: A semiconductor die has a top surface and a bottom surface. A source contact, a gate contact and a gate finger are formed on the top surface. The source contact has a slit and the gate finger is disposed in the slit of the source contact. A drain contact is formed on the bottom surface. An insulation layer is formed on the top surface to cover the gate finger. A semiconductor device includes the semiconductor die and an electrically conductive sheet attached to the source contact with a conductive paste. The electrically conductive sheet has a concave portion disposed above the gate finger. An air gap is formed between the concave portion and the insulation layer. By including the air gap, the stress that occurs between the electrically conductive sheet and the insulation layer can be reduced, thus an occurrence of a crack in the insulation layer can be prevented.

Abstract: In a lead-frame configuration (60), a module (70) and a data carrier (72), two connecting plates (12, 13) of the module (70), which are each intended for connection to a connecting contact or bump (47, 48) of a chip (41), are connected to a reinforcement film (66, 71) formed from a fiber-reinforced film of plastics material by means of a layer (73) of an adhesive that is particularly well suited to transmitting shear forces, in which case there is additionally provided in an advantageous further embodiment, on the reinforcement film (66, 71), at least one further layer (74, 75, 76) that is able to serve for protecting, damping or fastening purposes.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature.

Abstract: Arrangements are used for minimizing signal path discontinuities.

Abstract: A semiconductor chip is mounted on a tab, leads alternately arranged around the tab are electrically connected to electrodes of the semiconductor chip via bonding wires, and encapsulating resin encapsulates the semiconductor chip and bonding wires. The lower surfaces of the leads are exposed at the outer periphery of the back surface of the encapsulating resin to form external terminals. The lower surfaces of the leads are exposed at the back surface of the encapsulating resin located inwardly of the lower exposed surface of the leads to form external terminals. The cut surfaces of the leads are exposed at the cut surfaces of the encapsulating resin, while upper exposed surfaces of the leads are exposed from the encapsulating resin portion which is proximate to the cut surfaces thereof. Each of the upper exposed surfaces of the leads has a width smaller than the width of each of the lower exposed surfaces.

Abstract: A semiconductor device which permits reduction in the number of pins and in size thereof is provided.

Abstract: A circuit device is provided comprising leads and electrical circuitry. The circuit device has a first semiconductor element, a second semiconductor element, first leads electrically connected to the first semiconductor element or the second semiconductor element via fine metal wires and having an end thereof extending outwardly, second leads electrically connected via metal wires to both the first semiconductor element and the second semiconductor element to thus electrically connect the first and second semiconductor elements.

Abstract: A semiconductor chip, having an active surface including a peripheral area and a central area, presents a connection area formed on a portion of the peripheral area. The semiconductor chip includes output pads formed in the peripheral area of the active surface and input pads formed in the central area of the active surface. The input pads may be connected to wiring patterns of a TAB tape passing over the connection area.

Abstract: A semiconductor device comprises: a semiconductor chip; an extension portion formed in contact with the side surfaces so as to surround the semiconductor chip; an insulating film formed on a surface of the extension portion and the semiconductor chip; each of a plurality of wiring patterns electrically connected to each electrode pad, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided over the wiring patterns in a region including the upper side of the extension portion.

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract: A surface mounting structure and a packaging method thereof comprises a chip, a first conducting wire and a second conducting wire. The two conducting wires instead of lead frame architecture of the prior art is that the lead frame and a bridge jumper connected with N junction and P junction instead of the two conducting wires. The two conducting wires are drawn out from a bottom of a package, and are pressed and bent to original surface of the surface mounting pins so as to increase space utilization rate. Thereby it is to improve a complicated lead frame architecture of the prior art, increase use space and simplify system design.

Abstract: A semiconductor package includes a uniform thin insulating film covering the internal circuit formed on a silicon substrate. A plurality of thick island insulating films are formed underlying respective pad electrodes, which connect the internal circuit to an external circuit. The silicon substrate is polished from the bottom to have a thickness less than 0.6 mm. The thick island insulating films reduces an electrostatic capacitance of the pad electrodes to reduce the propagation delay of a signal passing through the pad electrodes.

Abstract: A method of modifying a semiconductor device to provide electrical parameter monitoring. The device includes a semiconductor die and a package substrate. The substrate includes a conductive plane. The die is connected to the plane via a plurality of connection structures. The method includes disconnecting a first one of the connection structures from the plane, and connecting the first connection structure to an external package connection, thereby providing a capability to monitor an electrical parameter of the die via the external package connection.

Abstract: A semiconductor package mainly includes a semiconductor chip and a plurality of L-shaped leads arranged at the periphery of the semiconductor chip. Each of the L-shaped leads has an inner lead portion exposed out of the lower surface of the semiconductor package and an outer lead portion formed substantially parallel to and adjacent to one of the side surfaces of the semiconductor package. The semiconductor chip has a plurality of bonding pads electrically coupled to the inner lead portions of the L-shaped leads. The semiconductor package is provided with a package body formed over the semiconductor chip and the inner lead portions of the L-shaped leads.

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract: A microelectronic component comprising a dielectric layer having an opening and leads extending across the opening is disclosed. The leads have an offset portion. A method of making a microelectronic assembly comprises connecting each of the leads to a contact on a microelectronic element. A semiconductor chip assembly has a microelectronic component with an opening and leads extending across the opening. The leads are connected to contacts on a semiconductor chip and have at least one twisted portion.

Abstract: A circuit board comprises a dielectric layer, a net of first power supply lines for providing a first reference voltage plane and a net of second power supply lines for providing a second reference voltage plane. The nets of first and second power supply lines are arranged such that first power supply lines and second power supply lines are alternately arranged in the direction of a first surface of the dielectric layer.

Abstract: A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also restrains the occurrence of disconnection caused by a wiring layer being crushed. In the semiconductor device, the sealing resin for sealing the semiconductor chip is molded on the circuit board that has a plurality of wiring patterns and a solder resist for insulatively covering the wiring patterns formed on the front surface thereof, the interval of the wiring patterns is set to range from 50% to 200% of its adjacent interval in a molding line area of the sealing resin.

Abstract: A and method for fabricating a warpage-preventive circuit board is provided, wherein a plurality of conductive traces are formed on a surface of an electrically-insulative core layer, and a plurality of discontinuous dummy circuit regions are disposed on the surface of the electrically-insulative core layer at area free of the conductive traces, with adjacent dummy circuit regions being spaced apart by at least a chink. During a high-temperature fabrication process, the dummy circuit regions help reduce thermal stress and the chinks absorb thermal expansion of the dummy circuit regions, to thereby prevent warpage of the circuit board and cracks of a chip mounted on the circuit board, such that yield and reliability of fabricated semiconductor devices can be improved.

Abstract: A semiconductor device comprises a semiconductor element and a conductive member. The semiconductor element has a semiconductor substrate having first and second major surfaces; a semiconductor layer formed on the first major surface of the semiconductor substrate; a plurality of trenches formed on the semiconductor layer, the trenches being parallel to each other and extending to a first direction; filling material filling the trenches; a first electrode pad provided on the semiconductor layer and connected electrically to a first major electrode; a second major electrode provided on the second major surface; and a gate electrode pad provided on the semiconductor layer and connected to a gate electrode which controls conduction between the first major electrode and the second major electrode. The conductive member is connected to at least one of the first electrode pad and the gate electrode pad via a first contact area.

Abstract: A semiconductor chip package includes an IC chip and a tape circuit substrate. The tape circuit substrate has a base film and a plurality of beam leads formed on the base film. One end portion of each beam lead extends from the base film, and the extended portion has a widthwise wavy portion. The widthwise wavy portion may be, for example, semicircular shaped, S-shaped or zig-zag shaped. The IC chip has chip pads formed on a top surface thereof.

Abstract: An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternatively, a connector may contact a portion of the conductive trace to make contact therewith.

Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.

Abstract: A semiconductor chip with test pads and a tape carrier package using the same are provided. The tape carrier package comprises a semiconductor chip. The semiconductor chip has an active surface and a back surface. The active surface has a main circuit area having integrated circuits and a peripheral area having chip pads connected to the integrated circuits. The semiconductor chip has test pads connected to the chip pads for testing the characteristics of the integrated circuits. The tape carrier package further comprises a tape wiring substrate having an insulating base film, wiring patterns formed on the insulating base film, leads formed integrally with the wiring patterns and dummy leads electrically isolated from the wiring patterns, and bumps connecting the chip pads to the corresponding leads and the test pads to the dummy leads.

Abstract: A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provided in a membrane defined by that portion of the layer below which the semiconductor substrate has been removed. A heat conducting and electrically insulating layer is applied to the bottom surface of the membrane. The heat conducting and electrically insulating layer has a thermal conductivity that is higher than the thermal conductivity of the membrane so that the heat conducting and electrically insulating layer allows heat to pass from the active region into the heat conducting and electrically insulating layer during normal operation of the device.

Abstract: A semiconductor package that includes two power semiconductor dies, such as power MOSFET dies, including vertical conduction MOSFETs, arranged in a half-bridge configuration is disclosed. The package may be mounted on a split conductive pad including two isolated die pads, each die pad being electrically connected to the second power electrode of the die that is on it. The split pad may include several conductive leads, including at least one output lead electrically connected to a first electrode of the first semiconductor die on the same side of the die as the control electrode and to the second electrode of the second die located on the opposite side of the second die from the control electrode.

Abstract: A method of fabricating a lead frame for a semiconductor device having a semiconductor chip resin-sealed therein. The lead frame includes a lead to be electrically connected to the semiconductor chip within sealing resin and to be sealed into the sealing resin such that at least a part of its mounting surface is exposed from the sealing resin. The method includes a lead forming step for forming the lead, and a side edge coining step for subjecting a side edge of a sealed surface, which is a surface on the opposite side of the mounting surface, of the lead to coining processing from the side of the sealed surface, to form a slipping preventing portion. The slipping preventing portion is to project sideward from the lead and to have a slipping preventing surface between the mounting surface and the sealed surface of the lead.